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[v2,for-10.0,37/54] target/i386: Set default NaN pattern explicitly

Message ID 20241202131347.498124-38-peter.maydell@linaro.org
State Superseded
Headers show
Series fpu: Remove pickNaNMulAdd, default-NaN ifdefs | expand

Commit Message

Peter Maydell Dec. 2, 2024, 1:13 p.m. UTC
Set the default NaN pattern explicitly, and remove the ifdef from
parts64_default_nan().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/i386/tcg/fpu_helper.c   | 4 ++++
 fpu/softfloat-specialize.c.inc | 3 ---
 2 files changed, 4 insertions(+), 3 deletions(-)

Comments

Richard Henderson Dec. 2, 2024, 5:27 p.m. UTC | #1
On 12/2/24 07:13, Peter Maydell wrote:
> Set the default NaN pattern explicitly, and remove the ifdef from
> parts64_default_nan().
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/i386/tcg/fpu_helper.c   | 4 ++++
>   fpu/softfloat-specialize.c.inc | 3 ---
>   2 files changed, 4 insertions(+), 3 deletions(-)
> 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
> index c8bc5b7cfb3..e788fcd1b25 100644
> --- a/target/i386/tcg/fpu_helper.c
> +++ b/target/i386/tcg/fpu_helper.c
> @@ -181,6 +181,10 @@ void cpu_init_fp_statuses(CPUX86State *env)
>        */
>       set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
>       set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
> +    /* Default NaN: sign bit set, most significant frac bit set */
> +    set_float_default_nan_pattern(0b11000000, &env->fp_status);
> +    set_float_default_nan_pattern(0b11000000, &env->mmx_status);
> +    set_float_default_nan_pattern(0b11000000, &env->sse_status);
>   }
>   
>   static inline uint8_t save_exception_flags(CPUX86State *env)
> diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
> index d77404f0c47..452fe378cd2 100644
> --- a/fpu/softfloat-specialize.c.inc
> +++ b/fpu/softfloat-specialize.c.inc
> @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
>   #if defined(TARGET_SPARC) || defined(TARGET_M68K)
>           /* Sign bit clear, all frac bits set */
>           dnan_pattern = 0b01111111;
> -#elif defined(TARGET_I386) || defined(TARGET_X86_64)
> -        /* Sign bit set, most significant frac bit set */
> -        dnan_pattern = 0b11000000;
>   #elif defined(TARGET_HPPA)
>           /* Sign bit clear, msb-1 frac bit set */
>           dnan_pattern = 0b00100000;
diff mbox series

Patch

diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index c8bc5b7cfb3..e788fcd1b25 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -181,6 +181,10 @@  void cpu_init_fp_statuses(CPUX86State *env)
      */
     set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
     set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
+    /* Default NaN: sign bit set, most significant frac bit set */
+    set_float_default_nan_pattern(0b11000000, &env->fp_status);
+    set_float_default_nan_pattern(0b11000000, &env->mmx_status);
+    set_float_default_nan_pattern(0b11000000, &env->sse_status);
 }
 
 static inline uint8_t save_exception_flags(CPUX86State *env)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index d77404f0c47..452fe378cd2 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -139,9 +139,6 @@  static void parts64_default_nan(FloatParts64 *p, float_status *status)
 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
         /* Sign bit clear, all frac bits set */
         dnan_pattern = 0b01111111;
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
-        /* Sign bit set, most significant frac bit set */
-        dnan_pattern = 0b11000000;
 #elif defined(TARGET_HPPA)
         /* Sign bit clear, msb-1 frac bit set */
         dnan_pattern = 0b00100000;