| Message ID | 20241206-gs101-phy-lanes-orientation-phy-v4-0-f5961268b149@linaro.org |
|---|---|
| Headers | show |
| Series | USB31DRD phy updates for Google Tensor gs101 (orientation & DWC3 rpm) | expand |
Hi André, On Sat, 7 Dec 2024 at 22:03, Peter Griffin <peter.griffin@linaro.org> wrote: > > Hi André, > > On Fri, 6 Dec 2024 at 16:31, André Draszik <andre.draszik@linaro.org> wrote: > > > > To make USB runtime suspend work when a UDC has been bound, the phy > > needs to inform the USBDRD controller (DWC3) that Vbus and bvalid are > > gone, so that it can in turn raise the respective gadget interrupt with > > event == DWC3_DEVICE_EVENT_DISCONNECT, which will cause the USB stack > > to clean up, allowing DWC3 to enter runtime suspend. > > > > On e850 and gs101 this isn't working, as the respective signals are not > > directly connected, and instead this driver uses override bits in the > > PHY IP to set those signals. It currently forcefully sets them to 'on', > > so the above mentioned interrupt will not be raised, preventing runtime > > suspend. > > > > To detect that state, update this driver to act on the TCPC's > > orientation signal - when orientation == NONE, Vbus is gone and we can > > clear the respective bits. Similarly, for other orientation values we > > re-enable them. > > > > This makes runtime suspend work on platforms with a TCPC (like Pixel6), > > while keeping compatibility with platforms without (e850-96). > > > > With runtime suspend working, USB-C cable orientation detection now > > also fully works on such platforms, and the link comes up as Superspeed > > as expected irrespective of the cable orientation and whether UDC / > > gadget are configured and active. > > > > Signed-off-by: André Draszik <andre.draszik@linaro.org> > > As mentioned on the last patch, in my testing cable orientation > detection is working, but Pixel is detected as a superspeed device in > one orientation, and high speed device in the other orientation. So > you should either change the wording of the last paragraph in the > commit message (assuming you get the same results as me) or make it > detect as superspeed in both orientations. You can disregard this point, I had a typo in my test setup :( I just confirmed that it is detected as SuperSpeed in both orientations. Thanks, Peter
Hi, This series enables USB3 Type-C lane orientation detection and configuration on platforms that support this (Google gs101), and it also allows the DWC3 core to enter runtime suspend even when UDC is active. For lane orientation, this driver now optionally (based on DT) subscribes to the TCPC's lane orientation notifier and remembers the orientation to later be used during phy_init(). To enable DWC3 runtime suspend, the gadget needs to inform the core via dwc3_gadget_interrupt() with event type == DWC3_DEVICE_EVENT_DISCONNECT of a cable disconnect. For that to allow to happen, this driver therefore needs to stop forcing the Vbus and bvalid signals to active and instead change their state based on actual conditions. The same TCPC notifier is used to detect this, and program the hardware accordingly. That signal state is based on advice given by Thinh in https://lore.kernel.org/all/20240813230625.jgkatqstyhcmpezv@synopsys.com/ Both changes together now allow cable orientation detection to work, as the DWC3 will now call phy_exit() on cable disconnect, and we can reprogram the lane mux in phy_init(). On top of that, there are some small related cleanup patches. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- Changes in v4: - separate out patch 5 'phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit()' from this series, as a stable patch shouldn't be buried inside a series like this (Greg) Link: https://lore.kernel.org/all/20241205-gs101-usb-phy-fix-v4-1-0278809fb810@linaro.org/ - Link to v3: https://lore.kernel.org/r/20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org Changes in v3: - patches 1 & 2: update as per Rob's suggestions - patch 7 & 8: drop init to -1 of phy_drd->orientation (Vinod) - patch 7: avoid an #ifdef - Link to v2: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-phy-v2-0-40dcf1b7670d@linaro.org Changes in v2: - squash patches #2 and #3 from v1 to actually disallow orientation-switch on !gs101 (not just optional) (Conor) - update bindings commit message to clarify that the intention for the driver is to work with old and new DTS (Conor) - add cc-stable and fixes tags to power gating patch (Krzysztof) - fix an #include and typo (Peter) - Link to v1: https://lore.kernel.org/r/20241127-gs101-phy-lanes-orientation-phy-v1-0-1b7fce24960b@linaro.org --- André Draszik (7): dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties phy: exynos5-usbdrd: convert to dev_err_probe phy: exynos5-usbdrd: fix EDS distribution tuning (gs101) phy: exynos5-usbdrd: gs101: configure SS lanes based on orientation phy: exynos5-usbdrd: subscribe to orientation notifier if required phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+) .../bindings/phy/samsung,usb3-drd-phy.yaml | 21 ++- drivers/phy/samsung/Kconfig | 1 + drivers/phy/samsung/phy-exynos5-usbdrd.c | 202 ++++++++++++++++----- 3 files changed, 182 insertions(+), 42 deletions(-) --- base-commit: c245a7a79602ccbee780c004c1e4abcda66aec32 change-id: 20241127-gs101-phy-lanes-orientation-phy-29d20c6d84d2 Best regards,