| Message ID | 20241212-x1e80100-qcp-sdhc-v4-0-a74c48ee68a3@linaro.org |
|---|---|
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: Describe SDCs and enable support on QCP | expand |
On 24-12-12 18:34:37, Konrad Dybcio wrote: > On 12.12.2024 5:50 PM, Abel Vesa wrote: > > The X Elite platform features two SDHC v5 controllers. > > > > Describe the controllers along with the pin configuration in TLMM > > for the SDC2, since they are hardwired and cannot be muxed to any > > other function. The SDC4 pin configuration can be muxed to different > > functions, so leave those to board specific dts. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 142 +++++++++++++++++++++++++++++++++ > > 1 file changed, 142 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..1584df66ea915230995f0cf662cde813f4ae02a1 100644 > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > @@ -4094,6 +4094,108 @@ lpass_lpicx_noc: interconnect@7430000 { > > #interconnect-cells = <2>; > > }; > > > > + sdhc_2: mmc@8804000 { > > + compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; > > + reg = <0 0x08804000 0 0x1000>; > > + > > + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "hc_irq", "pwr_irq"; > > + > > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > > + <&gcc GCC_SDCC2_APPS_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>; > > + clock-names = "iface", "core", "xo"; > > + iommus = <&apps_smmu 0x520 0>; > > + qcom,dll-config = <0x0007642c>; > > + qcom,ddr-config = <0x80040868>; > > + power-domains = <&rpmhpd RPMHPD_CX>; > > + operating-points-v2 = <&sdhc2_opp_table>; > > + > > + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, > > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; > > The comment regarding ICC defines from v3 still stands Urgh, missed that one. Will respin next week with that addressed as well. > > the rest of the patch looks good > > Konrad Thanks for reviewing! Abel
The X1E80100 has two SDHC controllers (called SDC2 and SDC4). Describe both of them and enable the SDC2 on QCP. This brings SD card support for the microSD port on QCP. The SDC4 is described but there is no device outthere yet that makes use of it, AFAIK. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- Changes in v4: - Squashed the pinconf for SDC2 into the patch that describes the controllers. - Reworded the commit messages a bit. - Link to v3: https://lore.kernel.org/r/20241022-x1e80100-qcp-sdhc-v3-0-46c401e32cbf@linaro.org Changes in v3: - Reordered the default and sleep pinconfs. Also the bias and drive-strength properties. As per Konrad's suggestion. - Link to v2: https://lore.kernel.org/r/20241014-x1e80100-qcp-sdhc-v2-0-868e70a825e0@linaro.org Changes in v2: - rebased on next-20241011 - dropped the bindings schema update patch - dropped the sdhci-caps-mask properties from both controllers as SDR104/SDR50 are actually supported - Link to v1: https://lore.kernel.org/r/20241008-x1e80100-qcp-sdhc-v1-0-dfef4c92ae31@linaro.org --- Abel Vesa (2): arm64: dts: qcom: x1e80100: Describe the SDHC controllers arm64: dts: qcom: x1e80100-qcp: Enable SD card support arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 20 +++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 142 ++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+) --- base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07 change-id: 20241007-x1e80100-qcp-sdhc-15c716dad946 Best regards,