| Message ID | 20241217153249.5712-1-pshete@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] pinctrl-tegra: Add config property GPIO mode | expand |
Hi Prathamesh, thanks for your patch! a question here: On Tue, Dec 17, 2024 at 4:33 PM Prathamesh Shete <pshete@nvidia.com> wrote: > The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing > system: > - When set to 1, the pin operates in SFIO mode, controlled by the > pin's assigned special function. > - When set to 0, the pin operates as a general-purpose GPIO. > > This SFIO/GPIO select bit that is set for a given pin is not displayed, > adding the support to retrieve this information from the > pinmux set for each pin. > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> If the description is correct, why is this bit not unconditionally set in tegra_pinctrl_gpio_request_enable() and unconditionally cleared in tegra_pinctrl_gpio_disable_free() ? Yours, Linus Walleij
On Fri, Dec 20, 2024 at 02:51:43PM +0100, Linus Walleij wrote: > Hi Prathamesh, > > thanks for your patch! > > a question here: > > On Tue, Dec 17, 2024 at 4:33 PM Prathamesh Shete <pshete@nvidia.com> wrote: > > > The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing > > system: > > - When set to 1, the pin operates in SFIO mode, controlled by the > > pin's assigned special function. > > - When set to 0, the pin operates as a general-purpose GPIO. > > > > This SFIO/GPIO select bit that is set for a given pin is not displayed, > > adding the support to retrieve this information from the > > pinmux set for each pin. > > > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > > If the description is correct, why is this bit not unconditionally > set in > tegra_pinctrl_gpio_request_enable() > and unconditionally cleared in > tegra_pinctrl_gpio_disable_free() > ? Sorry for the late reply. This bit is already being set during .gpio_request_enable() and .gpio_disable_free(). My understanding is that this patch is primarily for making this available in debugfs. I suppose we could make that clearer by not making this part of the standard pinconfig options, but rather put it into a "read-only" set configs? Thierry
Hi Linus, Can you please help check on this and provide feedback Thanks Prathamesh. On 23/01/25, 2:31 PM, "Thierry Reding" <thierry.reding@gmail.com> wrote: On Fri, Dec 20, 2024 at 02:51:43PM +0100, Linus Walleij wrote: > Hi Prathamesh, > > thanks for your patch! > > a question here: > > On Tue, Dec 17, 2024 at 4:33 PM Prathamesh Shete <pshete@nvidia.com <mailto:pshete@nvidia.com>> wrote: > > > The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing > > system: > > - When set to 1, the pin operates in SFIO mode, controlled by the > > pin's assigned special function. > > - When set to 0, the pin operates as a general-purpose GPIO. > > > > This SFIO/GPIO select bit that is set for a given pin is not displayed, > > adding the support to retrieve this information from the > > pinmux set for each pin. > > > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com <mailto:pshete@nvidia.com>> > > If the description is correct, why is this bit not unconditionally > set in > tegra_pinctrl_gpio_request_enable() > and unconditionally cleared in > tegra_pinctrl_gpio_disable_free() > ? Sorry for the late reply. This bit is already being set during .gpio_request_enable() and .gpio_disable_free(). My understanding is that this patch is primarily for making this available in debugfs. I suppose we could make that clearer by not making this part of the standard pinconfig options, but rather put it into a "read-only" set configs? Thierry
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 9523b93008d0..46728f19fa8e 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -96,6 +96,7 @@ static const struct cfg_param { {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, + {"nvidia,gpio-mode", TEGRA_PINCONF_PARAM_GPIO_MODE}, }; static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, @@ -476,6 +477,16 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *bit = g->drvtype_bit; *width = 2; break; + case TEGRA_PINCONF_PARAM_GPIO_MODE: + if (pmx->soc->sfsel_in_mux) { + *bank = g->mux_bank; + *reg = g->mux_reg; + *bit = g->sfsel_bit; + *width = 1; + } else { + *reg = -EINVAL; + } + break; default: dev_err(pmx->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index b97136685f7a..a47ac519f3ec 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -60,6 +60,8 @@ enum tegra_pinconf_param { TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, /* argument: Integer, range is HW-dependant */ TEGRA_PINCONF_PARAM_DRIVE_TYPE, + /* argument: Boolean */ + TEGRA_PINCONF_PARAM_GPIO_MODE, }; enum tegra_pinconf_pull {
The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing system: - When set to 1, the pin operates in SFIO mode, controlled by the pin's assigned special function. - When set to 0, the pin operates as a general-purpose GPIO. This SFIO/GPIO select bit that is set for a given pin is not displayed, adding the support to retrieve this information from the pinmux set for each pin. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> --- drivers/pinctrl/tegra/pinctrl-tegra.c | 11 +++++++++++ drivers/pinctrl/tegra/pinctrl-tegra.h | 2 ++ 2 files changed, 13 insertions(+)