| Message ID | 20250109133513.20151-1-kyrie.wu@mediatek.com |
|---|---|
| Headers | show |
| Series | Enable jpeg enc & dec multi-hardwares for MT8196 | expand |
Hi, Le jeudi 09 janvier 2025 à 21:35 +0800, kyrie.wu a écrit : > This series adds support for mt8196 multi-hardwares jpeg enc & dec, > by first adding mt8196 jpegdec and jpegenc compatible to install > kernel driver. Add smmu setting to support smmu and iommu at the > same time. > Secondly refactor buffer and clock setting to support multi-hw jpeg > working. > Lastly, fix some bugs, including resolution change handleing, stop > streaming sw flow and others. > > This series has been tested with MT8196 tast test. > Encoding and decoding worked for this chip. > > Patches 1-3 Adds jpeg encoder and decoder compatible. > Patches 4 add jpeg smmu sid setting. > Patches 5 fix jpeg hw count setting to support different chips. > Patches 6 refactor jpeg buffer payload setting to handle buffer > size bug while resolution changed. > Patches 7 reconstruct jpeg dst buffer layout. > Patches 8 fix multi-core stop streaming flow > Patches 9 refactor multi-core clk suspend/resume setting > Patches 10 fix decoding buffer number setting timing issue > Patches 11 refactor decoding resolution change operation > Patches 12 fix remove buffer operation > > --- > This series patches dependent on: > [1] > https://patchwork.kernel.org/project/linux-mediatek/patch/20240808092555.12999-1-jianhua.lin@mediatek.com/ > > kyrie.wu (11): would you mind fixing the --author in your configuration, write your name instead of your user name. UT8 is allowed, many people will use a ASCI spelling (some approximation) and then add their real name in parenthesis. regards, Nicolas > dt-bindings: mediatek: Add mediatek, mt8196-jpgdec compatible > dt-bindings: mediatek: Add mediatek, mt8196-jpgenc compatible > media: mediatek: jpeg: add jpeg compatible > media: mediatek: jpeg: add jpeg smmu sid setting > media: mediatek: jpeg: fix jpeg hw count setting > media: mediatek: jpeg: refactor jpeg buffer payload setting > media: mediatek: jpeg: refactor jpeg dst buffer layout > media: mediatek: jpeg: fix stop streaming flow for multi-core > media: mediatek: jpeg: refactor multi-core clk suspend and resume > setting > media: mediatek: jpeg: fix decoding buffer number setting timing issue > media: mediatek: jpeg: refactor decoding resolution change operation > media: mediatek: jpeg: fix remove buffer operation for multi-core > > ....yaml => mediatek,multi-core-jpegdec.yaml} | 10 +- > ....yaml => mediatek,multi-core-jpegenc.yaml} | 10 +- > .../platform/mediatek/jpeg/mtk_jpeg_core.c | 126 ++++++++++++------ > .../platform/mediatek/jpeg/mtk_jpeg_core.h | 17 ++- > .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 116 +++++++++++++++- > .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h | 4 + > .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 113 +++++++++++++++- > .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.h | 4 + > 8 files changed, 343 insertions(+), 57 deletions(-) > rename Documentation/devicetree/bindings/media/{mediatek,mt8195-jpegdec.yaml => mediatek,multi-core-jpegdec.yaml} (95%) > rename Documentation/devicetree/bindings/media/{mediatek,mt8195-jpegenc.yaml => mediatek,multi-core-jpegenc.yaml} (94%) >
On Thu, 2025-01-09 at 09:06 -0500, Nicolas Dufresne wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > Hi, > > Le jeudi 09 janvier 2025 à 21:35 +0800, kyrie.wu a écrit : > > This series adds support for mt8196 multi-hardwares jpeg enc & dec, > > by first adding mt8196 jpegdec and jpegenc compatible to install > > kernel driver. Add smmu setting to support smmu and iommu at the > > same time. > > Secondly refactor buffer and clock setting to support multi-hw jpeg > > working. > > Lastly, fix some bugs, including resolution change handleing, stop > > streaming sw flow and others. > > > > This series has been tested with MT8196 tast test. > > Encoding and decoding worked for this chip. > > > > Patches 1-3 Adds jpeg encoder and decoder compatible. > > Patches 4 add jpeg smmu sid setting. > > Patches 5 fix jpeg hw count setting to support different chips. > > Patches 6 refactor jpeg buffer payload setting to handle buffer > > size bug while resolution changed. > > Patches 7 reconstruct jpeg dst buffer layout. > > Patches 8 fix multi-core stop streaming flow > > Patches 9 refactor multi-core clk suspend/resume setting > > Patches 10 fix decoding buffer number setting timing issue > > Patches 11 refactor decoding resolution change operation > > Patches 12 fix remove buffer operation > > > > --- > > This series patches dependent on: > > [1] > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240808092555.12999-1-jianhua.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!mJmYHl_SoomWL8beP_5XuUZ0bpvhI_TqJVcDjN5mkxOnrNPnEkfu8-JdTfxx3Q6SZIEBU-3CvddOw-3uio1MxA$ > > > > kyrie.wu (11): > > would you mind fixing the --author in your configuration, write your > name > instead of your user name. UT8 is allowed, many people will use a > ASCI spelling > (some approximation) and then add their real name in parenthesis. > > regards, > Nicolas Dear Nicolas, I have resent a new version, but I didn't view this mail in time. Thanks for your advice, and I will fix it in the next version. Thanks. Regards, Kyrie. > > > dt-bindings: mediatek: Add mediatek, mt8196-jpgdec compatible > > dt-bindings: mediatek: Add mediatek, mt8196-jpgenc compatible > > media: mediatek: jpeg: add jpeg compatible > > media: mediatek: jpeg: add jpeg smmu sid setting > > media: mediatek: jpeg: fix jpeg hw count setting > > media: mediatek: jpeg: refactor jpeg buffer payload setting > > media: mediatek: jpeg: refactor jpeg dst buffer layout > > media: mediatek: jpeg: fix stop streaming flow for multi-core > > media: mediatek: jpeg: refactor multi-core clk suspend and resume > > setting > > media: mediatek: jpeg: fix decoding buffer number setting timing > > issue > > media: mediatek: jpeg: refactor decoding resolution change > > operation > > media: mediatek: jpeg: fix remove buffer operation for multi-core > > > > ....yaml => mediatek,multi-core-jpegdec.yaml} | 10 +- > > ....yaml => mediatek,multi-core-jpegenc.yaml} | 10 +- > > .../platform/mediatek/jpeg/mtk_jpeg_core.c | 126 ++++++++++++ > > ------ > > .../platform/mediatek/jpeg/mtk_jpeg_core.h | 17 ++- > > .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 116 > > +++++++++++++++- > > .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h | 4 + > > .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 113 > > +++++++++++++++- > > .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.h | 4 + > > 8 files changed, 343 insertions(+), 57 deletions(-) > > rename Documentation/devicetree/bindings/media/{mediatek,mt8195- > > jpegdec.yaml => mediatek,multi-core-jpegdec.yaml} (95%) > > rename Documentation/devicetree/bindings/media/{mediatek,mt8195- > > jpegenc.yaml => mediatek,multi-core-jpegenc.yaml} (94%) > > > >
Il 09/01/25 14:35, kyrie.wu ha scritto: > Add a configuration to set jpeg dec & enc smmu sid > > Signed-off-by: kyrie.wu <kyrie.wu@mediatek.com> > --- > .../platform/mediatek/jpeg/mtk_jpeg_core.c | 6 ++++ > .../platform/mediatek/jpeg/mtk_jpeg_core.h | 11 +++++++ > .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 30 +++++++++++++++++-- > .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h | 4 +++ > .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 26 ++++++++++++++++ > .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.h | 4 +++ > 6 files changed, 78 insertions(+), 3 deletions(-) > > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > index c3ccc525d9fd..77b3bd6c4d3f 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > @@ -1655,6 +1655,9 @@ static void mtk_jpegenc_worker(struct work_struct *work) > jpeg_dst_buf->frame_num = ctx->total_frame_num; > ctx->total_frame_num++; > mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); > +#if IS_ENABLED(CONFIG_ARM_SMMU_V3) > + mtk_jpeg_enc_set_smmu_sid(hw_id); > +#endif > mtk_jpeg_set_enc_dst(ctx, > comp_jpeg[hw_id]->reg_base, > &dst_buf->vb2_buf); > @@ -1771,6 +1774,9 @@ static void mtk_jpegdec_worker(struct work_struct *work) > spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); > ctx->total_frame_num++; > mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); > +#if IS_ENABLED(CONFIG_ARM_SMMU_V3) You can avoid using preprocessor conditionals - and then, this doesn't look like an ARM SMMUv3 configuration, but rather a JPEG dec/enc HW config, so in that case the enclosing of this in the proposed config option would even be wrong. Use platform data for that. > + mtk_jpeg_dec_set_smmu_sid(hw_id); > +#endif > mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, > jpeg->variant->support_34bit, > &jpeg_src_buf->dec_param, > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h > index 8fddc133c46c..d3aba1e6cae8 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h > @@ -36,6 +36,17 @@ > > #define MTK_JPEG_ADDR_MASK GENMASK(1, 0) > > +#if IS_ENABLED(CONFIG_ARM_SMMU_V3) > +#define JPG_REG_CORE0_GUSER_ID 0x380d0000 > +#define JPG_REG_CORE1_GUSER_ID 0x388d0000 At least these two definitions shall go in the devicetree reg node. > +#define JPG_REG_GUSER_ID_MASK 0x7 > +#define JPG_REG_GUSER_ID_DEC_SID 0x4 > +#define JPG_REG_GUSER_ID_ENC_SID 0x5 > +#define JPG_REG_DEC_GUSER_ID_SHIFT 8 > +#define JPG_REG_ENC_GUSER_ID_SHIFT 4 If this is setting an IOMMU SID, then you can just use the "iommus" property to pass a handle to the IOMMU that this device is using plus the streamid, which you can retrieve and write to the guser_id_{dec,enc}_sid register. There's no reason to hardcode that in this header, and actually hardcoding will give you a number of issues (example: unpowered/unclocked access to the IOMMU, and many others). > +#define GUSER_ID_MAPRANGE 4 > +#endif > + > /** > * enum mtk_jpeg_ctx_state - states of the context state machine > * @MTK_JPEG_INIT: current state is initialized > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c > index d868e46aaf37..fadfc4b5e366 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c > @@ -274,6 +274,32 @@ void mtk_jpeg_dec_reset(void __iomem *base) > } > EXPORT_SYMBOL_GPL(mtk_jpeg_dec_reset); > > +#if IS_ENABLED(CONFIG_ARM_SMMU_V3) > +void mtk_jpeg_dec_set_smmu_sid(int hwid) > +{ > + void __iomem *dec_reg_base; > + u32 val, mask; > + > + if (hwid) > + dec_reg_base = ioremap(JPG_REG_CORE1_GUSER_ID, GUSER_ID_MAPRANGE); > + else > + dec_reg_base = ioremap(JPG_REG_CORE0_GUSER_ID, GUSER_ID_MAPRANGE); > + if (!dec_reg_base) { > + dev_err(jpeg->dev, "Failed to map jpgdec JPG_REG_GUSER_ID\n"); > + return; > + } > + > + val = ioread32(dec_reg_base); > + mask = ~(JPG_REG_GUSER_ID_MASK << JPG_REG_DEC_GUSER_ID_SHIFT); > + val &= mask; > + val |= (JPG_REG_GUSER_ID_DEC_SID << JPG_REG_DEC_GUSER_ID_SHIFT); > + > + iowrite32(val, dec_reg_base); > + iounmap(dec_reg_base); > +} > +EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_smmu_sid); > +#endif > + > static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, > u8 yscale_h, u8 uvscale_w, u8 uvscale_h) > { > @@ -552,7 +578,6 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) > struct vb2_v4l2_buffer *src_buf, *dst_buf; > struct mtk_jpeg_src_buf *jpeg_src_buf; > enum vb2_buffer_state buf_state; > - struct mtk_jpeg_ctx *ctx; > u32 dec_irq_ret; > u32 irq_status; > int i; > @@ -562,7 +587,6 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) > > cancel_delayed_work(&jpeg->job_timeout_work); > > - ctx = jpeg->hw_param.curr_ctx; > src_buf = jpeg->hw_param.src_buffer; > dst_buf = jpeg->hw_param.dst_buffer; > v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); > @@ -585,7 +609,7 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) > buf_state = VB2_BUF_STATE_DONE; > v4l2_m2m_buf_done(src_buf, buf_state); > mtk_jpegdec_put_buf(jpeg); > - pm_runtime_put(ctx->jpeg->dev); > + pm_runtime_put(jpeg->dev); You're doing more than what you're describing in the commit title and description. If this change was intentional, please move it to a diffrent commit. Regards, Angelo
Il 09/01/25 14:35, kyrie.wu ha scritto: > 1. different IC has different hw core; > 2. use a parameter to set jpeg hw count. In MT8195, each decoder core has its own devicetree node, so you can count how many cores are actually present and registered. Please do the same with MT8196, and replace MTK_JPEG{ENC,DEC}_HW_MAX with a variable that stores the number of cores, counted at probe time. Regards, Angelo > > Signed-off-by: kyrie.wu <kyrie.wu@mediatek.com> > --- > .../platform/mediatek/jpeg/mtk_jpeg_core.c | 28 +++++++++++++++---- > .../platform/mediatek/jpeg/mtk_jpeg_core.h | 2 ++ > 2 files changed, 25 insertions(+), 5 deletions(-) > > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > index 77b3bd6c4d3f..4dc6f82d74fa 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > @@ -1468,7 +1468,7 @@ static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx) > int i; > > spin_lock_irqsave(&jpeg->hw_lock, flags); > - for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) { > + for (i = 0; i < jpeg->variant->max_hw_count; i++) { > comp_jpeg = jpeg->enc_hw_dev[i]; > if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) { > hw_id = i; > @@ -1515,7 +1515,7 @@ static int mtk_jpegdec_get_hw(struct mtk_jpeg_ctx *ctx) > int i; > > spin_lock_irqsave(&jpeg->hw_lock, flags); > - for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) { > + for (i = 0; i < jpeg->variant->max_hw_count; i++) { > comp_jpeg = jpeg->dec_hw_dev[i]; > if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) { > hw_id = i; > @@ -1598,7 +1598,7 @@ static void mtk_jpegenc_worker(struct work_struct *work) > jpeg_work); > struct mtk_jpeg_dev *jpeg = ctx->jpeg; > > - for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) > + for (i = 0; i < jpeg->variant->max_hw_count; i++) > comp_jpeg[i] = jpeg->enc_hw_dev[i]; > i = 0; > > @@ -1696,7 +1696,7 @@ static void mtk_jpegdec_worker(struct work_struct *work) > struct mtk_jpeg_fb fb; > unsigned long flags; > > - for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) > + for (i = 0; i < jpeg->variant->max_hw_count; i++) > comp_jpeg[i] = jpeg->dec_hw_dev[i]; > i = 0; > > @@ -1925,6 +1925,7 @@ static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = { > .out_q_default_fourcc = V4L2_PIX_FMT_YUYV, > .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG, > .multi_core = true, > + .max_hw_count = 2, > .jpeg_worker = mtk_jpegenc_worker, > }; > > @@ -1938,6 +1939,21 @@ static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = { > .out_q_default_fourcc = V4L2_PIX_FMT_JPEG, > .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M, > .multi_core = true, > + .max_hw_count = 3, > + .jpeg_worker = mtk_jpegdec_worker, > +}; > + > +static const struct mtk_jpeg_variant mtk8196_jpegdec_drvdata = { > + .formats = mtk_jpeg_dec_formats, > + .num_formats = MTK_JPEG_DEC_NUM_FORMATS, > + .qops = &mtk_jpeg_dec_qops, > + .m2m_ops = &mtk_jpeg_multicore_dec_m2m_ops, > + .dev_name = "mtk-jpeg-dec", > + .ioctl_ops = &mtk_jpeg_dec_ioctl_ops, > + .out_q_default_fourcc = V4L2_PIX_FMT_JPEG, > + .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M, > + .multi_core = true, > + .max_hw_count = 2, > .jpeg_worker = mtk_jpegdec_worker, > }; > > @@ -1954,6 +1970,7 @@ static const struct mtk_jpeg_variant mtk8188_jpegenc_drvdata = { > .ioctl_ops = &mtk_jpeg_enc_ioctl_ops, > .out_q_default_fourcc = V4L2_PIX_FMT_YUYV, > .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG, > + .max_hw_count = 1, > .support_34bit = true, > }; > > @@ -1970,6 +1987,7 @@ static const struct mtk_jpeg_variant mtk8188_jpegdec_drvdata = { > .ioctl_ops = &mtk_jpeg_dec_ioctl_ops, > .out_q_default_fourcc = V4L2_PIX_FMT_JPEG, > .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M, > + .max_hw_count = 1, > .support_34bit = true, > }; > > @@ -2008,7 +2026,7 @@ static const struct of_device_id mtk_jpeg_match[] = { > }, > { > .compatible = "mediatek,mt8196-jpgdec", > - .data = &mtk8195_jpegdec_drvdata, > + .data = &mtk8196_jpegdec_drvdata, > }, > {}, > }; > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h > index d3aba1e6cae8..38672499ca18 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h > @@ -74,6 +74,7 @@ enum mtk_jpeg_ctx_state { > * @out_q_default_fourcc: output queue default fourcc > * @cap_q_default_fourcc: capture queue default fourcc > * @multi_core: mark jpeg hw is multi_core or not > + * @max_hw_count: jpeg hw-core count > * @jpeg_worker: jpeg dec or enc worker > * @support_34bit: flag to check if support dma_address 34bit > */ > @@ -91,6 +92,7 @@ struct mtk_jpeg_variant { > u32 out_q_default_fourcc; > u32 cap_q_default_fourcc; > bool multi_core; > + u32 max_hw_count; > void (*jpeg_worker)(struct work_struct *work); > bool support_34bit; > };
Il 09/01/25 14:35, kyrie.wu ha scritto: > Add jpeg dec and enc compatible for mt8196 > > Signed-off-by: kyrie.wu <kyrie.wu@mediatek.com> > --- > drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 8 ++++++++ > drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 3 +++ > drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 3 +++ > 3 files changed, 14 insertions(+) > > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > index 9517ebed0701..c3ccc525d9fd 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c > @@ -1996,6 +1996,14 @@ static const struct of_device_id mtk_jpeg_match[] = { > .compatible = "mediatek,mt8188-jpgdec", > .data = &mtk8188_jpegdec_drvdata, > }, > + { > + .compatible = "mediatek,mt8196-jpgenc", > + .data = &mtk8195_jpegenc_drvdata, > + }, > + { > + .compatible = "mediatek,mt8196-jpgdec", > + .data = &mtk8195_jpegdec_drvdata, You're adding this with MT8195 platform data, and then you're changing it to MT8196 specific platform data. Just put this commit at the end of the series, at this point. Regards, Angelo > + }, > {}, > }; > > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c > index ebded06ba92d..d868e46aaf37 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c > @@ -45,6 +45,9 @@ static const struct of_device_id mtk_jpegdec_hw_ids[] = { > { > .compatible = "mediatek,mt8195-jpgdec-hw", > }, > + { > + .compatible = "mediatek,mt8196-jpgdec-hw", > + }, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids); > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c > index 87fe1f324f23..ca06d4f435cd 100644 > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c > @@ -52,6 +52,9 @@ static const struct of_device_id mtk_jpegenc_drv_ids[] = { > { > .compatible = "mediatek,mt8195-jpgenc-hw", > }, > + { > + .compatible = "mediatek,mt8196-jpgenc-hw", > + }, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids);
This series adds support for mt8196 multi-hardwares jpeg enc & dec, by first adding mt8196 jpegdec and jpegenc compatible to install kernel driver. Add smmu setting to support smmu and iommu at the same time. Secondly refactor buffer and clock setting to support multi-hw jpeg working. Lastly, fix some bugs, including resolution change handleing, stop streaming sw flow and others. This series has been tested with MT8196 tast test. Encoding and decoding worked for this chip. Patches 1-3 Adds jpeg encoder and decoder compatible. Patches 4 add jpeg smmu sid setting. Patches 5 fix jpeg hw count setting to support different chips. Patches 6 refactor jpeg buffer payload setting to handle buffer size bug while resolution changed. Patches 7 reconstruct jpeg dst buffer layout. Patches 8 fix multi-core stop streaming flow Patches 9 refactor multi-core clk suspend/resume setting Patches 10 fix decoding buffer number setting timing issue Patches 11 refactor decoding resolution change operation Patches 12 fix remove buffer operation --- This series patches dependent on: [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20240808092555.12999-1-jianhua.lin@mediatek.com/ kyrie.wu (11): dt-bindings: mediatek: Add mediatek, mt8196-jpgdec compatible dt-bindings: mediatek: Add mediatek, mt8196-jpgenc compatible media: mediatek: jpeg: add jpeg compatible media: mediatek: jpeg: add jpeg smmu sid setting media: mediatek: jpeg: fix jpeg hw count setting media: mediatek: jpeg: refactor jpeg buffer payload setting media: mediatek: jpeg: refactor jpeg dst buffer layout media: mediatek: jpeg: fix stop streaming flow for multi-core media: mediatek: jpeg: refactor multi-core clk suspend and resume setting media: mediatek: jpeg: fix decoding buffer number setting timing issue media: mediatek: jpeg: refactor decoding resolution change operation media: mediatek: jpeg: fix remove buffer operation for multi-core ....yaml => mediatek,multi-core-jpegdec.yaml} | 10 +- ....yaml => mediatek,multi-core-jpegenc.yaml} | 10 +- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 126 ++++++++++++------ .../platform/mediatek/jpeg/mtk_jpeg_core.h | 17 ++- .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 116 +++++++++++++++- .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h | 4 + .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 113 +++++++++++++++- .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.h | 4 + 8 files changed, 343 insertions(+), 57 deletions(-) rename Documentation/devicetree/bindings/media/{mediatek,mt8195-jpegdec.yaml => mediatek,multi-core-jpegdec.yaml} (95%) rename Documentation/devicetree/bindings/media/{mediatek,mt8195-jpegenc.yaml => mediatek,multi-core-jpegenc.yaml} (94%)