| Message ID | 20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com |
|---|---|
| Headers | show |
| Series | Support for Adreno X1-85 Speedbin along with new OPP levels | expand |
On 8.01.2025 11:42 PM, Akhil P Oommen wrote: > Adreno X1-85 has an additional bit which is at a non-contiguous > location in qfprom. Add support for this new "hi" bit along with > the speedbin mappings. > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- > 2 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { > .gmu_cgc_mode = 0x00020202, > }, > .address_space_size = SZ_256G, > + .speedbins = ADRENO_SPEEDBINS( > + { 0, 0 }, > + { 263, 1 }, > + { 315, 0 }, > + ), > .preempt_record_size = 4192 * SZ_1K, > }, { > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) > > int adreno_read_speedbin(struct device *dev, u32 *speedbin) > { > - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); > + u32 hi_bits = 0; > + int ret; > + > + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); > + if (ret) > + return ret; > + > + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ > + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); > + if (ret != -ENOENT) > + return ret; > + > + *speedbin |= (hi_bits << 8); Now that we're overwriting speedbin, we should probably have some checks in order to make sure somebody passing a too-wide cell to one of these won't result in cripplingly-untraceable value corruption I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it a day? Konrad
On Thu, Jan 09, 2025 at 04:12:39AM +0530, Akhil P Oommen wrote: > Update the RPMH level definitions to include TURBO_L5 corner. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > include/dt-bindings/power/qcom-rpmpd.h | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 1/9/2025 7:27 PM, Konrad Dybcio wrote: > On 8.01.2025 11:42 PM, Akhil P Oommen wrote: >> Adreno X1-85 has an additional bit which is at a non-contiguous >> location in qfprom. Add support for this new "hi" bit along with >> the speedbin mappings. >> --- >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- >> 2 files changed, 19 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { >> .gmu_cgc_mode = 0x00020202, >> }, >> .address_space_size = SZ_256G, >> + .speedbins = ADRENO_SPEEDBINS( >> + { 0, 0 }, >> + { 263, 1 }, >> + { 315, 0 }, >> + ), >> .preempt_record_size = 4192 * SZ_1K, >> }, { >> .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) >> >> int adreno_read_speedbin(struct device *dev, u32 *speedbin) >> { >> - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >> + u32 hi_bits = 0; >> + int ret; >> + >> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >> + if (ret) >> + return ret; >> + >> + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ >> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); >> + if (ret != -ENOENT) >> + return ret; >> + >> + *speedbin |= (hi_bits << 8); > > Now that we're overwriting speedbin, we should probably have some checks in > order to make sure somebody passing a too-wide cell to one of these won't > result in cripplingly-untraceable value corruption > > I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it > a day? X1E is an outlier here, because this was fixed from the next chipset onward. For newer chipsets, we can use just the "speed_bin" node, which represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) > 8)" here? -Akhil. > > Konrad
On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote: > On 1/9/2025 7:27 PM, Konrad Dybcio wrote: > > On 8.01.2025 11:42 PM, Akhil P Oommen wrote: > >> Adreno X1-85 has an additional bit which is at a non-contiguous > >> location in qfprom. Add support for this new "hi" bit along with > >> the speedbin mappings. > >> --- > >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ > >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- > >> 2 files changed, 19 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 > >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { > >> .gmu_cgc_mode = 0x00020202, > >> }, > >> .address_space_size = SZ_256G, > >> + .speedbins = ADRENO_SPEEDBINS( > >> + { 0, 0 }, > >> + { 263, 1 }, > >> + { 315, 0 }, > >> + ), > >> .preempt_record_size = 4192 * SZ_1K, > >> }, { > >> .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > >> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 > >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > >> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) > >> > >> int adreno_read_speedbin(struct device *dev, u32 *speedbin) > >> { > >> - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); > >> + u32 hi_bits = 0; > >> + int ret; > >> + > >> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); > >> + if (ret) > >> + return ret; > >> + > >> + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ > >> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); > >> + if (ret != -ENOENT) > >> + return ret; > >> + > >> + *speedbin |= (hi_bits << 8); > > > > Now that we're overwriting speedbin, we should probably have some checks in > > order to make sure somebody passing a too-wide cell to one of these won't > > result in cripplingly-untraceable value corruption > > > > I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it > > a day? > > X1E is an outlier here, because this was fixed from the next chipset > onward. For newer chipsets, we can use just the "speed_bin" node, which > represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) > > 8)" here? Or extend nvmem core to support non-contiguous fields. > > -Akhil. > > > > > Konrad >
On 15.01.2025 8:59 PM, Dmitry Baryshkov wrote: > On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote: >> On 1/9/2025 7:27 PM, Konrad Dybcio wrote: >>> On 8.01.2025 11:42 PM, Akhil P Oommen wrote: >>>> Adreno X1-85 has an additional bit which is at a non-contiguous >>>> location in qfprom. Add support for this new "hi" bit along with >>>> the speedbin mappings. >>>> --- >>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- >>>> 2 files changed, 19 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { >>>> .gmu_cgc_mode = 0x00020202, >>>> }, >>>> .address_space_size = SZ_256G, >>>> + .speedbins = ADRENO_SPEEDBINS( >>>> + { 0, 0 }, >>>> + { 263, 1 }, >>>> + { 315, 0 }, >>>> + ), >>>> .preempt_record_size = 4192 * SZ_1K, >>>> }, { >>>> .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ >>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) >>>> >>>> int adreno_read_speedbin(struct device *dev, u32 *speedbin) >>>> { >>>> - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >>>> + u32 hi_bits = 0; >>>> + int ret; >>>> + >>>> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >>>> + if (ret) >>>> + return ret; >>>> + >>>> + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ >>>> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); >>>> + if (ret != -ENOENT) >>>> + return ret; >>>> + >>>> + *speedbin |= (hi_bits << 8); >>> >>> Now that we're overwriting speedbin, we should probably have some checks in >>> order to make sure somebody passing a too-wide cell to one of these won't >>> result in cripplingly-untraceable value corruption >>> >>> I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it >>> a day? >> >> X1E is an outlier here, because this was fixed from the next chipset >> onward. For newer chipsets, we can use just the "speed_bin" node, which >> represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) > >> 8)" here? > > Or extend nvmem core to support non-contiguous fields. This sounds more desirable, as we surely aren't the only ones with such a "feature".. Konrad
On 1/17/2025 2:46 AM, Konrad Dybcio wrote: > On 15.01.2025 8:59 PM, Dmitry Baryshkov wrote: >> On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote: >>> On 1/9/2025 7:27 PM, Konrad Dybcio wrote: >>>> On 8.01.2025 11:42 PM, Akhil P Oommen wrote: >>>>> Adreno X1-85 has an additional bit which is at a non-contiguous >>>>> location in qfprom. Add support for this new "hi" bit along with >>>>> the speedbin mappings. >>>>> --- >>>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ >>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- >>>>> 2 files changed, 19 insertions(+), 1 deletion(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 >>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { >>>>> .gmu_cgc_mode = 0x00020202, >>>>> }, >>>>> .address_space_size = SZ_256G, >>>>> + .speedbins = ADRENO_SPEEDBINS( >>>>> + { 0, 0 }, >>>>> + { 263, 1 }, >>>>> + { 315, 0 }, >>>>> + ), >>>>> .preempt_record_size = 4192 * SZ_1K, >>>>> }, { >>>>> .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ >>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>>> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 >>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>>> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) >>>>> >>>>> int adreno_read_speedbin(struct device *dev, u32 *speedbin) >>>>> { >>>>> - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >>>>> + u32 hi_bits = 0; >>>>> + int ret; >>>>> + >>>>> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >>>>> + if (ret) >>>>> + return ret; >>>>> + >>>>> + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ >>>>> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); >>>>> + if (ret != -ENOENT) >>>>> + return ret; >>>>> + >>>>> + *speedbin |= (hi_bits << 8); >>>> >>>> Now that we're overwriting speedbin, we should probably have some checks in >>>> order to make sure somebody passing a too-wide cell to one of these won't >>>> result in cripplingly-untraceable value corruption >>>> >>>> I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it >>>> a day? >>> >>> X1E is an outlier here, because this was fixed from the next chipset >>> onward. For newer chipsets, we can use just the "speed_bin" node, which >>> represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) > >>> 8)" here? >> >> Or extend nvmem core to support non-contiguous fields. > > This sounds more desirable, as we surely aren't the only ones with > such a "feature".. Sounds good. I can explore that when I am back from vacation early next month. -Akhil. > > Konrad
On Thu, 09 Jan 2025 04:12:37 +0530, Akhil P Oommen wrote: > This series adds gpu speedbin support for Adreno X1-85 GPU along with > additional OPP levels. Because the higher OPPs require GPU ACD feature, > this series has dependency on the GPU ACD support series [1]. Also, > there is dependency on dimtry's series which fixes dword alignment in > nvmem driver [2]. We need a small fix up on top of that and that is > being discussed there. Hence, the RFC tag. > > [...] Applied, thanks! [3/4] dt-bindings: nvmem: qfprom: Add X1E80100 compatible commit: 3419bdfd88e314bc5f80b02fa4651c81a0a85b57 Best regards,
This series adds gpu speedbin support for Adreno X1-85 GPU along with additional OPP levels. Because the higher OPPs require GPU ACD feature, this series has dependency on the GPU ACD support series [1]. Also, there is dependency on dimtry's series which fixes dword alignment in nvmem driver [2]. We need a small fix up on top of that and that is being discussed there. Hence, the RFC tag. An interesting bit here is the non-contigous "hi" bit for speedbin fuse. Otherwise, it is business as usual. The device tree change has a dependency on the driver changes. So the driver changes should be picked up first. [1] https://lore.kernel.org/lkml/20250109-gpu-acd-v4-0-08a5efaf4a23@quicinc.com/ [2] https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org/ -Akhil --- Akhil P Oommen (4): drm/msm/adreno: Add speedbin support for X1-85 dt-bindings: power: qcom,rpmpd: add Turbo L5 corner dt-bindings: nvmem: qfprom: Add X1E80100 compatible arm64: dts: qcom: x1e80100: Update GPU OPP table .../devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 47 ++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++- include/dt-bindings/power/qcom-rpmpd.h | 1 + 5 files changed, 68 insertions(+), 1 deletion(-) --- base-commit: 5fcdd8fcd55d1da6fdf8deb78355a5c23ce94d39 change-id: 20240807-x1e-speedbin-b4-a0c304d13983 prerequisite-message-id: 20250109-gpu-acd-v4-0-08a5efaf4a23@quicinc.com prerequisite-patch-id: 2ac56343518c3c16229262051f52e448564f2286 prerequisite-patch-id: 1c363fb7cd864279bd97ed50a02f05f72ca00a5d prerequisite-patch-id: 059608aac5a0a1fa11ea93a8871820f054771301 prerequisite-patch-id: de12f1b879070aca3f42973b75ed04d4d835b244 prerequisite-patch-id: 421ea499b3e901030f66f697dc0a0b718d9db20e prerequisite-patch-id: ca6d3a3c65bd17bbcd7785e4584941a438aafcb9 prerequisite-patch-id: 017b7ba9e9bfd70719b77bf741bf0afa7f20cee0 prerequisite-message-id: 20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org prerequisite-patch-id: c1310808de89982d41261bab69c77be2e83a6339 prerequisite-patch-id: 34a5a771be148f71d66acd4417493cc752e6d3a6 prerequisite-patch-id: 30ac1f33b3dc8979f28fdfd6303595fcfce56b84 prerequisite-patch-id: 2238546441608d9f5755b4ebc1d5ea6090c6c3bb prerequisite-patch-id: 7a260ae7850d966e8fecd3ebc5114ac157d23c87 Best regards,