| Message ID | 20250108055012.1938530-1-dev.tailor@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: add cpu cache information to ExynosAuto-v920 | expand |
Hi Devang > -----Original Message----- > From: Devang Tailor <dev.tailor@samsung.com> > Sent: Wednesday, January 8, 2025 11:20 AM > To: alim.akhtar@samsung.com; dev.tailor@samsung.com; robh@kernel.org; > krzk+dt@kernel.org; conor+dt@kernel.org > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; > faraz.ata@samsung.com > Subject: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto- > v920 > > Add CPU caches information to its dt nodes so that the same is available to > userspace via sysfs. This SoC has 64/64 KB I/D cache and 256KB of L2 cache for > each core, 2 MB of shared L3 cache for each quad cpu cluster and 1 MB of > shared L3 cache for the dual cpu cluster. > > Signed-off-by: Devang Tailor <dev.tailor@samsung.com> > > --- > Changes in v2: > - Added L3 cache for all the three cpu clusters > - Corrected L2 cache numbering as a part of review comments from Krzysztof > and updated as per cpus clusters. > - Link to v1: https://patchwork.kernel.org/project/linux-arm- > kernel/patch/20241231064350.523713-1-dev.tailor@samsung.com/ > --- > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 127 > ++++++++++++++++++ > 1 file changed, 127 insertions(+) > [snip] > + l3_cache_cl0: l3-cache0 { You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and Remove the specific node for CL1, because both are same. > + compatible = "cache"; > + cache-level = <3>; > + cache-unified; > + cache-size = <0x200000>;/* 2MB L3 cache for cpu > cluster-0 */ > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + > + l3_cache_cl1: l3-cache1 { > + compatible = "cache"; > + cache-level = <3>; > + cache-unified; > + cache-size = <0x200000>;/* 2MB L3 cache for cpu > cluster-1 */ > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + [snip] > + l3_cache_cl2: l3-cache2 { > 2.34.1
On Fri, Jan 31, 2025 at 05:19:09PM +0530, Alim Akhtar wrote: > Hi Devang > > > > > Add CPU caches information to its dt nodes so that the same is available to > > userspace via sysfs. This SoC has 64/64 KB I/D cache and 256KB of L2 cache for > > each core, 2 MB of shared L3 cache for each quad cpu cluster and 1 MB of > > shared L3 cache for the dual cpu cluster. > > > > Signed-off-by: Devang Tailor <dev.tailor@samsung.com> > > > > --- > > Changes in v2: > > - Added L3 cache for all the three cpu clusters > > - Corrected L2 cache numbering as a part of review comments from Krzysztof > > and updated as per cpus clusters. > > - Link to v1: https://patchwork.kernel.org/project/linux-arm- > > kernel/patch/20241231064350.523713-1-dev.tailor@samsung.com/ > > --- > > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 127 > > ++++++++++++++++++ > > 1 file changed, 127 insertions(+) > > > [snip] > > + l3_cache_cl0: l3-cache0 { > You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and > Remove the specific node for CL1, because both are same. > What do you mean by "both are same" ? Do you mean both have exact same properties but are physically different caches ? OR Do you mean it is just one shared cache ? If former, we still need distinct node to get the cacheinfo about shareability correct. If this is about avoiding duplication of errors, you can probably define some macro and avoid it, but we need 2 nodes in the devicetree. If latter, you suggestion is correct. -- Regards, Sudeep
On 31/01/2025 14:27, Sudeep Holla wrote: >>> >> [snip] >> > + l3_cache_cl0: l3-cache0 { >> You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and >> Remove the specific node for CL1, because both are same. >> > > What do you mean by "both are same" ? > Do you mean both have exact same properties but are physically different > caches ? OR > Do you mean it is just one shared cache ? > > If former, we still need distinct node to get the cacheinfo about > shareability correct. If this is about avoiding duplication of errors, > you can probably define some macro and avoid it, but we need 2 nodes in > the devicetree. > > If latter, you suggestion is correct. No answers here, so I drop this patch from my queue. Best regards, Krzysztof
Hi Sudeep > -----Original Message----- > From: Sudeep Holla <sudeep.holla@arm.com> > Sent: Friday, January 31, 2025 6:57 PM > To: Alim Akhtar <alim.akhtar@samsung.com> > Cc: 'Devang Tailor' <dev.tailor@samsung.com>; robh@kernel.org; > krzk+dt@kernel.org; conor+dt@kernel.org; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; > linux-kernel@vger.kernel.org; faraz.ata@samsung.com > Subject: Re: [PATCH v2] arm64: dts: add cpu cache information to > ExynosAuto-v920 > [snip] > > You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and > > Remove the specific node for CL1, because both are same. > > > > What do you mean by "both are same" ? > Do you mean both have exact same properties but are physically different > caches ? OR Do you mean it is just one shared cache ? > Thanks for review and pointing it out, v920 has physically different caches (two of them are same properties, but the 3rd has 1MB lesser size) Got you point about having distinct node for cacheinfo population So for this patch: Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > If former, we still need distinct node to get the cacheinfo about shareability > correct. If this is about avoiding duplication of errors, you can probably define > some macro and avoid it, but we need 2 nodes in the devicetree. > > If latter, you suggestion is correct. > > -- > Regards, > Sudeep
Hi Krzysztof > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Wednesday, February 5, 2025 9:22 PM > To: Sudeep Holla <sudeep.holla@arm.com>; Alim Akhtar > <alim.akhtar@samsung.com> > Cc: 'Devang Tailor' <dev.tailor@samsung.com>; robh@kernel.org; > krzk+dt@kernel.org; conor+dt@kernel.org; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; > linux-kernel@vger.kernel.org; faraz.ata@samsung.com > Subject: Re: [PATCH v2] arm64: dts: add cpu cache information to > ExynosAuto-v920 > > On 31/01/2025 14:27, Sudeep Holla wrote: > >>> > >> [snip] > >> > + l3_cache_cl0: l3-cache0 { > >> You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and > >> Remove the specific node for CL1, because both are same. > >> > > > > What do you mean by "both are same" ? > > Do you mean both have exact same properties but are physically > > different caches ? OR Do you mean it is just one shared cache ? > > > > If former, we still need distinct node to get the cacheinfo about > > shareability correct. If this is about avoiding duplication of errors, > > you can probably define some macro and avoid it, but we need 2 nodes > > in the devicetree. > > > > If latter, you suggestion is correct. > > No answers here, so I drop this patch from my queue. > It took sometime to get the confirmation internally (because of new year holiday) Just replied to Sudeep. It will be great if you can consider this patch for this cycle. Thanks! > Best regards, > Krzysztof
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index eb446cdc4ab6..a3fd503c1b21 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -89,6 +89,13 @@ cpu0: cpu@0 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu1: cpu@100 { @@ -96,6 +103,13 @@ cpu1: cpu@100 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu2: cpu@200 { @@ -103,6 +117,13 @@ cpu2: cpu@200 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x200>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu3: cpu@300 { @@ -110,6 +131,13 @@ cpu3: cpu@300 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x300>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu4: cpu@10000 { @@ -117,6 +145,13 @@ cpu4: cpu@10000 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x10000>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu5: cpu@10100 { @@ -124,6 +159,13 @@ cpu5: cpu@10100 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x10100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu6: cpu@10200 { @@ -131,6 +173,13 @@ cpu6: cpu@10200 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x10200>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu7: cpu@10300 { @@ -138,6 +187,13 @@ cpu7: cpu@10300 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x10300>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu8: cpu@20000 { @@ -145,6 +201,13 @@ cpu8: cpu@20000 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x20000>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl2>; }; cpu9: cpu@20100 { @@ -152,6 +215,70 @@ cpu9: cpu@20100 { compatible = "arm,cortex-a78ae"; reg = <0x0 0x20100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl2>; + }; + + l2_cache_cl0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl0>; + }; + + l2_cache_cl1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl1>; + }; + + l2_cache_cl2: l2-cache2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl2>; + }; + + l3_cache_cl0: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */ + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3_cache_cl1: l3-cache1 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */ + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3_cache_cl2: l3-cache2 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */ + cache-line-size = <64>; + cache-sets = <1365>; }; };
Add CPU caches information to its dt nodes so that the same is available to userspace via sysfs. This SoC has 64/64 KB I/D cache and 256KB of L2 cache for each core, 2 MB of shared L3 cache for each quad cpu cluster and 1 MB of shared L3 cache for the dual cpu cluster. Signed-off-by: Devang Tailor <dev.tailor@samsung.com> --- Changes in v2: - Added L3 cache for all the three cpu clusters - Corrected L2 cache numbering as a part of review comments from Krzysztof and updated as per cpus clusters. - Link to v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241231064350.523713-1-dev.tailor@samsung.com/ --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+)