| Message ID | 20250327-videocc-pll-multi-pd-voting-v3-15-895fafd62627@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: Add support to attach multiple power domains in cc probe | expand |
On 4/1/25 5:27 PM, Konrad Dybcio wrote: > On 3/27/25 10:52 AM, Jagadeesh Kona wrote: >> Videocc requires both MMCX and MXC rails to be powered ON to configure >> the video PLLs on SM8650 platform. Hence add MXC power domain to videocc >> node on SM8650. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc41195a1210a23 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { >> reg = <0 0x0aaf0000 0 0x10000>; >> clocks = <&bi_tcxo_div2>, >> <&gcc GCC_VIDEO_AHB_CLK>; >> - power-domains = <&rpmhpd RPMHPD_MMCX>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>, >> + <&rpmhpd RPMHPD_MXC>; > > So all other DTs touched in this series reference low_svs in required-opps actually "all" is wrong on my side, please also consider and if necessary apply the same change to patch 18 Konrad > > Is that an actual requirement? Otherwise since Commit e3e56c050ab6 > ("soc: qcom: rpmhpd: Make power_on actually enable the domain") we get the > first nonzero state, which can be something like low_svs_d2 > > Konrad
On 4/1/2025 8:57 PM, Konrad Dybcio wrote: > On 3/27/25 10:52 AM, Jagadeesh Kona wrote: >> Videocc requires both MMCX and MXC rails to be powered ON to configure >> the video PLLs on SM8650 platform. Hence add MXC power domain to videocc >> node on SM8650. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc41195a1210a23 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { >> reg = <0 0x0aaf0000 0 0x10000>; >> clocks = <&bi_tcxo_div2>, >> <&gcc GCC_VIDEO_AHB_CLK>; >> - power-domains = <&rpmhpd RPMHPD_MMCX>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>, >> + <&rpmhpd RPMHPD_MXC>; > > So all other DTs touched in this series reference low_svs in required-opps > > Is that an actual requirement? Otherwise since Commit e3e56c050ab6 > ("soc: qcom: rpmhpd: Make power_on actually enable the domain") we get the > first nonzero state, which can be something like low_svs_d2 > Yes, commit e3e56c050ab6 enables the power-domain at first non-zero level, but in some chipsets, the first nonzero state could be retention, which is not sufficient for clock controller to operate. So required-opps is needed to ensure the rails are at a level above retention for clock controller to operate. low_svs was choosen since that is a level that is generally supported across all the chipsets, but low_svs_d2 may not be supported on some chipsets. And required-opps is not mandatory for MXC power domain due to commit f0cc5f7cb43f (pmdomain: qcom: rpmhpd: Skip retention level for Power Domains), which ensures MXC always gets enabled above retention level. But it was added to make number of required-opps uniform with the number of power domains based on discussion at [1]. [1]: https://lore.kernel.org/all/eoqqz5hyyq6ej5uo6phijbeu5qafbpfxlnreyzzcyfw23pl2yq@ftxnasc6sr2t/#t Thanks, Jagadeesh > Konrad
On 4/1/2025 9:30 PM, Konrad Dybcio wrote: > On 4/1/25 5:27 PM, Konrad Dybcio wrote: >> On 3/27/25 10:52 AM, Jagadeesh Kona wrote: >>> Videocc requires both MMCX and MXC rails to be powered ON to configure >>> the video PLLs on SM8650 platform. Hence add MXC power domain to videocc >>> node on SM8650. >>> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >>> --- >>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc41195a1210a23 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> @@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { >>> reg = <0 0x0aaf0000 0 0x10000>; >>> clocks = <&bi_tcxo_div2>, >>> <&gcc GCC_VIDEO_AHB_CLK>; >>> - power-domains = <&rpmhpd RPMHPD_MMCX>; >>> + power-domains = <&rpmhpd RPMHPD_MMCX>, >>> + <&rpmhpd RPMHPD_MXC>; >> >> So all other DTs touched in this series reference low_svs in required-opps > > actually "all" is wrong on my side, please also consider and if necessary apply > the same change to patch 18 > > Konrad > It is not needed for SM8650. In the initial SM8650 videocc and camcc series, required-opps was added for MMCX. But it was dropped based on the review comments in that series, after confirming that minimum non-zero level from cmd-db on MMCX is > retention on SM8650. And as mentioned here[1], required-opps is not mandatory for MXC as well. [1]: https://lore.kernel.org/all/44dad3b5-ea3d-47db-8aca-8f67294fced9@quicinc.com/ Thanks, Jagadeesh >> >> Is that an actual requirement? Otherwise since Commit e3e56c050ab6 >> ("soc: qcom: rpmhpd: Make power_on actually enable the domain") we get the >> first nonzero state, which can be something like low_svs_d2 >> >> Konrad
On 4/11/25 9:16 AM, Jagadeesh Kona wrote: > > > On 4/1/2025 8:57 PM, Konrad Dybcio wrote: >> On 3/27/25 10:52 AM, Jagadeesh Kona wrote: >>> Videocc requires both MMCX and MXC rails to be powered ON to configure >>> the video PLLs on SM8650 platform. Hence add MXC power domain to videocc >>> node on SM8650. >>> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >>> --- >>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc41195a1210a23 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> @@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { >>> reg = <0 0x0aaf0000 0 0x10000>; >>> clocks = <&bi_tcxo_div2>, >>> <&gcc GCC_VIDEO_AHB_CLK>; >>> - power-domains = <&rpmhpd RPMHPD_MMCX>; >>> + power-domains = <&rpmhpd RPMHPD_MMCX>, >>> + <&rpmhpd RPMHPD_MXC>; >> >> So all other DTs touched in this series reference low_svs in required-opps >> >> Is that an actual requirement? Otherwise since Commit e3e56c050ab6 >> ("soc: qcom: rpmhpd: Make power_on actually enable the domain") we get the >> first nonzero state, which can be something like low_svs_d2 >> > Yes, commit e3e56c050ab6 enables the power-domain at first non-zero level, but in > some chipsets, the first nonzero state could be retention, which is not sufficient > for clock controller to operate. So required-opps is needed to ensure the rails are > at a level above retention for clock controller to operate. low_svs was choosen since > that is a level that is generally supported across all the chipsets, but low_svs_d2 > may not be supported on some chipsets. > > And required-opps is not mandatory for MXC power domain due to commit f0cc5f7cb43f > (pmdomain: qcom: rpmhpd: Skip retention level for Power Domains), which ensures MXC > always gets enabled above retention level. But it was added to make number of > required-opps uniform with the number of power domains based on discussion at [1]. > > [1]: https://lore.kernel.org/all/eoqqz5hyyq6ej5uo6phijbeu5qafbpfxlnreyzzcyfw23pl2yq@ftxnasc6sr2t/#t Alright, thanks for the explanation! Konrad
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc41195a1210a23 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;