Message ID | 20250407121008.22230-1-quic_nitirawa@quicinc.com |
---|---|
State | New |
Headers | show |
Series | [V1] phy: qcom-qmp-ufs: check for mode type for phy setting | expand |
On Mon, 07 Apr 2025 17:40:08 +0530, Nitin Rawat wrote: > Generally all target supports Rate B but for very few like SM8550, > two sets of UFS PHY settings are provided, one set is to support > HS-G5 Rate A and another set is to support HS-G4 and lower > gears with Rate B. > > Commit b02cc9a17679("phy: qcom-qmp-ufs: Add PHY Configuration support > for sm8750") apply Rate B setting for SM8550 gear 5 without checking > for mode value (Rate A or Rate B) from Controller driver which caused > issue as SM8550 support rate A for Gear 5. > > [...] Applied, thanks! [1/1] phy: qcom-qmp-ufs: check for mode type for phy setting commit: d784552e76a23c4ffad0e383670cd1d86064a6be Best regards,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 45b3b792696e..b33e2e2b5014 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1754,7 +1754,8 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); } - qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); + if (qmp->mode == PHY_MODE_UFS_HS_B) + qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } static int qmp_ufs_com_init(struct qmp_ufs *qmp)