| Message ID | 20250501062344.2526061-14-pierrick.bouvier@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | single-binary: compile target/arm twice | expand |
On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/helper.h | 2 +- > target/arm/tcg/tlb_helper.c | 2 +- > target/arm/tcg/translate-a64.c | 2 +- > target/arm/tcg/translate.c | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 4/30/25 23:23, Pierrick Bouvier wrote: > --- a/target/arm/helper.h > +++ b/target/arm/helper.h > @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) > DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) > DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) > DEF_HELPER_2(exception_swstep, noreturn, env, i32) > -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) > +DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) > DEF_HELPER_1(setend, void, env) > DEF_HELPER_2(wfi, void, env, i32) > DEF_HELPER_1(wfe, void, env) > diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c > index 8841f039bc6..943b8438fc7 100644 > --- a/target/arm/tcg/tlb_helper.c > +++ b/target/arm/tcg/tlb_helper.c > @@ -277,7 +277,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); > } > > -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) > +void helper_exception_pc_alignment(CPUARMState *env, uint64_t pc) > { > ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; > int target_el = exception_target_el(env); I think for this and the next patch, it would be worth extending include/exec/helper-head.h.inc and include/tcg/ to allow vaddr. r~
On 5/1/25 9:30 AM, Richard Henderson wrote: > On 4/30/25 23:23, Pierrick Bouvier wrote: >> --- a/target/arm/helper.h >> +++ b/target/arm/helper.h >> @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) >> DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) >> DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) >> DEF_HELPER_2(exception_swstep, noreturn, env, i32) >> -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) >> +DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) >> DEF_HELPER_1(setend, void, env) >> DEF_HELPER_2(wfi, void, env, i32) >> DEF_HELPER_1(wfe, void, env) >> diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c >> index 8841f039bc6..943b8438fc7 100644 >> --- a/target/arm/tcg/tlb_helper.c >> +++ b/target/arm/tcg/tlb_helper.c >> @@ -277,7 +277,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, >> arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); >> } >> >> -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) >> +void helper_exception_pc_alignment(CPUARMState *env, uint64_t pc) >> { >> ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; >> int target_el = exception_target_el(env); > > I think for this and the next patch, it would be worth extending > include/exec/helper-head.h.inc and include/tcg/ to allow vaddr. > Ok, I'll add it. > > r~
diff --git a/target/arm/helper.h b/target/arm/helper.h index 09075058391..450c9d841bf 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 8841f039bc6..943b8438fc7 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -277,7 +277,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +void helper_exception_pc_alignment(CPUARMState *env, uint64_t pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; int target_el = exception_target_el(env); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 43408c71bbd..2fe8ada803a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10247,7 +10247,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * start of the TB. */ assert(s->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_i64(pc)); s->base.is_jmp = DISAS_NORETURN; s->base.pc_next = QEMU_ALIGN_UP(pc, 4); return; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 273b860d572..1577ef697b2 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7801,7 +7801,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * be possible after an indirect branch, at the start of the TB. */ assert(dc->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_i64(pc)); dc->base.is_jmp = DISAS_NORETURN; dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); return;
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.h | 2 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-)