| Message ID | 20250505015223.3895275-47-pierrick.bouvier@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | single-binary: compile target/arm twice | expand |
On 5/4/25 18:52, Pierrick Bouvier wrote: > aarch64 specific code is guarded by cpu_isar_feature(aa64*), so it's > safe to expose it. > > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/tcg/tlb-insns.c | 7 ------- > target/arm/tcg/meson.build | 3 ++- > 2 files changed, 2 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> In an ideal world, this would only be included within the system build, since all tlb flushing insns are privileged. However, it would appear helper.c needs more cleanup before that could happen. r~
On 5/5/25 11:49 AM, Richard Henderson wrote: > On 5/4/25 18:52, Pierrick Bouvier wrote: >> aarch64 specific code is guarded by cpu_isar_feature(aa64*), so it's >> safe to expose it. >> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/tcg/tlb-insns.c | 7 ------- >> target/arm/tcg/meson.build | 3 ++- >> 2 files changed, 2 insertions(+), 8 deletions(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > In an ideal world, this would only be included within the system build, since all tlb > flushing insns are privileged. However, it would appear helper.c needs more cleanup > before that could happen. > I added the ifndef CONFIG_USER_ONLY around define_tlb_insn_regs(cpu) in helper.c, which allows to build this tlb-insns only for system. > > r~
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index 0407ad5542d..95c26c6d463 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -35,7 +35,6 @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } -#ifdef TARGET_AARCH64 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -46,7 +45,6 @@ static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, } return CP_ACCESS_OK; } -#endif /* IS variants of TLB operations must affect all cores */ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -802,7 +800,6 @@ static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = { .writefn = tlbi_aa64_vae3_write }, }; -#ifdef TARGET_AARCH64 typedef struct { uint64_t base; uint64_t length; @@ -1270,8 +1267,6 @@ static const ARMCPRegInfo tlbi_rme_reginfo[] = { .writefn = tlbi_aa64_paallos_write }, }; -#endif - void define_tlb_insn_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1299,7 +1294,6 @@ void define_tlb_insn_regs(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, tlbi_el3_cp_reginfo); } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } @@ -1309,5 +1303,4 @@ void define_tlb_insn_regs(ARMCPU *cpu) if (cpu_isar_feature(aa64_rme, cpu)) { define_arm_cp_regs(cpu, tlbi_rme_reginfo); } -#endif } diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 9669eab89e3..a5fcf0e7b88 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -34,7 +34,6 @@ arm_ss.add(files( 'mve_helper.c', 'op_helper.c', 'vec_helper.c', - 'tlb-insns.c', 'arith_helper.c', 'vfp_helper.c', )) @@ -65,6 +64,7 @@ arm_common_system_ss.add(files( 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', + 'tlb-insns.c', )) arm_user_ss.add(files( 'crypto_helper.c', @@ -72,4 +72,5 @@ arm_user_ss.add(files( 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', + 'tlb-insns.c', ))
aarch64 specific code is guarded by cpu_isar_feature(aa64*), so it's safe to expose it. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/tlb-insns.c | 7 ------- target/arm/tcg/meson.build | 3 ++- 2 files changed, 2 insertions(+), 8 deletions(-)