diff mbox series

[08/12] target/ppc: Fill in TCGCPUOps.pointer_wrap

Message ID 20250504205714.3432096-9-richard.henderson@linaro.org
State New
Headers show
Series accel/tcg: Fix cross-page pointer wrapping issue | expand

Commit Message

Richard Henderson May 4, 2025, 8:57 p.m. UTC
Check 32 vs 64-bit state.

Cc: qemu-ppc@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/cpu_init.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Philippe Mathieu-Daudé May 5, 2025, 4:50 p.m. UTC | #1
On 4/5/25 22:57, Richard Henderson wrote:
> Check 32 vs 64-bit state.
> 
> Cc: qemu-ppc@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/ppc/cpu_init.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index cf88a18244..1f18967b62 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -7386,6 +7386,12 @@ static void ppc_cpu_exec_exit(CPUState *cs)
>           cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu);
>       }
>   }
> +
> +static vaddr ppc_pointer_wrap(CPUState *cs, int mmu_idx,
> +                              vaddr result, vaddr base)
> +{
> +    return (cpu_env(cs)->hflags >> HFLAGS_64) & 1 ? result : (uint32_t)result;

Alternatively expose and use NARROW_MODE().

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> +}
>   #endif /* CONFIG_TCG */
>   
>   #endif /* !CONFIG_USER_ONLY */
> @@ -7490,6 +7496,7 @@ static const TCGCPUOps ppc_tcg_ops = {
>     .record_sigsegv = ppc_cpu_record_sigsegv,
>   #else
>     .tlb_fill = ppc_cpu_tlb_fill,
> +  .pointer_wrap = ppc_pointer_wrap,
>     .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
>     .cpu_exec_halt = ppc_cpu_has_work,
>     .cpu_exec_reset = cpu_reset,
Richard Henderson May 5, 2025, 7 p.m. UTC | #2
On 5/5/25 09:50, Philippe Mathieu-Daudé wrote:
> On 4/5/25 22:57, Richard Henderson wrote:
>> Check 32 vs 64-bit state.
>>
>> Cc: qemu-ppc@nongnu.org
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/ppc/cpu_init.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
>> index cf88a18244..1f18967b62 100644
>> --- a/target/ppc/cpu_init.c
>> +++ b/target/ppc/cpu_init.c
>> @@ -7386,6 +7386,12 @@ static void ppc_cpu_exec_exit(CPUState *cs)
>>           cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu);
>>       }
>>   }
>> +
>> +static vaddr ppc_pointer_wrap(CPUState *cs, int mmu_idx,
>> +                              vaddr result, vaddr base)
>> +{
>> +    return (cpu_env(cs)->hflags >> HFLAGS_64) & 1 ? result : (uint32_t)result;
> 
> Alternatively expose and use NARROW_MODE().

Again, that's a DisasContext thing, only valid during translation.


r~
diff mbox series

Patch

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index cf88a18244..1f18967b62 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7386,6 +7386,12 @@  static void ppc_cpu_exec_exit(CPUState *cs)
         cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu);
     }
 }
+
+static vaddr ppc_pointer_wrap(CPUState *cs, int mmu_idx,
+                              vaddr result, vaddr base)
+{
+    return (cpu_env(cs)->hflags >> HFLAGS_64) & 1 ? result : (uint32_t)result;
+}
 #endif /* CONFIG_TCG */
 
 #endif /* !CONFIG_USER_ONLY */
@@ -7490,6 +7496,7 @@  static const TCGCPUOps ppc_tcg_ops = {
   .record_sigsegv = ppc_cpu_record_sigsegv,
 #else
   .tlb_fill = ppc_cpu_tlb_fill,
+  .pointer_wrap = ppc_pointer_wrap,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .cpu_exec_halt = ppc_cpu_has_work,
   .cpu_exec_reset = cpu_reset,