| Message ID | 20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com |
|---|---|
| Headers | show |
| Series | Add support for Amlogic S7/S7D/S6 pinctrl | expand |
On Wed, 14 May 2025 15:01:27 +0800, Xianwei Zhao wrote: > In some Amlogic SoCs, to save register space or due to some > abnormal arrangements, two sets of pins share one mux register. > A group starting from pin0 is the main pin group, which acquires > the register address through DTS and has management permissions, > but the register bit offset is undetermined. > Another GPIO group as a subordinate group. Some pins mux use share > register and bit offset from bit0 . But this group do not have > register management permissions. > > In SoC S7 and S7D, GPIOX(16~19) mux share with GPIOCC mux register. > > In SoC S6, GPIOX(16~19) mux share with GPIOCC mux register, and GPIOD(6) > mux share with GPIOF mux register. > > Add S7/S7D/S6 pinctrl compatible string and device node. > > Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> > --- > Xianwei Zhao (8): > dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7 > dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7D > dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S6 > pinctrl: meson: a4: remove special data processing > pinctrl: meson: support amlogic S6/S7/S7D SoC > dts: arm64: amlogic: add S7 pinctrl node > dts: arm64: amlogic: add S7D pinctrl node > dts: arm64: amlogic: add S6 pinctrl node > > .../bindings/pinctrl/amlogic,pinctrl-a4.yaml | 9 +- > arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 97 ++++++++++++++++++ > arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++ > arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 90 +++++++++++++++++ > drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 111 ++++++++++++++++----- > 5 files changed, 363 insertions(+), 25 deletions(-) > --- > base-commit: aa94665adc28f3fdc3de2979ac1e98bae961d6ca > change-id: 20250514-s6-s7-pinctrl-af1ebda88a4e > > Best regards, > -- > Xianwei Zhao <xianwei.zhao@amlogic.com> > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: using specified base-commit aa94665adc28f3fdc3de2979ac1e98bae961d6ca If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/amlogic/' for 20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com: arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dtb: bus@fe000000 (simple-bus): pinctrl:ranges: [[0, 0, 0, 16384, 0, 832]] is not of type 'boolean' from schema $id: http://devicetree.org/schemas/simple-bus.yaml# arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dtb: bus@fe000000 (simple-bus): pinctrl:ranges: [[0, 0, 0, 16384, 0, 832]] is not of type 'boolean' from schema $id: http://devicetree.org/schemas/simple-bus.yaml# arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dtb: bus@fe000000 (simple-bus): pinctrl:ranges: [[0, 0, 0, 16384, 0, 832]] is not of type 'boolean' from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
In some Amlogic SoCs, to save register space or due to some abnormal arrangements, two sets of pins share one mux register. A group starting from pin0 is the main pin group, which acquires the register address through DTS and has management permissions, but the register bit offset is undetermined. Another GPIO group as a subordinate group. Some pins mux use share register and bit offset from bit0 . But this group do not have register management permissions. In SoC S7 and S7D, GPIOX(16~19) mux share with GPIOCC mux register. In SoC S6, GPIOX(16~19) mux share with GPIOCC mux register, and GPIOD(6) mux share with GPIOF mux register. Add S7/S7D/S6 pinctrl compatible string and device node. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> --- Xianwei Zhao (8): dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7 dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7D dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S6 pinctrl: meson: a4: remove special data processing pinctrl: meson: support amlogic S6/S7/S7D SoC dts: arm64: amlogic: add S7 pinctrl node dts: arm64: amlogic: add S7D pinctrl node dts: arm64: amlogic: add S6 pinctrl node .../bindings/pinctrl/amlogic,pinctrl-a4.yaml | 9 +- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 97 ++++++++++++++++++ arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++ arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 90 +++++++++++++++++ drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 111 ++++++++++++++++----- 5 files changed, 363 insertions(+), 25 deletions(-) --- base-commit: aa94665adc28f3fdc3de2979ac1e98bae961d6ca change-id: 20250514-s6-s7-pinctrl-af1ebda88a4e Best regards,