From patchwork Fri Nov 10 14:20:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 118534 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp2257476edl; Fri, 10 Nov 2017 06:21:52 -0800 (PST) X-Google-Smtp-Source: AGs4zMYXNtYrF6YuGNNLrZVjnVoSkYQ4ghHgkF6kGIRCADYid9vG4xdpmZJNYrhft9UVqw/dSIRS X-Received: by 10.98.85.71 with SMTP id j68mr549758pfb.222.1510323712342; Fri, 10 Nov 2017 06:21:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510323712; cv=none; d=google.com; s=arc-20160816; b=j8qzBeAkn4czvg4t3Y0WIwbrwudirTcQfJuymL+hQpcJnPEYHCmmZNB1tSdN1j539H 6gKCBiC7NE2izLWDmKwk8ZtewXWQ9AH2dH6j5ZbYv5f1XV4fRQP1Hn0Dvi2s4U6eETF+ V5weRarKcAMd6kaSp30TPvel7QjCP4tml2Il2GY1HPj8CQklcuN4xTY3n1kwrR2VqQ5n s0wSNIp8dXkOtSdyEToc5OzuxjuE/iTl45fRtqIzXPUQEECVCf/3cBjpIYSfpjVpz7Gu urO2hKoVS3FHTt1dLbSKseYGS+K/6Oigq8DETnxBw25G3uwZ9R0740IvqscpxEGEYclH 8VRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :delivered-to:arc-authentication-results; bh=toN3scsczodi5NwAu1PX/iEGW4PcQuc6yBuYZSyjqXo=; b=O/f1/W00TKqNBr5c3RszJb4Vz0Bfj9KwJsnPOH2tCcmolTcB+/gAUeG0yfbch1NIZ0 kBOJxIXmVB8WoRGc1aWJW99s917fxNtNyoTg4Qjjk4kg4Rv3EqW1NYzr8AgmwOVbimss SENERBSJdn6bGc7L6Q99kOJrHLL1+aaF2QWfUdkqRoLNMAdkP+W/Sc7FVNILDYUw9QHI CdJtZCQxtlWqw+x3aGKNB9KM9L8pJ0Z7lgJtb8hw7XV5sEZ3ikuTKvY70nAbZCo6zYhL 9kXnLK/Be9atKwSjds1u7rMf2LJ6Ttmg9MY1NzEa30jxSn5QpTwExoqy9XLAfL8LPRfR PJ3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SsRnKv/a; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id r15si4311030pgt.573.2017.11.10.06.21.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:21:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SsRnKv/a; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 830AD20355206; Fri, 10 Nov 2017 06:17:48 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::233; helo=mail-wr0-x233.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x233.google.com (mail-wr0-x233.google.com [IPv6:2a00:1450:400c:c0c::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3CC6021B00DC0 for ; Fri, 10 Nov 2017 06:17:46 -0800 (PST) Received: by mail-wr0-x233.google.com with SMTP id p96so8729838wrb.7 for ; Fri, 10 Nov 2017 06:21:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=vIg6i5CMnMQuwNklm7yI2w/0yVIkYqzaEokvi0NZUy0=; b=SsRnKv/aUUvk1xZCTpgAAdNsr6SYDOCKrnvnsQ14f8QZKXE5j/lr/ujeIkWTdRg0RJ Faj5ZDnL2SMw+RaKzBvpimEX9lO8eZOBlSv157B8lmWNKbabFdvaWSfJzbcF4Zamyhzz W0Buk9dmmVyJj5kRm4Z3isKyG98NiLJLRn4Is= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vIg6i5CMnMQuwNklm7yI2w/0yVIkYqzaEokvi0NZUy0=; b=TpIeEqLkcHbMThUiE4qpGKAmIECX5q4yH/gVV7nbKIMq7CjHTDuZVwb5mEYJpUw1Pd pjnmLzKP1vOhm3MiHo1ekGKVeZhHQLhc+2rfeMDt3p4+u+E3Q/F3OiFhv3y9CBO0JVLT 7UUwEmlfeBY4rD50NdgaWSQaqvTkvIbm+qXDWTpx6hN9NOJZWMYoQj2quF+DicSEAZnb y9rTyL6m2dHXW3O+E/Oupg1fDkT4MlQ9riLesQwOcLa25wzqojoZGo+264EJISluxTqv FMcs9M1IqDr5dizgBWyfb6py/9Gt90o5Wm2+RqcBRQ+ZUTUHG2Rpb2u5jl9pQGJt1u1j XAUw== X-Gm-Message-State: AJaThX5S3PAr8gH+rPQ3Ht3XsnJdOwE5RH/jk61jHCAiVcFP1k7g9n+l bez9aiBR0mspB7ldXjO/WtJJ48MGyPc= X-Received: by 10.223.197.131 with SMTP id m3mr520773wrg.0.1510323707993; Fri, 10 Nov 2017 06:21:47 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.21.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:21:47 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Fri, 10 Nov 2017 14:20:53 +0000 Message-Id: <20171110142127.12018-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms v4 00/34] add support for Socionext SynQuacer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" This adds support for the Socionext Synquacer SC2A11 evaluation board and revision 0.1/0.2 of the Developer Box. It implements support for the core peripherals (CPU, GIC, serial), and for the two PCIe RCs present on this board, as well as the NETSEC network controller. The DT description contains references to drivers that are not upstream yet, and will be merged into Linux v4.15 at the earliest. No other OS support is currently planned (as far as I am aware) The non-volatile EFI variable store is backed by the SPI NOR flash, which is therefore not exposed to the OS. Note that it occupies the 'devtree' partition, which must be wiped before use. A driver for the NETSEC network interface is included, which means network boot is supported as well. (Note that this driver deviates in coding style. This code is based on the platform independent driver provided by Socionext, and making cosmetic changes to it will only make it more difficult to track upstream changes) Changes since v3: - remove ACPI support for now, we can add it on top if we manage to sort out all the SoC quirks that make it difficult to have full support under ACPI - add RTC support to DeveloperBox - add eMMC support to SynQuacerEvalBoard - incorporate review feedback on the SPI NOR driver (which was possible after noticing that I did in fact have a manual for this IP) - map NOR and EEPROM as writeback cacheable non-shareable; this allows the split FV hack to be reverted, and improves boot time considerably - some other minor changes have been applied, these have been added to the individual patches as notes Changes since v2: - converted NETSEC driver to UEFI driver model - added a platform DXE driver that declares the non-discoverable NETSEC device for the UEFI driver model driver to bind to - remove hardcoded DRAM information - everything is now retrieved from ARM Trusted Firmware - added DT descriptions of the GPIO and interrupt controller IP blocks - addressed various style issues and merge errors highlighted by Leif Ard Biesheuvel (33): Silicon/SynQuacer: add package with platform headers Silicon/Socionext: add driver for NETSEC network controller Silicon/Socionext: add PlatformPeilib implementation for SynQuacer Silicon/SynQuacer: implement a platform DXE driver Silicon/SynQuacer: add MemoryInitPeiLib implementation Platform: add support for Socionext SynQuacer eval board Silicon/SynQuacer: implement PciSegmentLib to support dual RCs Silicon/SynQuacer: implement PciHostBridgeLib support Silicon/SynQuacer: implement EFI_CPU_IO2_PROTOCOL Platform/SynQuacerEvalBoard: add PCI support Platform/SynQuacerEvalBoard: add NETSEC driver Silicon/SynQuacer: add device tree support for eval board Silicon/SynQuacer: add NorFlashPlatformLib implementation Platform/SynQuacer: incorporate NOR flash and variable drivers Silicon/SynQuacer: implement PlatformFlashAccessLib SynQuacer/SynQuacerMemoryInitPeiLib: add capsule support Socionext/SynQuacerEvalBoard: wire up basic capsule support Socionext/SynQuacerEvalBoard: switch to execute in place Platform/SynQuacerEvalBoard: add signed capsule update support Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards Platform/Socionext: add support for Socionext Developer Box rev 0.1 Platform/DeveloperBox: add ConsolePrefDxe driver Silicon/SynQuacer: add description of GPIO block to device tree Silicon/SynQuacer: add description of EXIU to the device tree Silicon/SynQuacer: add DT description of the SDHCI controller Silicon/SynQuacerMemoryInitPeiLib: ignore capsules when clearing NVRAM Silicon/SynQuacer: implement PEIM that exposes GPIO PPI Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch Silicon/NXP: add RTC support library for PCF8563 I2C IP Silicon/Socionext: implement I2C master protocol for SynQuacer I2C Platform/DeveloperBox: wire up RTC support Platform/DeveloperBox: add description of power button to DT Platform/SynQuacerEvalBoard: add eMMC driver stack Pipat Methavanitpong (1): Silicon/Socionext: add driver for SPI NOR flash Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 630 +++++++++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 465 +++++++ Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 46 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 68 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 80 ++ Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 25 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 609 ++++++++ Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 450 ++++++ Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 46 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 68 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 80 ++ Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 25 + Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | 402 ++++++ Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec | 29 + Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | 52 + Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 46 + Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf | 33 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 561 ++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 32 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf | 33 + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec | 31 + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf | 81 ++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Reg.h | 244 ++++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c | 138 ++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.c | 1391 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.h | 357 +++++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c | 853 ++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/ComponentName.c | 186 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/DriverBinding.c | 245 ++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 1056 ++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 46 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h | 118 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 70 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h | 736 ++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h | 45 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h | 24 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c | 88 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h | 52 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c | 1391 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h | 111 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c | 1454 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h | 210 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 1385 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h | 38 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 219 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h | 222 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h | 368 +++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 25 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 263 ++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c | 176 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 204 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 178 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 64 + Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c | 203 +++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf | 47 + Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c | 185 +++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c | 238 ++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 586 ++++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h | 162 +++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | 59 + Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c | 590 ++++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf | 50 + Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h | 30 + Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 68 + Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 63 + Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h | 64 + Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 70 + Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf | 41 + Silicon/Socionext/SynQuacer/Library/SynQuacerLib/AArch64/SynQuacerHelper.S | 87 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerLib/Arm/SynQuacerHelper.S | 87 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacer.c | 125 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf | 43 + Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 276 ++++ Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf | 70 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 225 +++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 50 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 394 ++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c | 1398 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf | 35 + Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c | 251 ++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf | 38 + Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 146 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 56 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 39 + 85 files changed, 21662 insertions(+) create mode 100644 Platform/Socionext/DeveloperBox/DeveloperBox.dsc create mode 100644 Platform/Socionext/DeveloperBox/DeveloperBox.fdf create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc create mode 100644 Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc create mode 100644 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts create mode 100644 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Reg.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/ComponentName.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/DriverBinding.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c create mode 100644 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Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf create mode 100644 Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h create mode 100644 Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h create mode 100644 Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h create mode 100644 Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h create mode 100644 Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c create mode 100644 Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/AArch64/SynQuacerHelper.S create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/Arm/SynQuacerHelper.S create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacer.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf create mode 100644 Silicon/Socionext/SynQuacer/SynQuacer.dec -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel