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[209.132.180.67]) by mx.google.com with ESMTP id e11si6553348pgf.450.2018.11.10.21.09.24; Sat, 10 Nov 2018 21:09:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZQI7ytwI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727447AbeKKO4A (ORCPT + 32 others); Sun, 11 Nov 2018 09:56:00 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52160 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727184AbeKKO4A (ORCPT ); Sun, 11 Nov 2018 09:56:00 -0500 Received: by mail-wm1-f67.google.com with SMTP id w7-v6so5402947wmc.1 for ; Sat, 10 Nov 2018 21:08:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Ow2naLIzo/IFM+0nIo0ADveDbpQEOg73+66OVgTfy9U=; b=ZQI7ytwIjjXjYAjMgqVxg5oX0CEBzSbEVvYwYsQp5QaYUmbf2M94wheVNdyPWeBDVN diFTDtCflyNToZ2xD1XUkVqB7Vp8UPa3FWtsIX5NV9d38pibkxgQBQhlHZxgjOYQFgxn PdtwbZeyW/6HCqLgoC/9TxI8Gt4DtjJvJuYrI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Ow2naLIzo/IFM+0nIo0ADveDbpQEOg73+66OVgTfy9U=; b=TNI1uMjES2Zj4F8kx1AJ+uPVzCL4nV2cLVD+eoR0C2gwPAFcrB1uldgE+4m63iJWyV mFTRiF1h1FCkbm98ql6k5RGhy3i4Q3KpSmYebf3ZCk9raNmDSkx5tSjVLG9CFWonYkqs h++YrAZzG5MhYZC4cikQbkjB8ByDJg5SS6gn3yipeiXorJR4xI/P3WpF44ZsHtPCYfCc zJO3OAKIfDli5emm3gNgNi4pYeEfWvYIU/vRS2Y79YppK/I45j1In3OoB2CKBaUUNzOE AWwqbXaMQzY/vk7wLirl/IbE6EE4SGvz8TC1q0AcHXt1wsk92uId7mizTyHU0KK87+cL 7vQg== X-Gm-Message-State: AGRZ1gK1QBzLqkcQBAL6W41LupYjHcEr00a0aS7LBcDllaunHK3FxKiF zMvKqBV5jz5PrqGXhB2WFgNEAg== X-Received: by 2002:a1c:b645:: with SMTP id g66-v6mr4098881wmf.25.1541912910203; Sat, 10 Nov 2018 21:08:30 -0800 (PST) Received: from localhost.localdomain ([209.250.228.18]) by smtp.gmail.com with ESMTPSA id b66-v6sm4471045wmb.21.2018.11.10.21.08.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 10 Nov 2018 21:08:29 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Mathieu Poirier , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mike Leach , Robert Walker , Al Grant , Coresight ML Cc: Leo Yan Subject: [PATCH v2 0/2] perf cs-etm: Add support for sample flags Date: Sun, 11 Nov 2018 13:07:54 +0800 Message-Id: <1541912876-20967-1-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch seris adds support for sample flags so can facilitate perf to print sample flags for branch instruction. The patch 0001 is to set branch instruction flags in packet, this patch has the core code in this series to set flags according to the decoding element type, and also based on the elements including instruction type, subtype and condition flag to help making decision to set flags value. The patch 0002 is to support sample flags by copying the flags value from packet structure to sample structure, and it includes three fixing up for TRACE_ON/TRACE_OFF and exception packets. The patch series is based on OpenCSD v0.10.0 and Rob's patch 'perf: Support for Arm A32/T32 instruction sets in CoreSight trace' also is prerequisite to support A32/T32 ISAs. This patch series is applied on the acme's perf core branch [1] with the latest commit f1d23afaf677 ("perf bpf: Reduce the hardcoded .max_entries for pid_maps") and has two prerequisites: 1) It's dependent on Rob's patch 'perf: Support for Arm A32/T32 instruction sets in CoreSight trace' [2]; 2) It's dependent on another patch series 'perf cs-etm: Correct packets handling' [3]. After applying the dependency patches and this patch series, we can verify sample flags with below command: # perf script -F,-time,+flags,+ip,+sym,+dso,+addr,+symoff -k vmlinux Changes from v1: * Moved exception packets handling patches into patch series 'perf cs-etm: Correct packets handling'. * Added sample flags fixing up for TRACE_OFF packet. * Created a new function which is used to maintain flags fixing up. [1] https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/log/?h=perf/core [2] http://archive.armlinux.org.uk/lurker/message/20181109.091126.9d69489d.en.html [3] http://archive.armlinux.org.uk/lurker/message/20181111.045938.782b378b.en.html Leo Yan (2): perf cs-etm: Set branch instruction flags in packet perf cs-etm: Add support sample flags tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 168 ++++++++++++++++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 43 +++++- 3 files changed, 210 insertions(+), 2 deletions(-) -- 2.7.4