From patchwork Fri Dec 14 15:11:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 153881 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2183945ljp; Fri, 14 Dec 2018 07:11:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/VOMNXksi9JeF8waWQoC8QzSDGpzo/BCqeMYVWawqRwGiDl4n35d+ZUOQdvLadzPkO+NuE9 X-Received: by 2002:a63:7d06:: with SMTP id y6mr3008345pgc.171.1544800297182; Fri, 14 Dec 2018 07:11:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544800297; cv=none; d=google.com; s=arc-20160816; b=XvwuoDksFVvHe4pVt/WnvQOSvIc85Pcl6G3y5HWlfu0CGtWP/vP+UUkYfv52EvAqmT OVp8KW8y/CY9eKLwOtgOEsanGaipyQVdnYn9FbDQ4OMGZ26gbs10oFHY+pV/G67GYWeH CFyQmcB6jR5UAW0CzNFMGkCL6M/fYNoxQIxrRyTrsLu9hjPwtKnlhmaDtTsv4OfOM/LD wDUNWAwW1dYN/ApSxfVLDMsJLVekfgAAJuXK91KtBvwOufLkPxb4iGHnrTamphhJJ0MR PE6JgGpVH8gxucNu7rOEJYS/OpLHUZr8Yqxsf2IwQRDpRslB/ZyScBnFhVy7nm0skO2K jxzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=2OEhyVYGwNvGpX/TNQZpzfpD5NsrteBRRKArChDs2kg=; b=xJz4Q0sab8yaS3eXmCUZm2BLz3aEG9Yt93847DIKxhQ8/BU68hBlhSr/ZsKpue9rqN yScYbZoopwFG8OoOD+OIFRG62uJYrMRT68osBXdkeC0IND+827AWtkFi+I+vS11WXhWd D7PbdXTxIhAoq2u88VYe+qVJOVlAyxaBJt5VnaK+p/kSwDJW1K5p+h5wgTs6QYa3T5g4 jB//nS3/RYkLNz1oD5QyWVMZcFXSbvfsDIyeQLw3QaTFvisn2EiUSSvedyxvsKsdeKvT 5rBTZ7aI32MpizNwXANa5orxL/aLUxxgvMO/xWkbTbdgDUfoic/rdehR11QdL4x5oE8A uLkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iqegc8gn; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 206si3976885pga.240.2018.12.14.07.11.36; Fri, 14 Dec 2018 07:11:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iqegc8gn; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730113AbeLNPLg (ORCPT + 6 others); Fri, 14 Dec 2018 10:11:36 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:37609 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729737AbeLNPLg (ORCPT ); Fri, 14 Dec 2018 10:11:36 -0500 Received: by mail-wr1-f68.google.com with SMTP id s12so5327289wrt.4 for ; Fri, 14 Dec 2018 07:11:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=2OEhyVYGwNvGpX/TNQZpzfpD5NsrteBRRKArChDs2kg=; b=iqegc8gnG9oY1FO5Zo5pNCjRd1E9N7JkmsEs5fd06a2ecUBk1zH4fhsBwpAH1NO94Z OJhpX5P64lpJKbUIgkmd+RkqNwBSq+dFLKHD+N9nnhVPGUjT6A+MJT61fAnvvfjonEIk f5X51WP8E9nbXb6kzSibmn3MrpYOuUZ/ovJFo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=2OEhyVYGwNvGpX/TNQZpzfpD5NsrteBRRKArChDs2kg=; b=sx4OTexemwwb7urAIK8Afi4ouoeeBJkU5OExqV92U2VVdyT7pyh2cvGBQZJKAjSm3Y guCo936lx/oSHkvb1XiaD++hFHwWAWPWB4uS9NGL7BuAwIyMs3G6VCJ9T7yhZ922VxuS zFD9Hfn8H6P00WNkAIfA/J87C9RSutfmn8LF7eDTWSSrOHjbB2Awpv6zSFkRNtTQ/No7 /3VC8rpxPSh1flUBVticJB/iHrHZKhoQfmPpepSU56lFXUkn5gmlqZzllUWp1maJgl3R IgHExk6JHikZW+8LiUK+wohLzXRWhAvoq+rDrcH7XsQcGXiw2SjmDWaF3fE7Ewl7NGu0 aYuw== X-Gm-Message-State: AA+aEWaO5AEingtDyshmanz8k1xjKTkPNo4/uWhcfNFzRoOg/zfLdy0k uk3AskUT224/WT0do2PO4HCyeA== X-Received: by 2002:adf:dec4:: with SMTP id i4mr2803270wrn.307.1544800294582; Fri, 14 Dec 2018 07:11:34 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:113f:f362:2090:a70c:c5c6:347e]) by smtp.gmail.com with ESMTPSA id i13sm3381567wrw.32.2018.12.14.07.11.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 14 Dec 2018 07:11:34 -0800 (PST) From: Benjamin Gaignard To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v2 0/2] Make STM32 interrupt controller use hwspinlock Date: Fri, 14 Dec 2018 16:11:26 +0100 Message-Id: <20181214151128.10005-1-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.15.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Benjamin Gaignard This series allow to protect STM32 interrupt controller configuration registers with a hwspinlock to avoid conflicting accesses between processors. version 2: - rework hwspinlock locking sequence in stm32 irqchip to take care of the cases where hwspinlock node is disabled or not yet probed Benjamin Gaignard (2): irqchip: stm32: protect configuration registers with hwspinlock ARM: dts: stm32: Add hwlock for irqchip on stm32mp157 arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/irqchip/irq-stm32-exti.c | 116 ++++++++++++++++++++++++++++++++----- 2 files changed, 101 insertions(+), 16 deletions(-) -- 2.15.0