[v2,0/5] pin and gpio controller driver for Renesas RZ/G2L

Message ID 20210712194422.12405-1-prabhakar.mahadev-lad.rj@bp.renesas.com
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  • pin and gpio controller driver for Renesas RZ/G2L
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Lad Prabhakar July 12, 2021, 7:44 p.m.
Hi All,

This patch series adds pin and gpio controller driver for Renesas RZ/G2L
SoC. RZ/G2L has a simple pin and GPIO controller combined similar to RZ/A2.

This patch series applies on top of https://git.kernel.org/pub/scm/linux/
kernel/git/geert/renesas-drivers.git/log/?h=topic/rzg2l-update-clock-defs-v4

Cheers,
Prabhakar

Changes for v2:
* Added support for per pin pinmux support
* Added support for pins to set configs
* Dropped pfc-r9a07g044.c/h
* Fixed review comments pointed by Geert
* Included clock/reset changes
* Included DTS/I changes

Lad Prabhakar (5):
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add DT bindings for
    RZ/G2L pinctrl
  pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
  drivers: clk: renesas: r9a07g044-cpg: Add GPIO clock and reset entries
  arm64: dts: renesas: r9a07g044: Add pinctrl node
  arm64: dts: renesas: rzg2l-smarc: Add scif0 pins

 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |  155 +++
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |   13 +
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  |   10 +
 drivers/clk/renesas/r9a07g044-cpg.c           |    5 +
 drivers/pinctrl/renesas/Kconfig               |   11 +
 drivers/pinctrl/renesas/Makefile              |    1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 1196 +++++++++++++++++
 include/dt-bindings/pinctrl/rzg2l-pinctrl.h   |   23 +
 8 files changed, 1414 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
 create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c
 create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h


base-commit: 06c1e6911a7a76b446e4b00fc8bad5d8465932f8

Comments

Sergei Shtylyov July 13, 2021, 11:18 a.m. | #1
On 12.07.2021 22:44, Lad Prabhakar wrote:

> Add scif0 pins in pinctrl node and update the scif0 node
> to include pinctrl property.

    Properties? There are a couple... :-)

> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>   arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> index adcd4f50519e..0987163f25ee 100644
> --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
[...]
>   	clock-frequency = <24000000>;
>   };
>   
> +&pinctrl {
> +	scif0_pins: scif0 {
> +		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
> +			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
> +	};
> +};
> +
>   &scif0 {
> +	pinctrl-0 = <&scif0_pins>;
> +	pinctrl-names = "default";
>   	status = "okay";
>   };
> 

MBR, Sergei
Geert Uytterhoeven July 13, 2021, 1:37 p.m. | #2
On Mon, Jul 12, 2021 at 9:44 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add GPIO clock and reset entries in CPG driver.

>

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>


Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

i.e. will queue in renesas-clk-for-v5.15.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Lad, Prabhakar July 13, 2021, 2:34 p.m. | #3
Hi Sergei,

Thank you for the review.

On Tue, Jul 13, 2021 at 12:18 PM Sergei Shtylyov
<sergei.shtylyov@gmail.com> wrote:
>

> On 12.07.2021 22:44, Lad Prabhakar wrote:

>

> > Add scif0 pins in pinctrl node and update the scif0 node

> > to include pinctrl property.

>

>     Properties? There are a couple... :-)

>

Agreed will update the commit message.

Cheers,
Prabhakar

> >

> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

> > ---

> >   arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 ++++++++++

> >   1 file changed, 10 insertions(+)

> >

> > diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

> > index adcd4f50519e..0987163f25ee 100644

> > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

> [...]

> >       clock-frequency = <24000000>;

> >   };

> >

> > +&pinctrl {

> > +     scif0_pins: scif0 {

> > +             pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */

> > +                      <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */

> > +     };

> > +};

> > +

> >   &scif0 {

> > +     pinctrl-0 = <&scif0_pins>;

> > +     pinctrl-names = "default";

> >       status = "okay";

> >   };

> >

>

> MBR, Sergei
Rob Herring July 13, 2021, 9:37 p.m. | #4
On Mon, 12 Jul 2021 20:44:18 +0100, Lad Prabhakar wrote:
> Add device tree binding documentation and header file for Renesas
> RZ/G2L pinctrl.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../pinctrl/renesas,rzg2l-pinctrl.yaml        | 155 ++++++++++++++++++
>  include/dt-bindings/pinctrl/rzg2l-pinctrl.h   |  23 +++
>  2 files changed, 178 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
>  create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.example.dts:29.34-35 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1418: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1504169

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Geert Uytterhoeven July 20, 2021, 1:42 p.m. | #5
Hi Prabhakar,

On Mon, Jul 12, 2021 at 9:44 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add device tree binding documentation and header file for Renesas
> RZ/G2L pinctrl.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides constants for Renesas RZ/G2L family pinctrl bindings.
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H
> +#define __DT_BINDINGS_RZG2L_PINCTRL_H
> +
> +#define RZG2L_PINS_PER_PORT    8
> +
> +/*
> + * Create the pin index from its bank and position numbers and store in
> + * the upper 16 bits the alternate function identifier
> + */
> +#define RZG2L_PORT_PINMUX(b, p, f)     ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
> +
> +/* Convert a port and pin label to its global pin index */
> + #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))

I know this was copied from RZ/A2, but some consistency in the naming
(b or bank vs. port, p vs. pin) would be nice to have.

> +
> +#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert
Linus Walleij July 30, 2021, 12:36 p.m. | #6
On Mon, Jul 12, 2021 at 9:44 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:

> Add device tree binding documentation and header file for Renesas
> RZ/G2L pinctrl.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Looks good to me and I essentially trust Geert to review this
driver and eventually merge it and send it by pull request
as well.

Yours,
Linus Walleij