| Message ID | 20210915222847.10239-1-asmaa@nvidia.com |
|---|---|
| Headers | show |
| Series | gpio: mlxbf2: Introduce proper interrupt handling | expand |
> + /* Enable PHY interrupt by setting the priority level */ This should be an abstract driver for a collection of GPIO lines. Yes, one of these GPIOs is used for the PHY, but the GPIO driver does not care. So please remove this comment. Asmaa>> Done > + val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); > + val |= BIT(offset); > + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); What exactly does this do? It appears to clear the interrupt, if i understand mlxbf2_gpio_irq_handler(). I don't know the GPIO framework well enough to know if this is correct. It does mean if the interrupt signal is active but masked, and you enable it, you appear to loose the interrupt? Maybe you want the interrupt to fire as soon as it is enabled? Asmaa>> YU_GPIO_CAUSE_OR_CLRCAUSE - Makes sure the interrupt is initially cleared. Otherwise, we will not receive further interrupts. YU_GPIO_CAUSE_OR_EVTEN0 - All interrupts are disabled by default. This register is what actually unmasks/enables the specific interrupt to start "firing". > +static void mlxbf2_gpio_irq_mask(struct irq_data *irqd) { > + mlxbf2_gpio_irq_disable(irqd); > +} > + > +static void mlxbf2_gpio_irq_unmask(struct irq_data *irqd) { > + mlxbf2_gpio_irq_enable(irqd); > +} Do these two functions have any value? Asmaa>> This code is actually not being called. enable/disable is what's being called. So I will remove it. > + switch (type & IRQ_TYPE_SENSE_MASK) { > + case IRQ_TYPE_EDGE_BOTH: > + case IRQ_TYPE_LEVEL_MASK: > + fall = true; > + rise = true; > + break; > + case IRQ_TYPE_EDGE_RISING: > + case IRQ_TYPE_LEVEL_HIGH: > + rise = true; > + break; > + case IRQ_TYPE_EDGE_FALLING: > + case IRQ_TYPE_LEVEL_LOW: > + fall = true; > + break; This looks wrong. You cannot map a level interrupt into an edge. It looks like your hardware only supports edges. If asked to do level, return -EINVAL. Asmaa>> done > + > + /* The INT_N interrupt level is active low. > + * So enable cause fall bit to detect when GPIO > + * state goes low. > + */ I don't understand this comment. Asmaa>> removed.
On Thu, Sep 16, 2021 at 03:48:51PM +0000, Asmaa Mnebhi wrote: > > + /* Enable PHY interrupt by setting the priority level */ > > This should be an abstract driver for a collection of GPIO lines. > Yes, one of these GPIOs is used for the PHY, but the GPIO driver does not care. So please remove this comment. > Asmaa>> Done > > > + val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); > > + val |= BIT(offset); > > + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); > > What exactly does this do? It appears to clear the interrupt, if i understand mlxbf2_gpio_irq_handler(). I don't know the GPIO framework well enough to know if this is correct. It does mean if the interrupt signal is active but masked, and you enable it, you appear to loose the interrupt? Maybe you want the interrupt to fire as soon as it is enabled? > > Asmaa>> > YU_GPIO_CAUSE_OR_CLRCAUSE - Makes sure the interrupt is initially cleared. Otherwise, we will not receive further interrupts. If the interrupt status bit is set, as soon as you unmask the interrupt, the hardware should fire the interrupt. At least, that is how interrupt controllers usually work. A typical pattern is that the interrupt fires. You mask it, ack it, and then do what is needed to actually handle the interrupt. While doing the handling, the hardware can indicate the interrupt again. But since it is masked nothing happened. This avoids your interrupt handler going recursive. Once the handler has finished, the interrupt is unmasked. At this point it actually fires, triggering the interrupt handler again. Please also get your email client fixed. I wrap my emails at around 75 characters. Your mailer has destroyed it. Your text should also be wrapped at about 75 characters. Andrew