Message ID | 1498801600-20896-9-git-send-email-amit.pundir@linaro.org |
---|---|
State | New |
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[209.132.180.67]) by mx.google.com with ESMTP id b12si1658852plk.568.2017.06.29.22.47.13; Thu, 29 Jun 2017 22:47:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=WP4SYZov; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751954AbdF3FrM (ORCPT <rfc822;sumit.semwal@linaro.org> + 6 others); Fri, 30 Jun 2017 01:47:12 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:34022 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751951AbdF3FrL (ORCPT <rfc822;stable@vger.kernel.org>); Fri, 30 Jun 2017 01:47:11 -0400 Received: by mail-pf0-f176.google.com with SMTP id s66so61548343pfs.1 for <stable@vger.kernel.org>; Thu, 29 Jun 2017 22:47:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dgUFbN42bUExTBiKQuWWHB0EIV0fAWCgdJ5DTTjMntQ=; b=WP4SYZov6wJipxSoTDlGjARFHLQ1OQhlc/LVEdPbepsJ0idTX0QTOaPohNi28UhTFT g7asy32Q0y/w+al/uD5IwH8YHzmuAGlmWQd0QHhmpE4aYcH3yZSwqFWCr54FS0a62Wlj aU5NPY3tksCGTArlAelmhnNOrKLQw2+o665No= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dgUFbN42bUExTBiKQuWWHB0EIV0fAWCgdJ5DTTjMntQ=; b=MEFejAZwSLk8Jn9LXXCnX0cY7F4M/pjiygbV5RxWV8ywJhwVDVTLuADVQ/kt3Zqn5k 7Tj5Hc65Mabq/j4vGkU2V4xb+1WIVMDwtgi3vqloElTRlYJxD6A2Mv3bk/EhQiZ3SfD2 UOcKM5gEd6j9Wdke9WyNrg9/2tMDxhN6iz/FlzD1u56Jk3AuWk0A6MuEzXqekj8bhYDK w9ShAYDJUHsZOzMokxeyYn1+BkDDrIQQDzBJ9FZtOKVNLPFcb3838CJzTRQF7dOk2+EI c5i7FiTDzNgydkpnykliV/pISrlg/ssk2Ph+LJw55TuN2mnNY4PEAbHTE+eyjZkq+Xs/ R0uA== X-Gm-Message-State: AKS2vOxey+NbLAhDOsjFaUnWaITFNb2kAR1SOhuLfcQJgIuC4FwR2GVO aieR5roebaXEca1kqPHGVg== X-Received: by 10.84.216.26 with SMTP id m26mr22626914pli.112.1498801631078; Thu, 29 Jun 2017 22:47:11 -0700 (PDT) Received: from localhost.localdomain ([106.51.129.233]) by smtp.gmail.com with ESMTPSA id a187sm11405550pgc.37.2017.06.29.22.47.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Jun 2017 22:47:09 -0700 (PDT) From: Amit Pundir <amit.pundir@linaro.org> To: Greg KH <gregkh@linuxfoundation.org> Cc: Stable <stable@vger.kernel.org>, =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_?= =?utf-8?q?Rojas?= <noltari@gmail.com>, john@phrozen.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle <ralf@linux-mips.org> Subject: [PATCH for-4.4 08/16] MIPS: ralink: fix MT7628 pinmux typos Date: Fri, 30 Jun 2017 11:16:32 +0530 Message-Id: <1498801600-20896-9-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498801600-20896-1-git-send-email-amit.pundir@linaro.org> References: <1498801600-20896-1-git-send-email-amit.pundir@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: <stable.vger.kernel.org> X-Mailing-List: stable@vger.kernel.org |
Series |
Stable commits picked up from lede project
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diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 4c17dc6e8ae9..37cfc7d3c185 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -223,9 +223,9 @@ static struct rt2880_pmx_func wled_an_grp_mt7628[] = { #define MT7628_GPIO_MODE_GPIO 0 static struct rt2880_pmx_group mt7628an_pinmux_data[] = { - GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, + GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1), - GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, + GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0), GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART2),