@@ -64,3 +64,7 @@
&usb1 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
@@ -285,6 +285,17 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
@@ -58,3 +58,7 @@
&i2c0 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
@@ -66,3 +66,7 @@
&usb3 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
@@ -305,6 +305,17 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-uniphier-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ };
};
};
@@ -368,6 +368,17 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-uniphier-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
@@ -352,6 +352,17 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
@@ -73,3 +73,7 @@
&usb3 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
@@ -256,5 +256,14 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@f8000000 {
+ compatible = "denali,denali-nand-uniphier-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+ interrupts = <0 65 4>;
+ clocks = <&sys_clk 2>;
+ };
};
};
@@ -285,6 +285,17 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-uniphier-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
Add NAND controller node to sLD3, LD4, Pro4, sLD8, Pro5, and PXs2. Set up pinctrl to enable 2 chip select lines except Pro4. The CS1 for Pro4 is multiplexed with other peripherals such as UART2, so I did not enable it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- arch/arm/boot/dts/uniphier-ld4-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-ld4.dtsi | 11 +++++++++++ arch/arm/boot/dts/uniphier-ld6b-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-pro4-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-pro4.dtsi | 11 +++++++++++ arch/arm/boot/dts/uniphier-pro5.dtsi | 11 +++++++++++ arch/arm/boot/dts/uniphier-pxs2.dtsi | 11 +++++++++++ arch/arm/boot/dts/uniphier-sld3-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-sld3.dtsi | 9 +++++++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 11 +++++++++++ 10 files changed, 80 insertions(+) -- 2.7.4