| Message ID | 20170814142418.13267-9-julien.grall@arm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen/arm: Memory subsystem clean-up | expand |
Hi, On 14/08/17 15:23, Julien Grall wrote: > Signed-off-by: Julien Grall <julien.grall@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> > --- > xen/include/asm-arm/processor.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > index ab5225fa6c..51645f08c0 100644 > --- a/xen/include/asm-arm/processor.h > +++ b/xen/include/asm-arm/processor.h > @@ -505,9 +505,9 @@ union hsr { > > struct hsr_iabt { > unsigned long ifsc:6; /* Instruction fault status code */ > - unsigned long res0:1; > + unsigned long res0:1; /* RES0 */ > unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ > - unsigned long res1:1; > + unsigned long res1:1; /* RES0 */ > unsigned long eat:1; /* External abort type */ > unsigned long res2:15; As we are at it: newer versions of the ARM ARM have the "FnV" bit here at bit 10, so would it be worth to update it as: unsigned long fnv:1; /* FAR not Valid */ unsigned long res2:14; Cheers, Andre. > unsigned long len:1; /* Instruction length */ >
On 22/08/17 15:21, Andre Przywara wrote: > Hi, Hi Andre, > > On 14/08/17 15:23, Julien Grall wrote: >> Signed-off-by: Julien Grall <julien.grall@arm.com> > > Reviewed-by: Andre Przywara <andre.przywara@arm.com> > >> --- >> xen/include/asm-arm/processor.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h >> index ab5225fa6c..51645f08c0 100644 >> --- a/xen/include/asm-arm/processor.h >> +++ b/xen/include/asm-arm/processor.h >> @@ -505,9 +505,9 @@ union hsr { >> >> struct hsr_iabt { >> unsigned long ifsc:6; /* Instruction fault status code */ >> - unsigned long res0:1; >> + unsigned long res0:1; /* RES0 */ >> unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ >> - unsigned long res1:1; >> + unsigned long res1:1; /* RES0 */ >> unsigned long eat:1; /* External abort type */ >> unsigned long res2:15; > > As we are at it: newer versions of the ARM ARM have the "FnV" bit here > at bit 10, so would it be worth to update it as: See patch 11 :). I would prefer if we keep "clean-up" out of new addition for the review. Cheers, > > unsigned long fnv:1; /* FAR not Valid */ > unsigned long res2:14;
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index ab5225fa6c..51645f08c0 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -505,9 +505,9 @@ union hsr { struct hsr_iabt { unsigned long ifsc:6; /* Instruction fault status code */ - unsigned long res0:1; + unsigned long res0:1; /* RES0 */ unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ - unsigned long res1:1; + unsigned long res1:1; /* RES0 */ unsigned long eat:1; /* External abort type */ unsigned long res2:15; unsigned long len:1; /* Instruction length */
Signed-off-by: Julien Grall <julien.grall@arm.com> --- xen/include/asm-arm/processor.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)