| Message ID | CAN8C2CqL+2LtuMMLtVL=L_MRpQrU_CRiC8dCjChkUiMZF9=+tw@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
Patch rebased to latest version of master due to a lot of changes were done by Alan here https://sourceware.org/ml/binutils/2017-08/msg00245.html in commit b80c727008fc32d5271f3966be4e2a43badf8055 Please apply if it is okay. On Wed, Aug 23, 2017 at 1:13 PM, Alexander Fedotov <alfedotov@gmail.com> wrote: > This patch adds SPE2 and EFS2 instructions support to PowerPC VLE. Based against > current master branch. > > Alex -- Best regards, AFFrom 714bca9aa2987a4cf3ce0fc7f002697983e4d253 Mon Sep 17 00:00:00 2001 From: Alexander Fedotov-B55613 <b55613@freescale.com> Date: Wed, 23 Aug 2017 18:01:37 +0300 Subject: [PATCH] [PowerPC VLE] Add SPE2 and EFS2 instructions support --- gas/ChangeLog | 24 + gas/config/tc-ppc.c | 53 ++ gas/doc/as.texinfo | 2 +- gas/doc/c-ppc.texi | 3 + gas/testsuite/gas/ppc/efs.d | 25 + gas/testsuite/gas/ppc/efs.s | 29 + gas/testsuite/gas/ppc/efs2.d | 19 + gas/testsuite/gas/ppc/efs2.s | 18 + gas/testsuite/gas/ppc/ppc.exp | 8 + gas/testsuite/gas/ppc/spe.d | 267 ++++++++ gas/testsuite/gas/ppc/spe.s | 274 ++++++++ gas/testsuite/gas/ppc/spe2-checks.d | 4 + gas/testsuite/gas/ppc/spe2-checks.l | 73 +++ gas/testsuite/gas/ppc/spe2-checks.s | 99 +++ gas/testsuite/gas/ppc/spe2.d | 815 ++++++++++++++++++++++++ gas/testsuite/gas/ppc/spe2.s | 834 +++++++++++++++++++++++++ gas/testsuite/gas/ppc/spe_ambiguous.d | 15 + gas/testsuite/gas/ppc/spe_ambiguous.s | 21 + include/ChangeLog | 10 + include/opcode/ppc.h | 14 + opcodes/ChangeLog | 60 ++ opcodes/ppc-dis.c | 83 ++- opcodes/ppc-opc.c | 1108 ++++++++++++++++++++++++++++++++- 23 files changed, 3845 insertions(+), 13 deletions(-) create mode 100644 gas/testsuite/gas/ppc/efs.d create mode 100644 gas/testsuite/gas/ppc/efs.s create mode 100644 gas/testsuite/gas/ppc/efs2.d create mode 100644 gas/testsuite/gas/ppc/efs2.s create mode 100644 gas/testsuite/gas/ppc/spe.d create mode 100644 gas/testsuite/gas/ppc/spe.s create mode 100644 gas/testsuite/gas/ppc/spe2-checks.d create mode 100644 gas/testsuite/gas/ppc/spe2-checks.l create mode 100644 gas/testsuite/gas/ppc/spe2-checks.s create mode 100644 gas/testsuite/gas/ppc/spe2.d create mode 100644 gas/testsuite/gas/ppc/spe2.s create mode 100644 gas/testsuite/gas/ppc/spe_ambiguous.d create mode 100644 gas/testsuite/gas/ppc/spe_ambiguous.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 328037e..8bea1df 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,27 @@ +2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com> + Edmar Wienskoski <edmar.wienskoski@nxp.com + + * config/tc-ppc.c: + (md_parse_option): Add mspe2 switch. + (md_show_usage): Document -mspe2. + (ppc_setup_opcodes): Handle spe2_opcodes. + * doc/as.texinfo: Document -mspe2. + * doc/c-ppc.texi: Likewise. + * testsuite/gas/ppc/efs.d: New file. + * testsuite/gas/ppc/efs.s: Likewise. + * testsuite/gas/ppc/efs2.d: Likewise. + * testsuite/gas/ppc/efs2.s: Likewise. + * testsuite/gas/ppc/ppc.exp: Run new tests. + * testsuite/gas/ppc/spe.d: New file. + * testsuite/gas/ppc/spe.s: Likewise. + * testsuite/gas/ppc/spe2-checks.d: Likewise. + * testsuite/gas/ppc/spe2-checks.l: Likewise. + * testsuite/gas/ppc/spe2-checks.s: Likewise. + * testsuite/gas/ppc/spe2.d: Likewise. + * testsuite/gas/ppc/spe2.s: Likewise. + * testsuite/gas/ppc/spe_ambiguous.d: Likewise. + * testsuite/gas/ppc/spe_ambiguous.s: Likewise. + 2017-08-23 James Clarke <jrtc27@jrtc27.com> * config/tc-sparc.c (tc_gen_reloc): Convert BFD_RELOC_8/16/32/64 diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index e8dfbc4..d20fac6 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1258,6 +1258,10 @@ md_parse_option (int c, const char *arg) msolaris = FALSE; ppc_comment_chars = ppc_eabi_comment_chars; } + else if (strcmp (arg, "spe2") == 0) + { + ppc_cpu |= PPC_OPCODE_SPE2; + } #endif else { @@ -1353,6 +1357,7 @@ PowerPC options:\n\ -me5500, generate code for Freescale e5500 core complex\n\ -me6500, generate code for Freescale e6500 core complex\n\ -mspe generate code for Motorola SPE instructions\n\ +-mspe2 generate code for Freescale SPE2 instructions\n\ -mvle generate code for Freescale VLE instructions\n\ -mtitan generate code for AppliedMicro Titan core complex\n\ -mregnames Allow symbolic names for registers\n\ @@ -1688,6 +1693,54 @@ ppc_setup_opcodes (void) } } + /* SPE2 instructions */ + if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) + { + op_end = spe2_opcodes + spe2_num_opcodes; + for (op = spe2_opcodes; op < op_end; op++) + { + if (ENABLE_CHECKING) + { + if (op != spe2_opcodes) + { + unsigned old_seg, new_seg; + + old_seg = VLE_OP (op[-1].opcode, op[-1].mask); + old_seg = VLE_OP_TO_SEG (old_seg); + new_seg = VLE_OP (op[0].opcode, op[0].mask); + new_seg = VLE_OP_TO_SEG (new_seg); + + /* The major opcodes had better be sorted. Code in the + disassembler assumes the insns are sorted according to + major opcode. */ + if (new_seg < old_seg) + { + as_bad (_("major opcode is not sorted for %s"), op->name); + bad_insn = TRUE; + } + } + + bad_insn |= insn_validate (op); + } + + if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated)) + { + const char *retval; + + retval = hash_insert (ppc_hash, op->name, (void *) op); + if (retval != NULL) + { + as_bad (_("duplicate instruction %s"), + op->name); + bad_insn = TRUE; + } + } + } + + for (op = spe2_opcodes; op < op_end; op++) + hash_insert (ppc_hash, op->name, (void *) op); + } + /* Insert the macros into a hash table. */ ppc_macro_hash = hash_new (); diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 8aa83ef..8c125fd 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -487,7 +487,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}| @b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}| @b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}| - @b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}] + @b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-me300}|@b{-mcom}] [@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}] [@b{-mregnames}|@b{-mno-regnames}] [@b{-mrelocatable}|@b{-mrelocatable-lib}|@b{-K PIC}] [@b{-memb}] diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi index d94b418..7e66625 100644 --- a/gas/doc/c-ppc.texi +++ b/gas/doc/c-ppc.texi @@ -99,6 +99,9 @@ Generate code for Freescale e6500 core complex. @item -mspe Generate code for Motorola SPE instructions. +@item -mspe2 +Generate code for Freescale SPE2 instructions. + @item -mtitan Generate code for AppliedMicro Titan core complex. diff --git a/gas/testsuite/gas/ppc/efs.d b/gas/testsuite/gas/ppc/efs.d new file mode 100644 index 0000000..8d365a4 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs.d @@ -0,0 +1,25 @@ +#as: -mvle +#objdump: -d -Mefs -Mvle -Mefs2 +#name: Validate EFS instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 00 12 d1 efscfsi r0,r2 + 4: 10 00 12 d5 efsctsi r0,r2 + 8: 10 00 12 f1 efdcfsi r0,r2 + c: 10 00 12 f5 efdctsi r0,r2 + 10: 10 01 12 c2 efsmadd r0,r1,r2 + 14: 10 01 12 c3 efsmsub r0,r1,r2 + 18: 10 01 12 ca efsnmadd r0,r1,r2 + 1c: 10 01 12 cb efsnmsub r0,r1,r2 + 20: 10 01 12 e2 efdmadd r0,r1,r2 + 24: 10 01 12 e3 efdmsub r0,r1,r2 + 28: 10 01 12 ea efdnmadd r0,r1,r2 + 2c: 10 01 12 eb efdnmsub r0,r1,r2 + 30: 10 01 12 f0 efdcfuid r0,r2 + 34: 10 01 12 f1 efdcfsid r0,r2 + 38: 10 01 12 f8 efdctuidz r0,r2 + 3c: 10 01 12 fa efdctsidz r0,r2 \ No newline at end of file diff --git a/gas/testsuite/gas/ppc/efs.s b/gas/testsuite/gas/ppc/efs.s new file mode 100644 index 0000000..7afcfd8 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs.s @@ -0,0 +1,29 @@ +# PA EFS 1.0 and 1.1 instructions +# CMPE200GCC-62 + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + +;# EFS 1.0 instructions in accordance with EFP2_rev.1.4_spec + efscfsi rD, rB + efsctsi rD, rB + efdcfsi rD, rB + efdctsi rD, rB + +;# EFS 1.1 instructions in accordance with EFP2_rev.1.4_spec + efsmadd rD, rA, rB + efsmsub rD, rA, rB + efsnmadd rD, rA, rB + efsnmsub rD, rA, rB + efdmadd rD, rA, rB + efdmsub rD, rA, rB + efdnmadd rD, rA, rB + efdnmsub rD, rA, rB + +;# moved EFS opcodes in accordance with EFP2_rev.1.4_spec + efdcfuid rD, rB + efdcfsid rD, rB + efdctuidz rD, rB + efdctsidz rD, rB diff --git a/gas/testsuite/gas/ppc/efs2.d b/gas/testsuite/gas/ppc/efs2.d new file mode 100644 index 0000000..bfdfb14 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs2.d @@ -0,0 +1,19 @@ +#as: -mvle +#objdump: -d -Mvle -Mefs2 +#name: Validate EFS2 instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 12 b0 efsmax r0,r1,r2 + 4: 10 01 12 b1 efsmin r0,r1,r2 + 8: 10 01 12 b8 efdmax r0,r1,r2 + c: 10 01 12 b9 efdmin r0,r1,r2 + 10: 10 01 02 c7 efssqrt r0,r1 + 14: 10 04 12 d1 efscfh r0,r2 + 18: 10 04 12 d5 efscth r0,r2 + 1c: 10 01 02 e7 efdsqrt r0,r1 + 20: 10 04 12 f1 efdcfh r0,r2 + 24: 10 04 12 f5 efdcth r0,r2 \ No newline at end of file diff --git a/gas/testsuite/gas/ppc/efs2.s b/gas/testsuite/gas/ppc/efs2.s new file mode 100644 index 0000000..5d35e98 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs2.s @@ -0,0 +1,18 @@ +# PA EFS2 instructions in accordance with EFP2_rev.1.4_spec +# CMPE200GCC-62 + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + + efsmax rD, rA, rB + efsmin rD, rA, rB + efdmax rD, rA, rB + efdmin rD, rA, rB + efssqrt rD, rA + efscfh rD, rB + efscth rD, rB + efdsqrt rD, rA + efdcfh rD, rB + efdcth rD, rB diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index bbe64be..cdcd8a1 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -65,6 +65,14 @@ if { [istarget powerpc*-*-*] } then { setup_xfail "*-*-*" run_dump_test "lsp" run_dump_test "lsp-checks" + run_dump_test "efs" + run_dump_test "efs2" + run_dump_test "spe2" + run_dump_test "spe2-checks" + run_dump_test "spe" + + setup_xfail "*-*-*" + run_dump_test "spe_ambiguous" } } diff --git a/gas/testsuite/gas/ppc/spe.d b/gas/testsuite/gas/ppc/spe.d new file mode 100644 index 0000000..7391028 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe.d @@ -0,0 +1,267 @@ +#as: -a32 -mvle +#objdump: -d -Mspe +#name: Validate SPE instructions + +.*: +file format elf.*-powerpc.* + + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 12 00 evaddw r0,r1,r2 + 4: 10 1f 12 02 evaddiw r0,r2,31 + 8: 10 01 12 04 evsubfw r0,r1,r2 + c: 10 01 12 04 evsubfw r0,r1,r2 + 10: 10 1f 12 06 evsubifw r0,31,r2 + 14: 10 1f 12 06 evsubifw r0,31,r2 + 18: 10 01 02 08 evabs r0,r1 + 1c: 10 01 02 09 evneg r0,r1 + 20: 10 01 02 0a evextsb r0,r1 + 24: 10 01 02 0b evextsh r0,r1 + 28: 10 01 02 0c evrndw r0,r1 + 2c: 10 01 02 0d evcntlzw r0,r1 + 30: 10 01 02 0e evcntlsw r0,r1 + 34: 10 01 12 0f brinc r0,r1,r2 + 38: 10 01 12 11 evand r0,r1,r2 + 3c: 10 01 12 12 evandc r0,r1,r2 + 40: 10 01 12 16 evxor r0,r1,r2 + 44: 10 01 0a 17 evmr r0,r1 + 48: 10 01 12 17 evor r0,r1,r2 + 4c: 10 01 12 18 evnor r0,r1,r2 + 50: 10 01 0a 18 evnor r0,r1,r1 + 54: 10 01 12 19 eveqv r0,r1,r2 + 58: 10 01 12 1b evorc r0,r1,r2 + 5c: 10 01 12 1e evnand r0,r1,r2 + 60: 10 01 12 20 evsrwu r0,r1,r2 + 64: 10 01 12 21 evsrws r0,r1,r2 + 68: 10 01 fa 22 evsrwiu r0,r1,31 + 6c: 10 01 fa 23 evsrwis r0,r1,31 + 70: 10 01 12 24 evslw r0,r1,r2 + 74: 10 01 fa 26 evslwi r0,r1,31 + 78: 10 01 12 28 evrlw r0,r1,r2 + 7c: 10 10 02 29 evsplati r0,-16 + 80: 10 01 fa 2a evrlwi r0,r1,31 + 84: 10 10 02 2b evsplatfi r0,-16 + 88: 10 01 12 2c evmergehi r0,r1,r2 + 8c: 10 01 12 2d evmergelo r0,r1,r2 + 90: 10 01 12 2e evmergehilo r0,r1,r2 + 94: 10 01 12 2f evmergelohi r0,r1,r2 + 98: 10 01 12 30 evcmpgtu cr0,r1,r2 + 9c: 10 01 12 31 evcmpgts cr0,r1,r2 + a0: 10 01 12 32 evcmpltu cr0,r1,r2 + a4: 10 01 12 33 evcmplts cr0,r1,r2 + a8: 10 01 12 34 evcmpeq cr0,r1,r2 + ac: 10 01 12 78 evsel r0,r1,r2,cr0 + b0: 10 01 12 80 evfsadd r0,r1,r2 + b4: 10 01 12 81 evfssub r0,r1,r2 + b8: 10 01 12 82 evfsmadd r0,r1,r2 + bc: 10 01 12 83 evfsmsub r0,r1,r2 + c0: 10 01 02 84 evfsabs r0,r1 + c4: 10 01 02 85 evfsnabs r0,r1 + c8: 10 01 02 86 evfsneg r0,r1 + cc: 10 01 12 88 evfsmul r0,r1,r2 + d0: 10 01 12 89 evfsdiv r0,r1,r2 + d4: 10 01 12 8a evfsnmadd r0,r1,r2 + d8: 10 01 12 8b evfsnmsub r0,r1,r2 + dc: 10 01 12 8c evfscmpgt cr0,r1,r2 + e0: 10 01 12 8d evfscmplt cr0,r1,r2 + e4: 10 01 12 8e evfscmpeq cr0,r1,r2 + e8: 10 00 12 90 evfscfui r0,r2 + ec: 10 00 12 91 evfscfsi r0,r2 + f0: 10 00 12 92 evfscfuf r0,r2 + f4: 10 00 12 93 evfscfsf r0,r2 + f8: 10 00 12 94 evfsctui r0,r2 + fc: 10 00 12 95 evfsctsi r0,r2 + 100: 10 00 12 96 evfsctuf r0,r2 + 104: 10 00 12 97 evfsctsf r0,r2 + 108: 10 00 12 98 evfsctuiz r0,r2 + 10c: 10 00 12 9a evfsctsiz r0,r2 + 110: 10 01 12 9c evfststgt cr0,r1,r2 + 114: 10 01 12 9d evfststlt cr0,r1,r2 + 118: 10 01 12 9e evfststeq cr0,r1,r2 + 11c: 10 01 13 00 evlddx r0,r1,r2 + 120: 10 01 0b 01 evldd r0,8\(r1\) + 124: 10 01 13 02 evldwx r0,r1,r2 + 128: 10 01 0b 03 evldw r0,8\(r1\) + 12c: 10 01 13 04 evldhx r0,r1,r2 + 130: 10 01 0b 05 evldh r0,8\(r1\) + 134: 10 01 13 08 evlhhesplatx r0,r1,r2 + 138: 10 01 0b 09 evlhhesplat r0,2\(r1\) + 13c: 10 01 13 0c evlhhousplatx r0,r1,r2 + 140: 10 01 0b 0d evlhhousplat r0,2\(r1\) + 144: 10 01 13 0e evlhhossplatx r0,r1,r2 + 148: 10 01 0b 0f evlhhossplat r0,2\(r1\) + 14c: 10 01 13 10 evlwhex r0,r1,r2 + 150: 10 01 0b 11 evlwhe r0,4\(r1\) + 154: 10 01 13 14 evlwhoux r0,r1,r2 + 158: 10 01 0b 15 evlwhou r0,4\(r1\) + 15c: 10 01 13 16 evlwhosx r0,r1,r2 + 160: 10 01 0b 17 evlwhos r0,4\(r1\) + 164: 10 01 13 18 evlwwsplatx r0,r1,r2 + 168: 10 01 0b 19 evlwwsplat r0,4\(r1\) + 16c: 10 01 13 1c evlwhsplatx r0,r1,r2 + 170: 10 01 0b 1d evlwhsplat r0,4\(r1\) + 174: 10 01 13 20 evstddx r0,r1,r2 + 178: 10 01 0b 21 evstdd r0,8\(r1\) + 17c: 10 01 13 22 evstdwx r0,r1,r2 + 180: 10 01 0b 23 evstdw r0,8\(r1\) + 184: 10 01 13 24 evstdhx r0,r1,r2 + 188: 10 01 0b 25 evstdh r0,8\(r1\) + 18c: 10 01 13 30 evstwhex r0,r1,r2 + 190: 10 01 0b 31 evstwhe r0,4\(r1\) + 194: 10 01 13 34 evstwhox r0,r1,r2 + 198: 10 01 0b 35 evstwho r0,4\(r1\) + 19c: 10 01 13 38 evstwwex r0,r1,r2 + 1a0: 10 01 0b 39 evstwwe r0,4\(r1\) + 1a4: 10 01 13 3c evstwwox r0,r1,r2 + 1a8: 10 01 0b 3d evstwwo r0,4\(r1\) + 1ac: 10 01 14 03 evmhessf r0,r1,r2 + 1b0: 10 01 14 07 evmhossf r0,r1,r2 + 1b4: 10 01 14 08 evmheumi r0,r1,r2 + 1b8: 10 01 14 09 evmhesmi r0,r1,r2 + 1bc: 10 01 14 0b evmhesmf r0,r1,r2 + 1c0: 10 01 14 0c evmhoumi r0,r1,r2 + 1c4: 10 01 14 0d evmhosmi r0,r1,r2 + 1c8: 10 01 14 0f evmhosmf r0,r1,r2 + 1cc: 10 01 14 23 evmhessfa r0,r1,r2 + 1d0: 10 01 14 27 evmhossfa r0,r1,r2 + 1d4: 10 01 14 28 evmheumia r0,r1,r2 + 1d8: 10 01 14 29 evmhesmia r0,r1,r2 + 1dc: 10 01 14 2b evmhesmfa r0,r1,r2 + 1e0: 10 01 14 2c evmhoumia r0,r1,r2 + 1e4: 10 01 14 2d evmhosmia r0,r1,r2 + 1e8: 10 01 14 2f evmhosmfa r0,r1,r2 + 1ec: 10 01 14 43 evmwlssf r0,r1,r2 + 1f0: 10 01 14 47 evmwhssf r0,r1,r2 + 1f4: 10 01 14 48 evmwlumi r0,r1,r2 + 1f8: 10 01 14 4b evmwlsmf r0,r1,r2 + 1fc: 10 01 14 4c evmwhumi r0,r1,r2 + 200: 10 01 14 4d evmwhsmi r0,r1,r2 + 204: 10 01 14 4f evmwhsmf r0,r1,r2 + 208: 10 01 14 53 evmwssf r0,r1,r2 + 20c: 10 01 14 58 evmwumi r0,r1,r2 + 210: 10 01 14 59 evmwsmi r0,r1,r2 + 214: 10 01 14 5b evmwsmf r0,r1,r2 + 218: 10 01 14 63 evmwlssfa r0,r1,r2 + 21c: 10 01 14 67 evmwhssfa r0,r1,r2 + 220: 10 01 14 68 evmwlumia r0,r1,r2 + 224: 10 01 14 6b evmwlsmfa r0,r1,r2 + 228: 10 01 14 6c evmwhumia r0,r1,r2 + 22c: 10 01 14 6d evmwhsmia r0,r1,r2 + 230: 10 01 14 6f evmwhsmfa r0,r1,r2 + 234: 10 01 14 73 evmwssfa r0,r1,r2 + 238: 10 01 14 78 evmwumia r0,r1,r2 + 23c: 10 01 14 79 evmwsmia r0,r1,r2 + 240: 10 01 14 7b evmwsmfa r0,r1,r2 + 244: 10 01 04 c0 evaddusiaaw r0,r1 + 248: 10 01 04 c1 evaddssiaaw r0,r1 + 24c: 10 01 04 c2 evsubfusiaaw r0,r1 + 250: 10 01 04 c3 evsubfssiaaw r0,r1 + 254: 10 01 04 c4 evmra r0,r1 + 258: 10 01 14 c6 evdivws r0,r1,r2 + 25c: 10 01 14 c7 evdivwu r0,r1,r2 + 260: 10 01 04 c8 evaddumiaaw r0,r1 + 264: 10 01 04 c9 evaddsmiaaw r0,r1 + 268: 10 01 04 ca evsubfumiaaw r0,r1 + 26c: 10 01 04 cb evsubfsmiaaw r0,r1 + 270: 10 01 15 00 evmheusiaaw r0,r1,r2 + 274: 10 01 15 01 evmhessiaaw r0,r1,r2 + 278: 10 01 15 03 evmhessfaaw r0,r1,r2 + 27c: 10 01 15 04 evmhousiaaw r0,r1,r2 + 280: 10 01 15 05 evmhossiaaw r0,r1,r2 + 284: 10 01 15 07 evmhossfaaw r0,r1,r2 + 288: 10 01 15 08 evmheumiaaw r0,r1,r2 + 28c: 10 01 15 09 evmhesmiaaw r0,r1,r2 + 290: 10 01 15 0b evmhesmfaaw r0,r1,r2 + 294: 10 01 15 0c evmhoumiaaw r0,r1,r2 + 298: 10 01 15 0d evmhosmiaaw r0,r1,r2 + 29c: 10 01 15 0f evmhosmfaaw r0,r1,r2 + 2a0: 10 01 15 28 evmhegumiaa r0,r1,r2 + 2a4: 10 01 15 29 evmhegsmiaa r0,r1,r2 + 2a8: 10 01 15 2b evmhegsmfaa r0,r1,r2 + 2ac: 10 01 15 2c evmhogumiaa r0,r1,r2 + 2b0: 10 01 15 2d evmhogsmiaa r0,r1,r2 + 2b4: 10 01 15 2f evmhogsmfaa r0,r1,r2 + 2b8: 10 01 15 40 evmwlusiaaw r0,r1,r2 + 2bc: 10 01 15 41 evmwlssiaaw r0,r1,r2 + 2c0: 10 01 15 43 evmwlssfaaw r0,r1,r2 + 2c4: 10 01 15 44 evmwhusiaa r0,r1,r2 + 2c8: 10 01 15 45 evmwhssmaa r0,r1,r2 + 2cc: 10 01 15 47 evmwhssfaa r0,r1,r2 + 2d0: 10 01 15 48 evmwlumiaaw r0,r1,r2 + 2d4: 10 01 15 49 evmwlsmiaaw r0,r1,r2 + 2d8: 10 01 15 4b evmwlsmfaaw r0,r1,r2 + 2dc: 10 01 15 4c evmwhumiaa r0,r1,r2 + 2e0: 10 01 15 4d evmwhsmiaa r0,r1,r2 + 2e4: 10 01 15 4f evmwhsmfaa r0,r1,r2 + 2e8: 10 01 15 53 evmwssfaa r0,r1,r2 + 2ec: 10 01 15 58 evmwumiaa r0,r1,r2 + 2f0: 10 01 15 59 evmwsmiaa r0,r1,r2 + 2f4: 10 01 15 5b evmwsmfaa r0,r1,r2 + 2f8: 10 01 15 64 evmwhgumiaa r0,r1,r2 + 2fc: 10 01 15 65 evmwhgsmiaa r0,r1,r2 + 300: 10 01 15 67 evmwhgssfaa r0,r1,r2 + 304: 10 01 15 6f evmwhgsmfaa r0,r1,r2 + 308: 10 01 15 80 evmheusianw r0,r1,r2 + 30c: 10 01 15 81 evmhessianw r0,r1,r2 + 310: 10 01 15 83 evmhessfanw r0,r1,r2 + 314: 10 01 15 84 evmhousianw r0,r1,r2 + 318: 10 01 15 85 evmhossianw r0,r1,r2 + 31c: 10 01 15 87 evmhossfanw r0,r1,r2 + 320: 10 01 15 88 evmheumianw r0,r1,r2 + 324: 10 01 15 89 evmhesmianw r0,r1,r2 + 328: 10 01 15 8b evmhesmfanw r0,r1,r2 + 32c: 10 01 15 8c evmhoumianw r0,r1,r2 + 330: 10 01 15 8d evmhosmianw r0,r1,r2 + 334: 10 01 15 8f evmhosmfanw r0,r1,r2 + 338: 10 01 15 a8 evmhegumian r0,r1,r2 + 33c: 10 01 15 a9 evmhegsmian r0,r1,r2 + 340: 10 01 15 ab evmhegsmfan r0,r1,r2 + 344: 10 01 15 ac evmhogumian r0,r1,r2 + 348: 10 01 15 ad evmhogsmian r0,r1,r2 + 34c: 10 01 15 af evmhogsmfan r0,r1,r2 + 350: 10 01 15 c0 evmwlusianw r0,r1,r2 + 354: 10 01 15 c1 evmwlssianw r0,r1,r2 + 358: 10 01 15 c3 evmwlssfanw r0,r1,r2 + 35c: 10 01 15 c4 evmwhusian r0,r1,r2 + 360: 10 01 15 c5 evmwhssian r0,r1,r2 + 364: 10 01 15 c7 evmwhssfan r0,r1,r2 + 368: 10 01 15 c8 evmwlumianw r0,r1,r2 + 36c: 10 01 15 c9 evmwlsmianw r0,r1,r2 + 370: 10 01 15 cb evmwlsmfanw r0,r1,r2 + 374: 10 01 15 cc evmwhumian r0,r1,r2 + 378: 10 01 15 cd evmwhsmian r0,r1,r2 + 37c: 10 01 15 cf evmwhsmfan r0,r1,r2 + 380: 10 01 15 d3 evmwssfan r0,r1,r2 + 384: 10 01 15 d8 evmwumian r0,r1,r2 + 388: 10 01 15 d9 evmwsmian r0,r1,r2 + 38c: 10 01 15 db evmwsmfan r0,r1,r2 + 390: 10 01 15 e4 evmwhgumian r0,r1,r2 + 394: 10 01 15 e5 evmwhgsmian r0,r1,r2 + 398: 10 01 15 e7 evmwhgssfan r0,r1,r2 + 39c: 10 01 15 ef evmwhgsmfan r0,r1,r2 + 3a0: 7c 01 16 3e evlddepx r0,r1,r2 + 3a4: 7c 01 17 3e evstddepx r0,r1,r2 + 3a8: 10 01 12 c0 efsadd r0,r1,r2 + 3ac: 10 01 12 c1 efssub r0,r1,r2 + 3b0: 10 01 02 c4 efsabs r0,r1 + 3b4: 10 01 02 c5 efsnabs r0,r1 + 3b8: 10 01 02 c6 efsneg r0,r1 + 3bc: 10 01 12 c8 efsmul r0,r1,r2 + 3c0: 10 01 12 c9 efsdiv r0,r1,r2 + 3c4: 10 01 12 cc efscmpgt cr0,r1,r2 + 3c8: 10 01 12 cd efscmplt cr0,r1,r2 + 3cc: 10 01 12 ce efscmpeq cr0,r1,r2 + 3d0: 10 00 12 d0 efscfui r0,r2 + 3d4: 10 00 12 d1 efscfsi r0,r2 + 3d8: 10 00 12 d2 efscfuf r0,r2 + 3dc: 10 00 12 d3 efscfsf r0,r2 + 3e0: 10 00 12 d4 efsctui r0,r2 + 3e4: 10 00 12 d5 efsctsi r0,r2 + 3e8: 10 00 12 d6 efsctuf r0,r2 + 3ec: 10 00 12 d7 efsctsf r0,r2 + 3f0: 10 00 12 d8 efsctuiz r0,r2 + 3f4: 10 00 12 da efsctsiz r0,r2 + 3f8: 10 01 12 dc efststgt cr0,r1,r2 + 3fc: 10 01 12 dd efststlt cr0,r1,r2 + 400: 10 01 12 de efststeq cr0,r1,r2 diff --git a/gas/testsuite/gas/ppc/spe.s b/gas/testsuite/gas/ppc/spe.s new file mode 100644 index 0000000..5be3386 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe.s @@ -0,0 +1,274 @@ +# PA SPE instructions + .section ".text" + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ rT,0 + .equ UIMM, 31 + .equ UIMM_2, 2 + .equ UIMM_4, 4 + .equ UIMM_8, 8 + .equ SIMM, -16 + .equ crD, 0 + .equ crS, 0 + + evaddw rS, rA, rB + evaddiw rS, rB, UIMM + evsubfw rS, rA, rB + evsubw rS, rB, rA + evsubifw rS, UIMM, rB + evsubiw rS, rB, UIMM + evabs rS, rA + evneg rS, rA + evextsb rS, rA + evextsh rS, rA + evrndw rS, rA + evcntlzw rS, rA + evcntlsw rS, rA + brinc rS, rA, rB + evand rS, rA, rB + evandc rS, rA, rB + evxor rS, rA, rB + evmr rS, rA + evor rS, rA, rB + evnor rS, rA, rB + evnot rS, rA + eveqv rS, rA, rB + evorc rS, rA, rB + evnand rS, rA, rB + evsrwu rS, rA, rB + evsrws rS, rA, rB + evsrwiu rS, rA, UIMM + evsrwis rS, rA, UIMM + evslw rS, rA, rB + evslwi rS, rA, UIMM + evrlw rS, rA, rB + evsplati rS, SIMM + evrlwi rS, rA, UIMM + evsplatfi rS, SIMM + evmergehi rS, rA, rB + evmergelo rS, rA, rB + evmergehilo rS, rA, rB + evmergelohi rS, rA, rB + evcmpgtu crD, rA, rB + evcmpgts crD, rA, rB + evcmpltu crD, rA, rB + evcmplts crD, rA, rB + evcmpeq crD, rA, rB + evsel rS, rA, rB, crS + evfsadd rS, rA, rB + evfssub rS, rA, rB + evfsmadd rS, rA, rB + evfsmsub rS, rA, rB + evfsabs rS, rA + evfsnabs rS, rA + evfsneg rS, rA + evfsmul rS, rA, rB + evfsdiv rS, rA, rB + evfsnmadd rS, rA, rB + evfsnmsub rS, rA, rB + evfscmpgt crD, rA, rB + evfscmplt crD, rA, rB + evfscmpeq crD, rA, rB + evfscfui rS, rB + evfscfsi rS, rB + evfscfuf rS, rB + evfscfsf rS, rB + evfsctui rS, rB + evfsctsi rS, rB + evfsctuf rS, rB + evfsctsf rS, rB + evfsctuiz rS, rB + evfsctsiz rS, rB + evfststgt crD, rA, rB + evfststlt crD, rA, rB + evfststeq crD, rA, rB + evlddx rS, rA, rB + evldd rS, UIMM_8(rA) + evldwx rS, rA, rB + evldw rS, UIMM_8(rA) + evldhx rS, rA, rB + evldh rS, UIMM_8(rA) + evlhhesplatx rS, rA, rB + evlhhesplat rS, UIMM_2(rA) + evlhhousplatx rS, rA, rB + evlhhousplat rS, UIMM_2(rA) + evlhhossplatx rS, rA, rB + evlhhossplat rS, UIMM_2(rA) + evlwhex rS, rA, rB + evlwhe rS, UIMM_4(rA) + evlwhoux rS, rA, rB + evlwhou rS, UIMM_4(rA) + evlwhosx rS, rA, rB + evlwhos rS, UIMM_4(rA) + evlwwsplatx rS, rA, rB + evlwwsplat rS, UIMM_4(rA) + evlwhsplatx rS, rA, rB + evlwhsplat rS, UIMM_4(rA) + evstddx rS, rA, rB + evstdd rS, UIMM_8(rA) + evstdwx rS, rA, rB + evstdw rS, UIMM_8(rA) + evstdhx rS, rA, rB + evstdh rS, UIMM_8(rA) + evstwhex rS, rA, rB + evstwhe rS, UIMM_4(rA) + evstwhox rS, rA, rB + evstwho rS, UIMM_4(rA) + evstwwex rS, rA, rB + evstwwe rS, UIMM_4(rA) + evstwwox rS, rA, rB + evstwwo rS, UIMM_4(rA) + evmhessf rS, rA, rB + evmhossf rS, rA, rB + evmheumi rS, rA, rB + evmhesmi rS, rA, rB + evmhesmf rS, rA, rB + evmhoumi rS, rA, rB + evmhosmi rS, rA, rB + evmhosmf rS, rA, rB + evmhessfa rS, rA, rB + evmhossfa rS, rA, rB + evmheumia rS, rA, rB + evmhesmia rS, rA, rB + evmhesmfa rS, rA, rB + evmhoumia rS, rA, rB + evmhosmia rS, rA, rB + evmhosmfa rS, rA, rB + evmwlssf rD, rA, rB + evmwhssf rS, rA, rB + evmwlumi rS, rA, rB + evmwlsmf rD, rA, rB + evmwhumi rS, rA, rB + evmwhsmi rS, rA, rB + evmwhsmf rS, rA, rB + evmwssf rS, rA, rB + evmwumi rS, rA, rB + evmwsmi rS, rA, rB + evmwsmf rS, rA, rB + evmwlssfa rD, rA, rB + evmwhssfa rS, rA, rB + evmwlumia rS, rA, rB + evmwlsmfa rD, rA, rB + evmwhumia rS, rA, rB + evmwhsmia rS, rA, rB + evmwhsmfa rS, rA, rB + evmwssfa rS, rA, rB + evmwumia rS, rA, rB + evmwsmia rS, rA, rB + evmwsmfa rS, rA, rB + evaddusiaaw rS, rA + evaddssiaaw rS, rA + evsubfusiaaw rS, rA + evsubfssiaaw rS, rA + evmra rS, rA + evdivws rS, rA, rB + evdivwu rS, rA, rB + evaddumiaaw rS, rA + evaddsmiaaw rS, rA + evsubfumiaaw rS, rA + evsubfsmiaaw rS, rA + evmheusiaaw rS, rA, rB + evmhessiaaw rS, rA, rB + evmhessfaaw rS, rA, rB + evmhousiaaw rS, rA, rB + evmhossiaaw rS, rA, rB + evmhossfaaw rS, rA, rB + evmheumiaaw rS, rA, rB + evmhesmiaaw rS, rA, rB + evmhesmfaaw rS, rA, rB + evmhoumiaaw rS, rA, rB + evmhosmiaaw rS, rA, rB + evmhosmfaaw rS, rA, rB + evmhegumiaa rS, rA, rB + evmhegsmiaa rS, rA, rB + evmhegsmfaa rS, rA, rB + evmhogumiaa rS, rA, rB + evmhogsmiaa rS, rA, rB + evmhogsmfaa rS, rA, rB + evmwlusiaaw rS, rA, rB + evmwlssiaaw rS, rA, rB + evmwlssfaaw rD, rA, rB + evmwhusiaa rD, rA, rB + evmwhssmaa rD, rA, rB + evmwhssfaa rD, rA, rB + evmwlumiaaw rS, rA, rB + evmwlsmiaaw rS, rA, rB + evmwlsmfaaw rD, rA, rB + evmwhumiaa rD, rA, rB + evmwhsmiaa rD, rA, rB + evmwhsmfaa rD, rA, rB + evmwssfaa rS, rA, rB + evmwumiaa rS, rA, rB + evmwsmiaa rS, rA, rB + evmwsmfaa rS, rA, rB + evmwhgumiaa rD, rA, rB + evmwhgsmiaa rD, rA, rB + evmwhgssfaa rD, rA, rB + evmwhgsmfaa rD, rA, rB + evmheusianw rS, rA, rB + evmhessianw rS, rA, rB + evmhessfanw rS, rA, rB + evmhousianw rS, rA, rB + evmhossianw rS, rA, rB + evmhossfanw rS, rA, rB + evmheumianw rS, rA, rB + evmhesmianw rS, rA, rB + evmhesmfanw rS, rA, rB + evmhoumianw rS, rA, rB + evmhosmianw rS, rA, rB + evmhosmfanw rS, rA, rB + evmhegumian rS, rA, rB + evmhegsmian rS, rA, rB + evmhegsmfan rS, rA, rB + evmhogumian rS, rA, rB + evmhogsmian rS, rA, rB + evmhogsmfan rS, rA, rB + evmwlusianw rS, rA, rB + evmwlssianw rS, rA, rB + evmwlssfanw rD, rA, rB + evmwhusian rD, rA, rB + evmwhssian rD, rA, rB + evmwhssfan rD, rA, rB + evmwlumianw rS, rA, rB + evmwlsmianw rS, rA, rB + evmwlsmfanw rD, rA, rB + evmwhumian rD, rA, rB + evmwhsmian rD, rA, rB + evmwhsmfan rD, rA, rB + evmwssfan rS, rA, rB + evmwumian rS, rA, rB + evmwsmian rS, rA, rB + evmwsmfan rS, rA, rB + evmwhgumian rD, rA, rB + evmwhgsmian rD, rA, rB + evmwhgssfan rD, rA, rB + evmwhgsmfan rD, rA, rB + evlddepx rT, rA, rB + evstddepx rT, rA, rB + +;#SPE mapped by macro + evsadd rS, rA, rB + evssub rS, rA, rB + evsabs rS, rA + evsnabs rS, rA + evsneg rS, rA + evsmul rS, rA, rB + evsdiv rS, rA, rB + evscmpgt crD, rA, rB + evsgmplt crD, rA, rB + evsgmpeq crD, rA, rB + evscfui rS, rB + evscfsi rS, rB + evscfuf rS, rB + evscfsf rS, rB + evsctui rS, rB + evsctsi rS, rB + evsctuf rS, rB + evsctsf rS, rB + evsctuiz rS, rB + evsctsiz rS, rB + evststgt crD, rA, rB + evststlt crD, rA, rB + evststeq crD, rA, rB diff --git a/gas/testsuite/gas/ppc/spe2-checks.d b/gas/testsuite/gas/ppc/spe2-checks.d new file mode 100644 index 0000000..6af4102 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2-checks.d @@ -0,0 +1,4 @@ +#as: -a32 -mvle -mspe2 +#name: Test SPE2 operands checks +#error-output: spe2-checks.l + diff --git a/gas/testsuite/gas/ppc/spe2-checks.l b/gas/testsuite/gas/ppc/spe2-checks.l new file mode 100644 index 0000000..276c650 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2-checks.l @@ -0,0 +1,73 @@ +[^:]*: Assembler messages: +.*:29: Error: operand out of range \(32 is not between 0 and 31\) +.*:30: Error: operand out of range \(32 is not between 0 and 31\) +.*:31: Error: operand out of range \(32 is not between 0 and 31\) +.*:32: Error: operand out of range \(32 is not between 0 and 31\) +.*:33: Error: operand out of range \(8 is not between 0 and 7\) +.*:34: Error: operand out of range \(8 is not between 0 and 7\) +.*:35: Error: operand out of range \(4 is not between 0 and 3\) +.*:36: Error: operand out of range \(8 is not between 0 and 7\) +.*:37: Error: operand out of range \(4 is not between 0 and 3\) +.*:38: Error: operand out of range \(16 is not between 0 and 15\) +.*:39: Error: operand out of range \(16 is not between 0 and 15\) +.*:40: Error: operand out of range \(16 is not between 0 and 15\) +.*:41: Error: operand out of range \(4 is not between 0 and 3\) +.*:42: Error: operand out of range \(4 is not between 0 and 3\) +.*:43: Error: invalid offset +.*:44: Error: operand out of range \(8 is not between 0 and 7\) +.*:44: Error: invalid offset +.*:45: Error: UIMM values >7 are illegal +.*:46: Error: UIMM values >7 are illegal +.*:47: Error: UIMM values >7 are illegal +.*:48: Error: UIMM values >7 are illegal +.*:49: Error: UIMM values >15 are illegal +.*:50: Error: UIMM values >15 are illegal +.*:51: Error: UIMM values >15 are illegal +.*:52: Error: UIMM values >15 are illegal +.*:53: Error: operand out of range \(8 is not between 0 and 7\) +.*:54: Error: operand out of range \(8 is not between 0 and 7\) +.*:55: Error: operand out of range \(8 is not between 0 and 7\) +.*:56: Error: operand out of domain \(7 is not a multiple of 8\) +.*:57: Error: operand out of domain \(1 is not a multiple of 2\) +.*:58: Error: operand out of domain \(3 is not a multiple of 4\) +.*:59: Error: operand out of domain \(3 is not a multiple of 4\) +.*:60: Error: operand out of range \(32 is not between 0 and 31\) +.*:61: Error: operand out of domain \(7 is not a multiple of 8\) +.*:62: Error: operand out of domain \(3 is not a multiple of 4\) +.*:63: Error: operand out of domain \(3 is not a multiple of 4\) +.*:64: Error: operand out of domain \(3 is not a multiple of 4\) +.*:65: Error: operand out of domain \(3 is not a multiple of 4\) +.*:66: Error: operand out of domain \(3 is not a multiple of 4\) +.*:67: Error: operand out of domain \(3 is not a multiple of 4\) +.*:68: Error: operand out of domain \(1 is not a multiple of 2\) +.*:69: Error: operand out of domain \(7 is not a multiple of 8\) +.*:70: Error: operand out of domain \(7 is not a multiple of 8\) +.*:71: Error: operand out of domain \(7 is not a multiple of 8\) +.*:72: Error: operand out of domain \(7 is not a multiple of 8\) +.*:73: Error: operand out of domain \(1 is not a multiple of 2\) +.*:74: Error: operand out of domain \(1 is not a multiple of 2\) +.*:75: Error: operand out of domain \(1 is not a multiple of 2\) +.*:76: Error: operand out of domain \(1 is not a multiple of 2\) +.*:77: Error: operand out of domain \(3 is not a multiple of 4\) +.*:78: Error: operand out of domain \(3 is not a multiple of 4\) +.*:79: Error: operand out of domain \(3 is not a multiple of 4\) +.*:80: Error: operand out of domain \(3 is not a multiple of 4\) +.*:81: Error: operand out of domain \(3 is not a multiple of 4\) +.*:82: Error: operand out of domain \(3 is not a multiple of 4\) +.*:83: Error: operand out of domain \(3 is not a multiple of 4\) +.*:84: Error: UIMM = 00000 is illegal +.*:85: Error: operand out of domain \(7 is not a multiple of 8\) +.*:86: Error: operand out of domain \(7 is not a multiple of 8\) +.*:87: Error: operand out of domain \(7 is not a multiple of 8\) +.*:88: Error: operand out of domain \(7 is not a multiple of 8\) +.*:89: Error: operand out of domain \(3 is not a multiple of 4\) +.*:90: Error: operand out of domain \(3 is not a multiple of 4\) +.*:91: Error: operand out of domain \(3 is not a multiple of 4\) +.*:92: Error: operand out of domain \(3 is not a multiple of 4\) +.*:93: Error: operand out of domain \(3 is not a multiple of 4\) +.*:94: Error: operand out of domain \(3 is not a multiple of 4\) +.*:95: Error: operand out of domain \(3 is not a multiple of 4\) +.*:96: Error: operand out of domain \(3 is not a multiple of 4\) +.*:97: Error: operand out of domain \(3 is not a multiple of 4\) +.*:98: Error: operand out of domain \(3 is not a multiple of 4\) +.*:99: Error: operand out of domain \(1 is not a multiple of 2\) \ No newline at end of file diff --git a/gas/testsuite/gas/ppc/spe2-checks.s b/gas/testsuite/gas/ppc/spe2-checks.s new file mode 100644 index 0000000..b1fd776 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2-checks.s @@ -0,0 +1,99 @@ +# PA SPE2 instructions + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ UIMM_ILL, 32 + .equ UIMM_1_ZERO, 0 + .equ UIMM_1_ILL, 32 + .equ UIMM_2_ILL, 1 + .equ UIMM_4_ILL, 3 + .equ UIMM_8_ILL, 7 + .equ UIMM_GT7, 8 + .equ UIMM_GT15, 16 + .equ nnn_ILL, 8 + .equ bbb_ILL, 8 + .equ dd, 3 + .equ dd_ILL, 4 + .equ Ddd, 7 + .equ Ddd_ILL, 8 + .equ hh, 3 + .equ hh_ILL, 4 + .equ mask_ILL, 16 + .equ offset_ILL0, 0 + .equ offset_ILL, 8 + + + evaddib rD, rB, UIMM_ILL + evaddih rD, rB, UIMM_ILL + evsubifh rD, UIMM_ILL, rB + evsubifb rD, UIMM_ILL, rB + evinsb rD, rA, Ddd, bbb_ILL + evxtrb rD, rA, Ddd, bbb_ILL + evsplath rD, rA, hh_ILL + evsplatb rD, rA, bbb_ILL + evinsh rD, rA, dd_ILL, hh + evclrbe rD, rA, mask_ILL + evclrbo rD, rA, mask_ILL + evclrh rD, rA, mask_ILL + evxtrh rD, rA, dd_ILL, hh + evxtrh rD, rA, dd, hh_ILL + evxtrd rD, rA, rB, offset_ILL0 + evxtrd rD, rA, rB, offset_ILL + evsrbiu rD, rA, UIMM_GT7 + evsrbis rD, rA, UIMM_GT7 + evslbi rD, rA, UIMM_GT7 + evrlbi rD, rA, UIMM_GT7 + evsrhiu rD, rA, UIMM_GT15 + evsrhis rD, rA, UIMM_GT15 + evslhi rD, rA, UIMM_GT15 + evrlhi rD, rA, UIMM_GT15 + evsroiu rD, rA, nnn_ILL + evsrois rD, rA, nnn_ILL + evsloi rD, rA, nnn_ILL + evldb rD, UIMM_8_ILL (rA) + evlhhsplath rD, UIMM_2_ILL (rA) + evlwbsplatw rD, UIMM_4_ILL (rA) + evlwhsplatw rD, UIMM_4_ILL (rA) + evlbbsplatb rD, UIMM_1_ILL (rA) + evstdb rS, UIMM_8_ILL (rA) + evlwbe rD, UIMM_4_ILL (rA) + evlwbou rD, UIMM_4_ILL (rA) + evlwbos rD, UIMM_4_ILL (rA) + evstwbe rS, UIMM_4_ILL (rA) + evstwbo rS, UIMM_4_ILL (rA) + evstwb rS, UIMM_4_ILL (rA) + evsthb rS, UIMM_2_ILL (rA) + evlddu rD, UIMM_8_ILL (rA) + evldwu rD, UIMM_8_ILL (rA) + evldhu rD, UIMM_8_ILL (rA) + evldbu rD, UIMM_8_ILL (rA) + evlhhesplatu rD, UIMM_2_ILL (rA) + evlhhsplathu rD, UIMM_2_ILL (rA) + evlhhousplatu rD, UIMM_2_ILL (rA) + evlhhossplatu rD, UIMM_2_ILL (rA) + evlwheu rD, UIMM_4_ILL (rA) + evlwbsplatwu rD, UIMM_4_ILL (rA) + evlwhouu rD, UIMM_4_ILL (rA) + evlwhosu rD, UIMM_4_ILL (rA) + evlwwsplatu rD, UIMM_4_ILL (rA) + evlwhsplatwu rD, UIMM_4_ILL (rA) + evlwhsplatu rD, UIMM_4_ILL (rA) + evlbbsplatbu rD, UIMM_1_ZERO (rA) + evstddu rS, UIMM_8_ILL (rA) + evstdwu rS, UIMM_8_ILL (rA) + evstdhu rS, UIMM_8_ILL (rA) + evstdbu rS, UIMM_8_ILL (rA) + evlwbeu rD, UIMM_4_ILL (rA) + evlwbouu rD, UIMM_4_ILL (rA) + evlwbosu rD, UIMM_4_ILL (rA) + evstwheu rS, UIMM_4_ILL (rA) + evstwbeu rS, UIMM_4_ILL (rA) + evstwhou rS, UIMM_4_ILL (rA) + evstwbou rS, UIMM_4_ILL (rA) + evstwweu rS, UIMM_4_ILL (rA) + evstwbu rS, UIMM_4_ILL (rA) + evstwwou rS, UIMM_4_ILL (rA) + evsthbu rS, UIMM_2_ILL (rA) diff --git a/gas/testsuite/gas/ppc/spe2.d b/gas/testsuite/gas/ppc/spe2.d new file mode 100644 index 0000000..e4c45de --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2.d @@ -0,0 +1,815 @@ +#as: -a32 -mvle -mspe2 +#objdump: -d -Mspe2 -Mefs2 +#name: Validate SPE2 instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 10 80 evdotpwcssi r0,r1,r2 + 4: 10 01 10 81 evdotpwcsmi r0,r1,r2 + 8: 10 01 10 82 evdotpwcssfr r0,r1,r2 + c: 10 01 10 83 evdotpwcssf r0,r1,r2 + 10: 10 01 10 88 evdotpwgasmf r0,r1,r2 + 14: 10 01 10 89 evdotpwxgasmf r0,r1,r2 + 18: 10 01 10 8a evdotpwgasmfr r0,r1,r2 + 1c: 10 01 10 8b evdotpwxgasmfr r0,r1,r2 + 20: 10 01 10 8c evdotpwgssmf r0,r1,r2 + 24: 10 01 10 8d evdotpwxgssmf r0,r1,r2 + 28: 10 01 10 8e evdotpwgssmfr r0,r1,r2 + 2c: 10 01 10 8f evdotpwxgssmfr r0,r1,r2 + 30: 10 01 10 90 evdotpwcssiaaw3 r0,r1,r2 + 34: 10 01 10 91 evdotpwcsmiaaw3 r0,r1,r2 + 38: 10 01 10 92 evdotpwcssfraaw3 r0,r1,r2 + 3c: 10 01 10 93 evdotpwcssfaaw3 r0,r1,r2 + 40: 10 01 10 98 evdotpwgasmfaa3 r0,r1,r2 + 44: 10 01 10 99 evdotpwxgasmfaa3 r0,r1,r2 + 48: 10 01 10 9a evdotpwgasmfraa3 r0,r1,r2 + 4c: 10 01 10 9b evdotpwxgasmfraa3 r0,r1,r2 + 50: 10 01 10 9c evdotpwgssmfaa3 r0,r1,r2 + 54: 10 01 10 9d evdotpwxgssmfaa3 r0,r1,r2 + 58: 10 01 10 9e evdotpwgssmfraa3 r0,r1,r2 + 5c: 10 01 10 9f evdotpwxgssmfraa3 r0,r1,r2 + 60: 10 01 10 a0 evdotpwcssia r0,r1,r2 + 64: 10 01 10 a1 evdotpwcsmia r0,r1,r2 + 68: 10 01 10 a2 evdotpwcssfra r0,r1,r2 + 6c: 10 01 10 a3 evdotpwcssfa r0,r1,r2 + 70: 10 01 10 a8 evdotpwgasmfa r0,r1,r2 + 74: 10 01 10 a9 evdotpwxgasmfa r0,r1,r2 + 78: 10 01 10 aa evdotpwgasmfra r0,r1,r2 + 7c: 10 01 10 ab evdotpwxgasmfra r0,r1,r2 + 80: 10 01 10 ac evdotpwgssmfa r0,r1,r2 + 84: 10 01 10 ad evdotpwxgssmfa r0,r1,r2 + 88: 10 01 10 ae evdotpwgssmfra r0,r1,r2 + 8c: 10 01 10 af evdotpwxgssmfra r0,r1,r2 + 90: 10 01 10 b0 evdotpwcssiaaw r0,r1,r2 + 94: 10 01 10 b1 evdotpwcsmiaaw r0,r1,r2 + 98: 10 01 10 b2 evdotpwcssfraaw r0,r1,r2 + 9c: 10 01 10 b3 evdotpwcssfaaw r0,r1,r2 + a0: 10 01 10 b8 evdotpwgasmfaa r0,r1,r2 + a4: 10 01 10 b9 evdotpwxgasmfaa r0,r1,r2 + a8: 10 01 10 ba evdotpwgasmfraa r0,r1,r2 + ac: 10 01 10 bb evdotpwxgasmfraa r0,r1,r2 + b0: 10 01 10 bc evdotpwgssmfaa r0,r1,r2 + b4: 10 01 10 bd evdotpwxgssmfaa r0,r1,r2 + b8: 10 01 10 be evdotpwgssmfraa r0,r1,r2 + bc: 10 01 10 bf evdotpwxgssmfraa r0,r1,r2 + c0: 10 01 11 00 evdotphihcssi r0,r1,r2 + c4: 10 01 11 01 evdotplohcssi r0,r1,r2 + c8: 10 01 11 02 evdotphihcssf r0,r1,r2 + cc: 10 01 11 03 evdotplohcssf r0,r1,r2 + d0: 10 01 11 08 evdotphihcsmi r0,r1,r2 + d4: 10 01 11 09 evdotplohcsmi r0,r1,r2 + d8: 10 01 11 0a evdotphihcssfr r0,r1,r2 + dc: 10 01 11 0b evdotplohcssfr r0,r1,r2 + e0: 10 01 11 10 evdotphihcssiaaw3 r0,r1,r2 + e4: 10 01 11 11 evdotplohcssiaaw3 r0,r1,r2 + e8: 10 01 11 12 evdotphihcssfaaw3 r0,r1,r2 + ec: 10 01 11 13 evdotplohcssfaaw3 r0,r1,r2 + f0: 10 01 11 18 evdotphihcsmiaaw3 r0,r1,r2 + f4: 10 01 11 19 evdotplohcsmiaaw3 r0,r1,r2 + f8: 10 01 11 1a evdotphihcssfraaw3 r0,r1,r2 + fc: 10 01 11 1b evdotplohcssfraaw3 r0,r1,r2 + 100: 10 01 11 20 evdotphihcssia r0,r1,r2 + 104: 10 01 11 21 evdotplohcssia r0,r1,r2 + 108: 10 01 11 22 evdotphihcssfa r0,r1,r2 + 10c: 10 01 11 23 evdotplohcssfa r0,r1,r2 + 110: 10 01 11 28 evdotphihcsmia r0,r1,r2 + 114: 10 01 11 29 evdotplohcsmia r0,r1,r2 + 118: 10 01 11 2a evdotphihcssfra r0,r1,r2 + 11c: 10 01 11 2b evdotplohcssfra r0,r1,r2 + 120: 10 01 11 30 evdotphihcssiaaw r0,r1,r2 + 124: 10 01 11 31 evdotplohcssiaaw r0,r1,r2 + 128: 10 01 11 32 evdotphihcssfaaw r0,r1,r2 + 12c: 10 01 11 33 evdotplohcssfaaw r0,r1,r2 + 130: 10 01 11 38 evdotphihcsmiaaw r0,r1,r2 + 134: 10 01 11 39 evdotplohcsmiaaw r0,r1,r2 + 138: 10 01 11 3a evdotphihcssfraaw r0,r1,r2 + 13c: 10 01 11 3b evdotplohcssfraaw r0,r1,r2 + 140: 10 01 11 40 evdotphausi r0,r1,r2 + 144: 10 01 11 41 evdotphassi r0,r1,r2 + 148: 10 01 11 42 evdotphasusi r0,r1,r2 + 14c: 10 01 11 43 evdotphassf r0,r1,r2 + 150: 10 01 11 47 evdotphsssf r0,r1,r2 + 154: 10 01 11 48 evdotphaumi r0,r1,r2 + 158: 10 01 11 49 evdotphasmi r0,r1,r2 + 15c: 10 01 11 4a evdotphasumi r0,r1,r2 + 160: 10 01 11 4b evdotphassfr r0,r1,r2 + 164: 10 01 11 4d evdotphssmi r0,r1,r2 + 168: 10 01 11 4f evdotphsssfr r0,r1,r2 + 16c: 10 01 11 50 evdotphausiaaw3 r0,r1,r2 + 170: 10 01 11 51 evdotphassiaaw3 r0,r1,r2 + 174: 10 01 11 52 evdotphasusiaaw3 r0,r1,r2 + 178: 10 01 11 53 evdotphassfaaw3 r0,r1,r2 + 17c: 10 01 11 55 evdotphsssiaaw3 r0,r1,r2 + 180: 10 01 11 57 evdotphsssfaaw3 r0,r1,r2 + 184: 10 01 11 58 evdotphaumiaaw3 r0,r1,r2 + 188: 10 01 11 59 evdotphasmiaaw3 r0,r1,r2 + 18c: 10 01 11 5a evdotphasumiaaw3 r0,r1,r2 + 190: 10 01 11 5b evdotphassfraaw3 r0,r1,r2 + 194: 10 01 11 5d evdotphssmiaaw3 r0,r1,r2 + 198: 10 01 11 5f evdotphsssfraaw3 r0,r1,r2 + 19c: 10 01 11 60 evdotphausia r0,r1,r2 + 1a0: 10 01 11 61 evdotphassia r0,r1,r2 + 1a4: 10 01 11 62 evdotphasusia r0,r1,r2 + 1a8: 10 01 11 63 evdotphassfa r0,r1,r2 + 1ac: 10 01 11 67 evdotphsssfa r0,r1,r2 + 1b0: 10 01 11 68 evdotphaumia r0,r1,r2 + 1b4: 10 01 11 69 evdotphasmia r0,r1,r2 + 1b8: 10 01 11 6a evdotphasumia r0,r1,r2 + 1bc: 10 01 11 6b evdotphassfra r0,r1,r2 + 1c0: 10 01 11 6d evdotphssmia r0,r1,r2 + 1c4: 10 01 11 6f evdotphsssfra r0,r1,r2 + 1c8: 10 01 11 70 evdotphausiaaw r0,r1,r2 + 1cc: 10 01 11 71 evdotphassiaaw r0,r1,r2 + 1d0: 10 01 11 72 evdotphasusiaaw r0,r1,r2 + 1d4: 10 01 11 73 evdotphassfaaw r0,r1,r2 + 1d8: 10 01 11 75 evdotphsssiaaw r0,r1,r2 + 1dc: 10 01 11 77 evdotphsssfaaw r0,r1,r2 + 1e0: 10 01 11 78 evdotphaumiaaw r0,r1,r2 + 1e4: 10 01 11 79 evdotphasmiaaw r0,r1,r2 + 1e8: 10 01 11 7a evdotphasumiaaw r0,r1,r2 + 1ec: 10 01 11 7b evdotphassfraaw r0,r1,r2 + 1f0: 10 01 11 7d evdotphssmiaaw r0,r1,r2 + 1f4: 10 01 11 7f evdotphsssfraaw r0,r1,r2 + 1f8: 10 01 11 80 evdotp4hgaumi r0,r1,r2 + 1fc: 10 01 11 81 evdotp4hgasmi r0,r1,r2 + 200: 10 01 11 82 evdotp4hgasumi r0,r1,r2 + 204: 10 01 11 83 evdotp4hgasmf r0,r1,r2 + 208: 10 01 11 84 evdotp4hgssmi r0,r1,r2 + 20c: 10 01 11 85 evdotp4hgssmf r0,r1,r2 + 210: 10 01 11 86 evdotp4hxgasmi r0,r1,r2 + 214: 10 01 11 87 evdotp4hxgasmf r0,r1,r2 + 218: 10 01 11 88 evdotpbaumi r0,r1,r2 + 21c: 10 01 11 89 evdotpbasmi r0,r1,r2 + 220: 10 01 11 8a evdotpbasumi r0,r1,r2 + 224: 10 01 11 8e evdotp4hxgssmi r0,r1,r2 + 228: 10 01 11 8f evdotp4hxgssmf r0,r1,r2 + 22c: 10 01 11 90 evdotp4hgaumiaa3 r0,r1,r2 + 230: 10 01 11 91 evdotp4hgasmiaa3 r0,r1,r2 + 234: 10 01 11 92 evdotp4hgasumiaa3 r0,r1,r2 + 238: 10 01 11 93 evdotp4hgasmfaa3 r0,r1,r2 + 23c: 10 01 11 94 evdotp4hgssmiaa3 r0,r1,r2 + 240: 10 01 11 95 evdotp4hgssmfaa3 r0,r1,r2 + 244: 10 01 11 96 evdotp4hxgasmiaa3 r0,r1,r2 + 248: 10 01 11 97 evdotp4hxgasmfaa3 r0,r1,r2 + 24c: 10 01 11 98 evdotpbaumiaaw3 r0,r1,r2 + 250: 10 01 11 99 evdotpbasmiaaw3 r0,r1,r2 + 254: 10 01 11 9a evdotpbasumiaaw3 r0,r1,r2 + 258: 10 01 11 9e evdotp4hxgssmiaa3 r0,r1,r2 + 25c: 10 01 11 9f evdotp4hxgssmfaa3 r0,r1,r2 + 260: 10 01 11 a0 evdotp4hgaumia r0,r1,r2 + 264: 10 01 11 a1 evdotp4hgasmia r0,r1,r2 + 268: 10 01 11 a2 evdotp4hgasumia r0,r1,r2 + 26c: 10 01 11 a3 evdotp4hgasmfa r0,r1,r2 + 270: 10 01 11 a4 evdotp4hgssmia r0,r1,r2 + 274: 10 01 11 a5 evdotp4hgssmfa r0,r1,r2 + 278: 10 01 11 a6 evdotp4hxgasmia r0,r1,r2 + 27c: 10 01 11 a7 evdotp4hxgasmfa r0,r1,r2 + 280: 10 01 11 a8 evdotpbaumia r0,r1,r2 + 284: 10 01 11 a9 evdotpbasmia r0,r1,r2 + 288: 10 01 11 aa evdotpbasumia r0,r1,r2 + 28c: 10 01 11 ae evdotp4hxgssmia r0,r1,r2 + 290: 10 01 11 af evdotp4hxgssmfa r0,r1,r2 + 294: 10 01 11 b0 evdotp4hgaumiaa r0,r1,r2 + 298: 10 01 11 b1 evdotp4hgasmiaa r0,r1,r2 + 29c: 10 01 11 b2 evdotp4hgasumiaa r0,r1,r2 + 2a0: 10 01 11 b3 evdotp4hgasmfaa r0,r1,r2 + 2a4: 10 01 11 b4 evdotp4hgssmiaa r0,r1,r2 + 2a8: 10 01 11 b5 evdotp4hgssmfaa r0,r1,r2 + 2ac: 10 01 11 b6 evdotp4hxgasmiaa r0,r1,r2 + 2b0: 10 01 11 b7 evdotp4hxgasmfaa r0,r1,r2 + 2b4: 10 01 11 b8 evdotpbaumiaaw r0,r1,r2 + 2b8: 10 01 11 b9 evdotpbasmiaaw r0,r1,r2 + 2bc: 10 01 11 ba evdotpbasumiaaw r0,r1,r2 + 2c0: 10 01 11 be evdotp4hxgssmiaa r0,r1,r2 + 2c4: 10 01 11 bf evdotp4hxgssmfaa r0,r1,r2 + 2c8: 10 01 11 c0 evdotpwausi r0,r1,r2 + 2cc: 10 01 11 c1 evdotpwassi r0,r1,r2 + 2d0: 10 01 11 c2 evdotpwasusi r0,r1,r2 + 2d4: 10 01 11 c8 evdotpwaumi r0,r1,r2 + 2d8: 10 01 11 c9 evdotpwasmi r0,r1,r2 + 2dc: 10 01 11 ca evdotpwasumi r0,r1,r2 + 2e0: 10 01 11 cd evdotpwssmi r0,r1,r2 + 2e4: 10 01 11 d0 evdotpwausiaa3 r0,r1,r2 + 2e8: 10 01 11 d1 evdotpwassiaa3 r0,r1,r2 + 2ec: 10 01 11 d2 evdotpwasusiaa3 r0,r1,r2 + 2f0: 10 01 11 d5 evdotpwsssiaa3 r0,r1,r2 + 2f4: 10 01 11 d8 evdotpwaumiaa3 r0,r1,r2 + 2f8: 10 01 11 d9 evdotpwasmiaa3 r0,r1,r2 + 2fc: 10 01 11 da evdotpwasumiaa3 r0,r1,r2 + 300: 10 01 11 dd evdotpwssmiaa3 r0,r1,r2 + 304: 10 01 11 e0 evdotpwausia r0,r1,r2 + 308: 10 01 11 e1 evdotpwassia r0,r1,r2 + 30c: 10 01 11 e2 evdotpwasusia r0,r1,r2 + 310: 10 01 11 e8 evdotpwaumia r0,r1,r2 + 314: 10 01 11 e9 evdotpwasmia r0,r1,r2 + 318: 10 01 11 ea evdotpwasumia r0,r1,r2 + 31c: 10 01 11 ed evdotpwssmia r0,r1,r2 + 320: 10 01 11 f0 evdotpwausiaa r0,r1,r2 + 324: 10 01 11 f1 evdotpwassiaa r0,r1,r2 + 328: 10 01 11 f2 evdotpwasusiaa r0,r1,r2 + 32c: 10 01 11 f5 evdotpwsssiaa r0,r1,r2 + 330: 10 01 11 f8 evdotpwaumiaa r0,r1,r2 + 334: 10 01 11 f9 evdotpwasmiaa r0,r1,r2 + 338: 10 01 11 fa evdotpwasumiaa r0,r1,r2 + 33c: 10 01 11 fd evdotpwssmiaa r0,r1,r2 + 340: 10 1f 12 03 evaddib r0,r2,31 + 344: 10 1f 12 01 evaddih r0,r2,31 + 348: 10 1f 12 05 evsubifh r0,31,r2 + 34c: 10 1f 12 07 evsubifb r0,31,r2 + 350: 10 01 12 08 evabsb r0,r1 + 354: 10 01 22 08 evabsh r0,r1 + 358: 10 01 32 08 evabsd r0,r1 + 35c: 10 01 42 08 evabss r0,r1 + 360: 10 01 52 08 evabsbs r0,r1 + 364: 10 01 62 08 evabshs r0,r1 + 368: 10 01 72 08 evabsds r0,r1 + 36c: 10 01 0a 09 evnegwo r0,r1 + 370: 10 01 12 09 evnegb r0,r1 + 374: 10 01 1a 09 evnegbo r0,r1 + 378: 10 01 22 09 evnegh r0,r1 + 37c: 10 01 2a 09 evnegho r0,r1 + 380: 10 01 32 09 evnegd r0,r1 + 384: 10 01 42 09 evnegs r0,r1 + 388: 10 01 4a 09 evnegwos r0,r1 + 38c: 10 01 52 09 evnegbs r0,r1 + 390: 10 01 5a 09 evnegbos r0,r1 + 394: 10 01 62 09 evneghs r0,r1 + 398: 10 01 6a 09 evneghos r0,r1 + 39c: 10 01 72 09 evnegds r0,r1 + 3a0: 10 01 0a 0a evextzb r0,r1 + 3a4: 10 01 22 0a evextsbh r0,r1 + 3a8: 10 01 32 0b evextsw r0,r1 + 3ac: 10 01 02 0c evrndwh r0,r1 + 3b0: 10 01 22 0c evrndhb r0,r1 + 3b4: 10 01 32 0c evrnddw r0,r1 + 3b8: 10 01 42 0c evrndwhus r0,r1 + 3bc: 10 01 4a 0c evrndwhss r0,r1 + 3c0: 10 01 62 0c evrndhbus r0,r1 + 3c4: 10 01 6a 0c evrndhbss r0,r1 + 3c8: 10 01 72 0c evrnddwus r0,r1 + 3cc: 10 01 7a 0c evrnddwss r0,r1 + 3d0: 10 01 82 0c evrndwnh r0,r1 + 3d4: 10 01 a2 0c evrndhnb r0,r1 + 3d8: 10 01 b2 0c evrnddnw r0,r1 + 3dc: 10 01 c2 0c evrndwnhus r0,r1 + 3e0: 10 01 ca 0c evrndwnhss r0,r1 + 3e4: 10 01 e2 0c evrndhnbus r0,r1 + 3e8: 10 01 ea 0c evrndhnbss r0,r1 + 3ec: 10 01 f2 0c evrnddnwus r0,r1 + 3f0: 10 01 fa 0c evrnddnwss r0,r1 + 3f4: 10 01 22 0d evcntlzh r0,r1 + 3f8: 10 01 22 0e evcntlsh r0,r1 + 3fc: 10 01 d2 0e evpopcntb r0,r1 + 400: 10 01 12 10 circinc r0,r1,r2 + 404: 10 01 02 1c evunpkhibui r0,r1 + 408: 10 01 0a 1c evunpkhibsi r0,r1 + 40c: 10 01 12 1c evunpkhihui r0,r1 + 410: 10 01 1a 1c evunpkhihsi r0,r1 + 414: 10 01 22 1c evunpklobui r0,r1 + 418: 10 01 2a 1c evunpklobsi r0,r1 + 41c: 10 01 32 1c evunpklohui r0,r1 + 420: 10 01 3a 1c evunpklohsi r0,r1 + 424: 10 01 42 1c evunpklohf r0,r1 + 428: 10 01 4a 1c evunpkhihf r0,r1 + 42c: 10 01 62 1c evunpklowgsf r0,r1 + 430: 10 01 6a 1c evunpkhiwgsf r0,r1 + 434: 10 01 82 1c evsatsduw r0,r1 + 438: 10 01 8a 1c evsatsdsw r0,r1 + 43c: 10 01 92 1c evsatshub r0,r1 + 440: 10 01 9a 1c evsatshsb r0,r1 + 444: 10 01 a2 1c evsatuwuh r0,r1 + 448: 10 01 aa 1c evsatswsh r0,r1 + 44c: 10 01 b2 1c evsatswuh r0,r1 + 450: 10 01 ba 1c evsatuhub r0,r1 + 454: 10 01 c2 1c evsatuduw r0,r1 + 458: 10 01 ca 1c evsatuwsw r0,r1 + 45c: 10 01 d2 1c evsatshuh r0,r1 + 460: 10 01 da 1c evsatuhsh r0,r1 + 464: 10 01 e2 1c evsatswuw r0,r1 + 468: 10 01 ea 1c evsatswgsdf r0,r1 + 46c: 10 01 f2 1c evsatsbub r0,r1 + 470: 10 01 fa 1c evsatubsb r0,r1 + 474: 10 01 02 1d evmaxhpuw r0,r1 + 478: 10 01 0a 1d evmaxhpsw r0,r1 + 47c: 10 01 22 1d evmaxbpuh r0,r1 + 480: 10 01 2a 1d evmaxbpsh r0,r1 + 484: 10 01 32 1d evmaxwpud r0,r1 + 488: 10 01 3a 1d evmaxwpsd r0,r1 + 48c: 10 01 42 1d evminhpuw r0,r1 + 490: 10 01 4a 1d evminhpsw r0,r1 + 494: 10 01 62 1d evminbpuh r0,r1 + 498: 10 01 6a 1d evminbpsh r0,r1 + 49c: 10 01 72 1d evminwpud r0,r1 + 4a0: 10 01 7a 1d evminwpsd r0,r1 + 4a4: 10 01 12 1f evmaxmagws r0,r1,r2 + 4a8: 10 01 12 25 evsl r0,r1,r2 + 4ac: 10 01 fa 27 evsli r0,r1,31 + 4b0: 10 10 0a 29 evsplatie r0,-16 + 4b4: 10 10 12 29 evsplatib r0,-16 + 4b8: 10 10 1a 29 evsplatibe r0,-16 + 4bc: 10 10 22 29 evsplatih r0,-16 + 4c0: 10 10 2a 29 evsplatihe r0,-16 + 4c4: 10 10 32 29 evsplatid r0,-16 + 4c8: 10 10 82 29 evsplatia r0,-16 + 4cc: 10 10 8a 29 evsplatiea r0,-16 + 4d0: 10 10 92 29 evsplatiba r0,-16 + 4d4: 10 10 9a 29 evsplatibea r0,-16 + 4d8: 10 10 a2 29 evsplatiha r0,-16 + 4dc: 10 10 aa 29 evsplatihea r0,-16 + 4e0: 10 10 b2 29 evsplatida r0,-16 + 4e4: 10 10 0a 2b evsplatfio r0,-16 + 4e8: 10 10 12 2b evsplatfib r0,-16 + 4ec: 10 10 1a 2b evsplatfibo r0,-16 + 4f0: 10 10 22 2b evsplatfih r0,-16 + 4f4: 10 10 2a 2b evsplatfiho r0,-16 + 4f8: 10 10 32 2b evsplatfid r0,-16 + 4fc: 10 10 82 2b evsplatfia r0,-16 + 500: 10 10 8a 2b evsplatfioa r0,-16 + 504: 10 10 92 2b evsplatfiba r0,-16 + 508: 10 10 9a 2b evsplatfiboa r0,-16 + 50c: 10 10 a2 2b evsplatfiha r0,-16 + 510: 10 10 aa 2b evsplatfihoa r0,-16 + 514: 10 10 b2 2b evsplatfida r0,-16 + 518: 10 21 12 30 evcmpgtdu cr0,r1,r2 + 51c: 10 21 12 31 evcmpgtds cr0,r1,r2 + 520: 10 21 12 32 evcmpltdu cr0,r1,r2 + 524: 10 21 12 33 evcmpltds cr0,r1,r2 + 528: 10 21 12 34 evcmpeqd cr0,r1,r2 + 52c: 10 01 12 38 evswapbhilo r0,r1,r2 + 530: 10 01 12 39 evswapblohi r0,r1,r2 + 534: 10 01 12 3a evswaphhilo r0,r1,r2 + 538: 10 01 12 3b evswaphlohi r0,r1,r2 + 53c: 10 01 12 3c evswaphe r0,r1,r2 + 540: 10 01 12 3d evswaphhi r0,r1,r2 + 544: 10 01 12 3e evswaphlo r0,r1,r2 + 548: 10 01 12 3f evswapho r0,r1,r2 + 54c: 10 01 fa 49 evinsb r0,r1,7,7 + 550: 10 01 fa 4b evxtrb r0,r1,7,7 + 554: 10 01 62 4c evsplath r0,r1,3 + 558: 10 01 f2 4c evsplatb r0,r1,7 + 55c: 10 01 7a 4d evinsh r0,r1,3,3 + 560: 10 01 7a 4e evclrbe r0,r1,15 + 564: 10 01 fa 4e evclrbo r0,r1,15 + 568: 10 01 fa 4f evclrh r0,r1,15 + 56c: 10 01 7a 4f evxtrh r0,r1,3,3 + 570: 10 01 12 50 evselbitm0 r0,r1,r2 + 574: 10 01 12 51 evselbitm1 r0,r1,r2 + 578: 10 01 12 52 evselbit r0,r1,r2 + 57c: 10 01 12 54 evperm r0,r1,r2 + 580: 10 01 12 55 evperm2 r0,r1,r2 + 584: 10 01 12 56 evperm3 r0,r1,r2 + 588: 10 01 12 5f evxtrd r0,r1,r2,7 + 58c: 10 01 12 60 evsrbu r0,r1,r2 + 590: 10 01 12 61 evsrbs r0,r1,r2 + 594: 10 01 3a 62 evsrbiu r0,r1,7 + 598: 10 01 3a 63 evsrbis r0,r1,7 + 59c: 10 01 12 64 evslb r0,r1,r2 + 5a0: 10 01 12 65 evrlb r0,r1,r2 + 5a4: 10 01 3a 66 evslbi r0,r1,7 + 5a8: 10 01 3a 67 evrlbi r0,r1,7 + 5ac: 10 01 12 68 evsrhu r0,r1,r2 + 5b0: 10 01 12 69 evsrhs r0,r1,r2 + 5b4: 10 01 7a 6a evsrhiu r0,r1,15 + 5b8: 10 01 7a 6b evsrhis r0,r1,15 + 5bc: 10 01 12 6c evslh r0,r1,r2 + 5c0: 10 01 12 6d evrlh r0,r1,r2 + 5c4: 10 01 7a 6e evslhi r0,r1,15 + 5c8: 10 01 7a 6f evrlhi r0,r1,15 + 5cc: 10 01 12 70 evsru r0,r1,r2 + 5d0: 10 01 12 71 evsrs r0,r1,r2 + 5d4: 10 01 fa 72 evsriu r0,r1,31 + 5d8: 10 01 fa 73 evsris r0,r1,31 + 5dc: 10 01 12 74 evlvsl r0,r1,r2 + 5e0: 10 01 12 75 evlvsr r0,r1,r2 + 5e4: 10 01 3a 77 evsroiu r0,r1,7 + 5e8: 10 01 7a 77 evsrois r0,r1,7 + 5ec: 10 01 ba 77 evsloi r0,r1,7 + 5f0: 10 01 02 87 evfssqrt r0,r1 + 5f4: 10 04 12 91 evfscfh r0,r2 + 5f8: 10 04 12 95 evfscth r0,r2 + 5fc: 10 01 12 a0 evfsmax r0,r1,r2 + 600: 10 01 12 a1 evfsmin r0,r1,r2 + 604: 10 01 12 a2 evfsaddsub r0,r1,r2 + 608: 10 01 12 a3 evfssubadd r0,r1,r2 + 60c: 10 01 12 a4 evfssum r0,r1,r2 + 610: 10 01 12 a5 evfsdiff r0,r1,r2 + 614: 10 01 12 a6 evfssumdiff r0,r1,r2 + 618: 10 01 12 a7 evfsdiffsum r0,r1,r2 + 61c: 10 01 12 a8 evfsaddx r0,r1,r2 + 620: 10 01 12 a9 evfssubx r0,r1,r2 + 624: 10 01 12 aa evfsaddsubx r0,r1,r2 + 628: 10 01 12 ab evfssubaddx r0,r1,r2 + 62c: 10 01 12 ac evfsmulx r0,r1,r2 + 630: 10 01 12 ae evfsmule r0,r1,r2 + 634: 10 01 12 af evfsmulo r0,r1,r2 + 638: 10 01 13 06 evldbx r0,r1,r2 + 63c: 10 01 0b 07 evldb r0,8\(r1\) + 640: 10 01 13 0a evlhhsplathx r0,r1,r2 + 644: 10 01 0b 0b evlhhsplath r0,2\(r1\) + 648: 10 01 13 12 evlwbsplatwx r0,r1,r2 + 64c: 10 01 0b 13 evlwbsplatw r0,4\(r1\) + 650: 10 01 13 1a evlwhsplatwx r0,r1,r2 + 654: 10 01 0b 1b evlwhsplatw r0,4\(r1\) + 658: 10 01 13 1e evlbbsplatbx r0,r1,r2 + 65c: 10 01 0b 1f evlbbsplatb r0,1\(r1\) + 660: 10 01 13 26 evstdbx r0,r1,r2 + 664: 10 01 0b 27 evstdb r0,8\(r1\) + 668: 10 01 13 2a evlwbex r0,r1,r2 + 66c: 10 01 0b 2b evlwbe r0,4\(r1\) + 670: 10 01 13 2c evlwboux r0,r1,r2 + 674: 10 01 0b 2d evlwbou r0,4\(r1\) + 678: 10 01 13 2e evlwbosx r0,r1,r2 + 67c: 10 01 0b 2f evlwbos r0,4\(r1\) + 680: 10 01 13 32 evstwbex r0,r1,r2 + 684: 10 01 0b 33 evstwbe r0,4\(r1\) + 688: 10 01 13 36 evstwbox r0,r1,r2 + 68c: 10 01 0b 37 evstwbo r0,4\(r1\) + 690: 10 01 13 3a evstwbx r0,r1,r2 + 694: 10 01 0b 3b evstwb r0,4\(r1\) + 698: 10 01 13 3e evsthbx r0,r1,r2 + 69c: 10 01 0b 3f evsthb r0,2\(r1\) + 6a0: 10 01 13 40 evlddmx r0,r1,r2 + 6a4: 10 01 0b 41 evlddu r0,8\(r1\) + 6a8: 10 01 13 42 evldwmx r0,r1,r2 + 6ac: 10 01 0b 43 evldwu r0,8\(r1\) + 6b0: 10 01 13 44 evldhmx r0,r1,r2 + 6b4: 10 01 0b 45 evldhu r0,8\(r1\) + 6b8: 10 01 13 46 evldbmx r0,r1,r2 + 6bc: 10 01 0b 47 evldbu r0,8\(r1\) + 6c0: 10 01 13 48 evlhhesplatmx r0,r1,r2 + 6c4: 10 01 0b 49 evlhhesplatu r0,2\(r1\) + 6c8: 10 01 13 4a evlhhsplathmx r0,r1,r2 + 6cc: 10 01 0b 4b evlhhsplathu r0,2\(r1\) + 6d0: 10 01 13 4c evlhhousplatmx r0,r1,r2 + 6d4: 10 01 0b 4d evlhhousplatu r0,2\(r1\) + 6d8: 10 01 13 4e evlhhossplatmx r0,r1,r2 + 6dc: 10 01 0b 4f evlhhossplatu r0,2\(r1\) + 6e0: 10 01 13 50 evlwhemx r0,r1,r2 + 6e4: 10 01 0b 51 evlwheu r0,4\(r1\) + 6e8: 10 01 13 52 evlwbsplatwmx r0,r1,r2 + 6ec: 10 01 0b 53 evlwbsplatwu r0,4\(r1\) + 6f0: 10 01 13 54 evlwhoumx r0,r1,r2 + 6f4: 10 01 0b 55 evlwhouu r0,4\(r1\) + 6f8: 10 01 13 56 evlwhosmx r0,r1,r2 + 6fc: 10 01 0b 57 evlwhosu r0,4\(r1\) + 700: 10 01 13 58 evlwwsplatmx r0,r1,r2 + 704: 10 01 0b 59 evlwwsplatu r0,4\(r1\) + 708: 10 01 13 5a evlwhsplatwmx r0,r1,r2 + 70c: 10 01 0b 5b evlwhsplatwu r0,4\(r1\) + 710: 10 01 13 5c evlwhsplatmx r0,r1,r2 + 714: 10 01 0b 5d evlwhsplatu r0,4\(r1\) + 718: 10 01 13 5e evlbbsplatbmx r0,r1,r2 + 71c: 10 01 0b 5f evlbbsplatbu r0,1\(r1\) + 720: 10 01 13 60 evstddmx r0,r1,r2 + 724: 10 01 0b 61 evstddu r0,8\(r1\) + 728: 10 01 13 62 evstdwmx r0,r1,r2 + 72c: 10 01 0b 63 evstdwu r0,8\(r1\) + 730: 10 01 13 64 evstdhmx r0,r1,r2 + 734: 10 01 0b 65 evstdhu r0,8\(r1\) + 738: 10 01 13 66 evstdbmx r0,r1,r2 + 73c: 10 01 0b 67 evstdbu r0,8\(r1\) + 740: 10 01 13 6a evlwbemx r0,r1,r2 + 744: 10 01 0b 6b evlwbeu r0,4\(r1\) + 748: 10 01 13 6c evlwboumx r0,r1,r2 + 74c: 10 01 0b 6d evlwbouu r0,4\(r1\) + 750: 10 01 13 6e evlwbosmx r0,r1,r2 + 754: 10 01 0b 6f evlwbosu r0,4\(r1\) + 758: 10 01 13 70 evstwhemx r0,r1,r2 + 75c: 10 01 0b 71 evstwheu r0,4\(r1\) + 760: 10 01 13 72 evstwbemx r0,r1,r2 + 764: 10 01 0b 73 evstwbeu r0,4\(r1\) + 768: 10 01 13 74 evstwhomx r0,r1,r2 + 76c: 10 01 0b 75 evstwhou r0,4\(r1\) + 770: 10 01 13 76 evstwbomx r0,r1,r2 + 774: 10 01 0b 77 evstwbou r0,4\(r1\) + 778: 10 01 13 78 evstwwemx r0,r1,r2 + 77c: 10 01 0b 79 evstwweu r0,4\(r1\) + 780: 10 01 13 7a evstwbmx r0,r1,r2 + 784: 10 01 0b 7b evstwbu r0,4\(r1\) + 788: 10 01 13 7c evstwwomx r0,r1,r2 + 78c: 10 01 0b 7d evstwwou r0,4\(r1\) + 790: 10 01 13 7e evsthbmx r0,r1,r2 + 794: 10 01 0b 7f evsthbu r0,2\(r1\) + 798: 10 01 14 00 evmhusi r0,r1,r2 + 79c: 10 01 14 01 evmhssi r0,r1,r2 + 7a0: 10 01 14 02 evmhsusi r0,r1,r2 + 7a4: 10 01 14 04 evmhssf r0,r1,r2 + 7a8: 10 01 14 05 evmhumi r0,r1,r2 + 7ac: 10 01 14 06 evmhssfr r0,r1,r2 + 7b0: 10 01 14 0a evmhesumi r0,r1,r2 + 7b4: 10 01 14 0e evmhosumi r0,r1,r2 + 7b8: 10 01 14 18 evmbeumi r0,r1,r2 + 7bc: 10 01 14 19 evmbesmi r0,r1,r2 + 7c0: 10 01 14 1a evmbesumi r0,r1,r2 + 7c4: 10 01 14 1c evmboumi r0,r1,r2 + 7c8: 10 01 14 1d evmbosmi r0,r1,r2 + 7cc: 10 01 14 1e evmbosumi r0,r1,r2 + 7d0: 10 01 14 2a evmhesumia r0,r1,r2 + 7d4: 10 01 14 2e evmhosumia r0,r1,r2 + 7d8: 10 01 14 38 evmbeumia r0,r1,r2 + 7dc: 10 01 14 39 evmbesmia r0,r1,r2 + 7e0: 10 01 14 3a evmbesumia r0,r1,r2 + 7e4: 10 01 14 3c evmboumia r0,r1,r2 + 7e8: 10 01 14 3d evmbosmia r0,r1,r2 + 7ec: 10 01 14 3e evmbosumia r0,r1,r2 + 7f0: 10 01 14 40 evmwusiw r0,r1,r2 + 7f4: 10 01 14 41 evmwssiw r0,r1,r2 + 7f8: 10 01 14 46 evmwhssfr r0,r1,r2 + 7fc: 10 01 14 56 evmwehgsmfr r0,r1,r2 + 800: 10 01 14 57 evmwehgsmf r0,r1,r2 + 804: 10 01 14 5e evmwohgsmfr r0,r1,r2 + 808: 10 01 14 5f evmwohgsmf r0,r1,r2 + 80c: 10 01 14 66 evmwhssfra r0,r1,r2 + 810: 10 01 14 76 evmwehgsmfra r0,r1,r2 + 814: 10 01 14 77 evmwehgsmfa r0,r1,r2 + 818: 10 01 14 7e evmwohgsmfra r0,r1,r2 + 81c: 10 01 14 7f evmwohgsmfa r0,r1,r2 + 820: 10 01 04 80 evaddusiaa r0,r1 + 824: 10 01 04 81 evaddssiaa r0,r1 + 828: 10 01 04 82 evsubfusiaa r0,r1 + 82c: 10 01 04 83 evsubfssiaa r0,r1 + 830: 10 01 04 84 evaddsmiaa r0,r1 + 834: 10 01 04 86 evsubfsmiaa r0,r1 + 838: 10 01 14 88 evaddh r0,r1,r2 + 83c: 10 01 14 89 evaddhss r0,r1,r2 + 840: 10 01 14 8a evsubfh r0,r1,r2 + 844: 10 01 14 8b evsubfhss r0,r1,r2 + 848: 10 01 14 8c evaddhx r0,r1,r2 + 84c: 10 01 14 8d evaddhxss r0,r1,r2 + 850: 10 01 14 8e evsubfhx r0,r1,r2 + 854: 10 01 14 8f evsubfhxss r0,r1,r2 + 858: 10 01 14 90 evaddd r0,r1,r2 + 85c: 10 01 14 91 evadddss r0,r1,r2 + 860: 10 01 14 92 evsubfd r0,r1,r2 + 864: 10 01 14 93 evsubfdss r0,r1,r2 + 868: 10 01 14 94 evaddb r0,r1,r2 + 86c: 10 01 14 95 evaddbss r0,r1,r2 + 870: 10 01 14 96 evsubfb r0,r1,r2 + 874: 10 01 14 97 evsubfbss r0,r1,r2 + 878: 10 01 14 98 evaddsubfh r0,r1,r2 + 87c: 10 01 14 99 evaddsubfhss r0,r1,r2 + 880: 10 01 14 9a evsubfaddh r0,r1,r2 + 884: 10 01 14 9b evsubfaddhss r0,r1,r2 + 888: 10 01 14 9c evaddsubfhx r0,r1,r2 + 88c: 10 01 14 9d evaddsubfhxss r0,r1,r2 + 890: 10 01 14 9e evsubfaddhx r0,r1,r2 + 894: 10 01 14 9f evsubfaddhxss r0,r1,r2 + 898: 10 01 14 a0 evadddus r0,r1,r2 + 89c: 10 01 14 a1 evaddbus r0,r1,r2 + 8a0: 10 01 14 a2 evsubfdus r0,r1,r2 + 8a4: 10 01 14 a3 evsubfbus r0,r1,r2 + 8a8: 10 01 14 a4 evaddwus r0,r1,r2 + 8ac: 10 01 14 a5 evaddwxus r0,r1,r2 + 8b0: 10 01 14 a6 evsubfwus r0,r1,r2 + 8b4: 10 01 14 a7 evsubfwxus r0,r1,r2 + 8b8: 10 01 14 a8 evadd2subf2h r0,r1,r2 + 8bc: 10 01 14 a9 evadd2subf2hss r0,r1,r2 + 8c0: 10 01 14 aa evsubf2add2h r0,r1,r2 + 8c4: 10 01 14 ab evsubf2add2hss r0,r1,r2 + 8c8: 10 01 14 ac evaddhus r0,r1,r2 + 8cc: 10 01 14 ad evaddhxus r0,r1,r2 + 8d0: 10 01 14 ae evsubfhus r0,r1,r2 + 8d4: 10 01 14 af evsubfhxus r0,r1,r2 + 8d8: 10 01 14 b1 evaddwss r0,r1,r2 + 8dc: 10 01 14 b3 evsubfwss r0,r1,r2 + 8e0: 10 01 14 b4 evaddwx r0,r1,r2 + 8e4: 10 01 14 b5 evaddwxss r0,r1,r2 + 8e8: 10 01 14 b6 evsubfwx r0,r1,r2 + 8ec: 10 01 14 b7 evsubfwxss r0,r1,r2 + 8f0: 10 01 14 b8 evaddsubfw r0,r1,r2 + 8f4: 10 01 14 b9 evaddsubfwss r0,r1,r2 + 8f8: 10 01 14 ba evsubfaddw r0,r1,r2 + 8fc: 10 01 14 bb evsubfaddwss r0,r1,r2 + 900: 10 01 14 bc evaddsubfwx r0,r1,r2 + 904: 10 01 14 bd evaddsubfwxss r0,r1,r2 + 908: 10 01 14 be evsubfaddwx r0,r1,r2 + 90c: 10 01 14 bf evsubfaddwxss r0,r1,r2 + 910: 10 00 0c c4 evmar r0 + 914: 10 01 04 c5 evsumwu r0,r1 + 918: 10 01 0c c5 evsumws r0,r1 + 91c: 10 01 14 c5 evsum4bu r0,r1 + 920: 10 01 1c c5 evsum4bs r0,r1 + 924: 10 01 24 c5 evsum2hu r0,r1 + 928: 10 01 2c c5 evsum2hs r0,r1 + 92c: 10 01 34 c5 evdiff2his r0,r1 + 930: 10 01 3c c5 evsum2his r0,r1 + 934: 10 01 84 c5 evsumwua r0,r1 + 938: 10 01 8c c5 evsumwsa r0,r1 + 93c: 10 01 94 c5 evsum4bua r0,r1 + 940: 10 01 9c c5 evsum4bsa r0,r1 + 944: 10 01 a4 c5 evsum2hua r0,r1 + 948: 10 01 ac c5 evsum2hsa r0,r1 + 94c: 10 01 b4 c5 evdiff2hisa r0,r1 + 950: 10 01 bc c5 evsum2hisa r0,r1 + 954: 10 01 c4 c5 evsumwuaa r0,r1 + 958: 10 01 cc c5 evsumwsaa r0,r1 + 95c: 10 01 d4 c5 evsum4buaaw r0,r1 + 960: 10 01 dc c5 evsum4bsaaw r0,r1 + 964: 10 01 e4 c5 evsum2huaaw r0,r1 + 968: 10 01 ec c5 evsum2hsaaw r0,r1 + 96c: 10 01 f4 c5 evdiff2hisaaw r0,r1 + 970: 10 01 fc c5 evsum2hisaaw r0,r1 + 974: 10 01 14 cc evdivwsf r0,r1,r2 + 978: 10 01 14 cd evdivwuf r0,r1,r2 + 97c: 10 01 14 ce evdivs r0,r1,r2 + 980: 10 01 14 cf evdivu r0,r1,r2 + 984: 10 01 14 d0 evaddwegsi r0,r1,r2 + 988: 10 01 14 d1 evaddwegsf r0,r1,r2 + 98c: 10 01 14 d2 evsubfwegsi r0,r1,r2 + 990: 10 01 14 d3 evsubfwegsf r0,r1,r2 + 994: 10 01 14 d4 evaddwogsi r0,r1,r2 + 998: 10 01 14 d5 evaddwogsf r0,r1,r2 + 99c: 10 01 14 d6 evsubfwogsi r0,r1,r2 + 9a0: 10 01 14 d7 evsubfwogsf r0,r1,r2 + 9a4: 10 01 14 d8 evaddhhiuw r0,r1,r2 + 9a8: 10 01 14 d9 evaddhhisw r0,r1,r2 + 9ac: 10 01 14 da evsubfhhiuw r0,r1,r2 + 9b0: 10 01 14 db evsubfhhisw r0,r1,r2 + 9b4: 10 01 14 dc evaddhlouw r0,r1,r2 + 9b8: 10 01 14 dd evaddhlosw r0,r1,r2 + 9bc: 10 01 14 de evsubfhlouw r0,r1,r2 + 9c0: 10 01 14 df evsubfhlosw r0,r1,r2 + 9c4: 10 01 15 02 evmhesusiaaw r0,r1,r2 + 9c8: 10 01 15 06 evmhosusiaaw r0,r1,r2 + 9cc: 10 01 15 0a evmhesumiaaw r0,r1,r2 + 9d0: 10 01 15 0e evmhosumiaaw r0,r1,r2 + 9d4: 10 01 15 10 evmbeusiaah r0,r1,r2 + 9d8: 10 01 15 11 evmbessiaah r0,r1,r2 + 9dc: 10 01 15 12 evmbesusiaah r0,r1,r2 + 9e0: 10 01 15 14 evmbousiaah r0,r1,r2 + 9e4: 10 01 15 15 evmbossiaah r0,r1,r2 + 9e8: 10 01 15 16 evmbosusiaah r0,r1,r2 + 9ec: 10 01 15 18 evmbeumiaah r0,r1,r2 + 9f0: 10 01 15 19 evmbesmiaah r0,r1,r2 + 9f4: 10 01 15 1a evmbesumiaah r0,r1,r2 + 9f8: 10 01 15 1c evmboumiaah r0,r1,r2 + 9fc: 10 01 15 1d evmbosmiaah r0,r1,r2 + a00: 10 01 15 1e evmbosumiaah r0,r1,r2 + a04: 10 01 15 42 evmwlusiaaw3 r0,r1,r2 + a08: 10 01 15 43 evmwlssiaaw3 r0,r1,r2 + a0c: 10 01 15 44 evmwhssfraaw3 r0,r1,r2 + a10: 10 01 15 45 evmwhssfaaw3 r0,r1,r2 + a14: 10 01 15 46 evmwhssfraaw r0,r1,r2 + a18: 10 01 15 47 evmwhssfaaw r0,r1,r2 + a1c: 10 01 15 4a evmwlumiaaw3 r0,r1,r2 + a20: 10 01 15 4b evmwlsmiaaw3 r0,r1,r2 + a24: 10 01 15 50 evmwusiaa r0,r1,r2 + a28: 10 01 15 51 evmwssiaa r0,r1,r2 + a2c: 10 01 15 56 evmwehgsmfraa r0,r1,r2 + a30: 10 01 15 57 evmwehgsmfaa r0,r1,r2 + a34: 10 01 15 5e evmwohgsmfraa r0,r1,r2 + a38: 10 01 15 5f evmwohgsmfaa r0,r1,r2 + a3c: 10 01 15 82 evmhesusianw r0,r1,r2 + a40: 10 01 15 86 evmhosusianw r0,r1,r2 + a44: 10 01 15 8a evmhesumianw r0,r1,r2 + a48: 10 01 15 8e evmhosumianw r0,r1,r2 + a4c: 10 01 15 90 evmbeusianh r0,r1,r2 + a50: 10 01 15 91 evmbessianh r0,r1,r2 + a54: 10 01 15 92 evmbesusianh r0,r1,r2 + a58: 10 01 15 94 evmbousianh r0,r1,r2 + a5c: 10 01 15 95 evmbossianh r0,r1,r2 + a60: 10 01 15 96 evmbosusianh r0,r1,r2 + a64: 10 01 15 98 evmbeumianh r0,r1,r2 + a68: 10 01 15 99 evmbesmianh r0,r1,r2 + a6c: 10 01 15 9a evmbesumianh r0,r1,r2 + a70: 10 01 15 9c evmboumianh r0,r1,r2 + a74: 10 01 15 9d evmbosmianh r0,r1,r2 + a78: 10 01 15 9e evmbosumianh r0,r1,r2 + a7c: 10 01 15 c2 evmwlusianw3 r0,r1,r2 + a80: 10 01 15 c3 evmwlssianw3 r0,r1,r2 + a84: 10 01 15 c4 evmwhssfranw3 r0,r1,r2 + a88: 10 01 15 c5 evmwhssfanw3 r0,r1,r2 + a8c: 10 01 15 c6 evmwhssfranw r0,r1,r2 + a90: 10 01 15 c7 evmwhssfanw r0,r1,r2 + a94: 10 01 15 ca evmwlumianw3 r0,r1,r2 + a98: 10 01 15 cb evmwlsmianw3 r0,r1,r2 + a9c: 10 01 15 d0 evmwusian r0,r1,r2 + aa0: 10 01 15 d1 evmwssian r0,r1,r2 + aa4: 10 01 15 d6 evmwehgsmfran r0,r1,r2 + aa8: 10 01 15 d7 evmwehgsmfan r0,r1,r2 + aac: 10 01 15 de evmwohgsmfran r0,r1,r2 + ab0: 10 01 15 df evmwohgsmfan r0,r1,r2 + ab4: 10 01 16 00 evseteqb r0,r1,r2 + ab8: 10 01 16 01 evseteqb. r0,r1,r2 + abc: 10 01 16 02 evseteqh r0,r1,r2 + ac0: 10 01 16 03 evseteqh. r0,r1,r2 + ac4: 10 01 16 04 evseteqw r0,r1,r2 + ac8: 10 01 16 05 evseteqw. r0,r1,r2 + acc: 10 01 16 08 evsetgthu r0,r1,r2 + ad0: 10 01 16 09 evsetgthu. r0,r1,r2 + ad4: 10 01 16 0a evsetgths r0,r1,r2 + ad8: 10 01 16 0b evsetgths. r0,r1,r2 + adc: 10 01 16 0c evsetgtwu r0,r1,r2 + ae0: 10 01 16 0d evsetgtwu. r0,r1,r2 + ae4: 10 01 16 0e evsetgtws r0,r1,r2 + ae8: 10 01 16 0f evsetgtws. r0,r1,r2 + aec: 10 01 16 10 evsetgtbu r0,r1,r2 + af0: 10 01 16 11 evsetgtbu. r0,r1,r2 + af4: 10 01 16 12 evsetgtbs r0,r1,r2 + af8: 10 01 16 13 evsetgtbs. r0,r1,r2 + afc: 10 01 16 14 evsetltbu r0,r1,r2 + b00: 10 01 16 15 evsetltbu. r0,r1,r2 + b04: 10 01 16 16 evsetltbs r0,r1,r2 + b08: 10 01 16 17 evsetltbs. r0,r1,r2 + b0c: 10 01 16 18 evsetlthu r0,r1,r2 + b10: 10 01 16 19 evsetlthu. r0,r1,r2 + b14: 10 01 16 1a evsetlths r0,r1,r2 + b18: 10 01 16 1b evsetlths. r0,r1,r2 + b1c: 10 01 16 1c evsetltwu r0,r1,r2 + b20: 10 01 16 1d evsetltwu. r0,r1,r2 + b24: 10 01 16 1e evsetltws r0,r1,r2 + b28: 10 01 16 1f evsetltws. r0,r1,r2 + b2c: 10 01 16 20 evsaduw r0,r1,r2 + b30: 10 01 16 21 evsadsw r0,r1,r2 + b34: 10 01 16 22 evsad4ub r0,r1,r2 + b38: 10 01 16 23 evsad4sb r0,r1,r2 + b3c: 10 01 16 24 evsad2uh r0,r1,r2 + b40: 10 01 16 25 evsad2sh r0,r1,r2 + b44: 10 01 16 28 evsaduwa r0,r1,r2 + b48: 10 01 16 29 evsadswa r0,r1,r2 + b4c: 10 01 16 2a evsad4uba r0,r1,r2 + b50: 10 01 16 2b evsad4sba r0,r1,r2 + b54: 10 01 16 2c evsad2uha r0,r1,r2 + b58: 10 01 16 2d evsad2sha r0,r1,r2 + b5c: 10 01 16 30 evabsdifuw r0,r1,r2 + b60: 10 01 16 31 evabsdifsw r0,r1,r2 + b64: 10 01 16 32 evabsdifub r0,r1,r2 + b68: 10 01 16 33 evabsdifsb r0,r1,r2 + b6c: 10 01 16 34 evabsdifuh r0,r1,r2 + b70: 10 01 16 35 evabsdifsh r0,r1,r2 + b74: 10 01 16 38 evsaduwaa r0,r1,r2 + b78: 10 01 16 39 evsadswaa r0,r1,r2 + b7c: 10 01 16 3a evsad4ubaaw r0,r1,r2 + b80: 10 01 16 3b evsad4sbaaw r0,r1,r2 + b84: 10 01 16 3c evsad2uhaaw r0,r1,r2 + b88: 10 01 16 3d evsad2shaaw r0,r1,r2 + b8c: 10 01 16 40 evpkshubs r0,r1,r2 + b90: 10 01 16 41 evpkshsbs r0,r1,r2 + b94: 10 01 16 42 evpkswuhs r0,r1,r2 + b98: 10 01 16 43 evpkswshs r0,r1,r2 + b9c: 10 01 16 44 evpkuhubs r0,r1,r2 + ba0: 10 01 16 45 evpkuwuhs r0,r1,r2 + ba4: 10 01 16 46 evpkswshilvs r0,r1,r2 + ba8: 10 01 16 47 evpkswgshefrs r0,r1,r2 + bac: 10 01 16 48 evpkswshfrs r0,r1,r2 + bb0: 10 01 16 49 evpkswshilvfrs r0,r1,r2 + bb4: 10 01 16 4a evpksdswfrs r0,r1,r2 + bb8: 10 01 16 4b evpksdshefrs r0,r1,r2 + bbc: 10 01 16 4c evpkuduws r0,r1,r2 + bc0: 10 01 16 4d evpksdsws r0,r1,r2 + bc4: 10 01 16 4e evpkswgswfrs r0,r1,r2 + bc8: 10 01 16 50 evilveh r0,r1,r2 + bcc: 10 01 16 51 evilveoh r0,r1,r2 + bd0: 10 01 16 52 evilvhih r0,r1,r2 + bd4: 10 01 16 53 evilvhiloh r0,r1,r2 + bd8: 10 01 16 54 evilvloh r0,r1,r2 + bdc: 10 01 16 55 evilvlohih r0,r1,r2 + be0: 10 01 16 56 evilvoeh r0,r1,r2 + be4: 10 01 16 57 evilvoh r0,r1,r2 + be8: 10 01 16 58 evdlveb r0,r1,r2 + bec: 10 01 16 59 evdlveh r0,r1,r2 + bf0: 10 01 16 5a evdlveob r0,r1,r2 + bf4: 10 01 16 5b evdlveoh r0,r1,r2 + bf8: 10 01 16 5c evdlvob r0,r1,r2 + bfc: 10 01 16 5d evdlvoh r0,r1,r2 + c00: 10 01 16 5e evdlvoeb r0,r1,r2 + c04: 10 01 16 5f evdlvoeh r0,r1,r2 + c08: 10 01 16 60 evmaxbu r0,r1,r2 + c0c: 10 01 16 61 evmaxbs r0,r1,r2 + c10: 10 01 16 62 evmaxhu r0,r1,r2 + c14: 10 01 16 63 evmaxhs r0,r1,r2 + c18: 10 01 16 64 evmaxwu r0,r1,r2 + c1c: 10 01 16 65 evmaxws r0,r1,r2 + c20: 10 01 16 66 evmaxdu r0,r1,r2 + c24: 10 01 16 67 evmaxds r0,r1,r2 + c28: 10 01 16 68 evminbu r0,r1,r2 + c2c: 10 01 16 69 evminbs r0,r1,r2 + c30: 10 01 16 6a evminhu r0,r1,r2 + c34: 10 01 16 6b evminhs r0,r1,r2 + c38: 10 01 16 6c evminwu r0,r1,r2 + c3c: 10 01 16 6d evminws r0,r1,r2 + c40: 10 01 16 6e evmindu r0,r1,r2 + c44: 10 01 16 6f evminds r0,r1,r2 + c48: 10 01 16 70 evavgwu r0,r1,r2 + c4c: 10 01 16 71 evavgws r0,r1,r2 + c50: 10 01 16 72 evavgbu r0,r1,r2 + c54: 10 01 16 73 evavgbs r0,r1,r2 + c58: 10 01 16 74 evavghu r0,r1,r2 + c5c: 10 01 16 75 evavghs r0,r1,r2 + c60: 10 01 16 76 evavgdu r0,r1,r2 + c64: 10 01 16 77 evavgds r0,r1,r2 + c68: 10 01 16 78 evavgwur r0,r1,r2 + c6c: 10 01 16 79 evavgwsr r0,r1,r2 + c70: 10 01 16 7a evavgbur r0,r1,r2 + c74: 10 01 16 7b evavgbsr r0,r1,r2 + c78: 10 01 16 7c evavghur r0,r1,r2 + c7c: 10 01 16 7d evavghsr r0,r1,r2 + c80: 10 01 16 7e evavgdur r0,r1,r2 + c84: 10 01 16 7f evavgdsr r0,r1,r2 + c88: 10 01 11 4d evdotphssmi r0,r1,r2 + c8c: 10 01 11 6d evdotphssmia r0,r1,r2 + c90: 10 01 11 cd evdotpwssmi r0,r1,r2 + c94: 10 01 11 ed evdotpwssmia r0,r1,r2 diff --git a/gas/testsuite/gas/ppc/spe2.s b/gas/testsuite/gas/ppc/spe2.s new file mode 100644 index 0000000..37b6cdb --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2.s @@ -0,0 +1,834 @@ +# PA SPE2 instructions +# Testcase for CMPE200GCC-5, CMPE200GCC-62 + + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ UIMM, 31 + .equ UIMM_LT8, 7 + .equ UIMM_LT16, 15 + .equ UIMM_1, 1 + .equ UIMM_2, 2 + .equ UIMM_4, 4 + .equ UIMM_8, 8 + .equ SIMM, -16 + .equ crD, 0 + .equ nnn, 7 + .equ bbb, 7 + .equ dd, 3 + .equ Ddd, 7 + .equ hh, 3 + .equ mask, 15 + .equ offset, 7 + + evdotpwcssi rD, rA, rB + evdotpwcsmi rD, rA, rB + evdotpwcssfr rD, rA, rB + evdotpwcssf rD, rA, rB + evdotpwgasmf rD, rA, rB + evdotpwxgasmf rD, rA, rB + evdotpwgasmfr rD, rA, rB + evdotpwxgasmfr rD, rA, rB + evdotpwgssmf rD, rA, rB + evdotpwxgssmf rD, rA, rB + evdotpwgssmfr rD, rA, rB + evdotpwxgssmfr rD, rA, rB + evdotpwcssiaaw3 rD, rA, rB + evdotpwcsmiaaw3 rD, rA, rB + evdotpwcssfraaw3 rD, rA, rB + evdotpwcssfaaw3 rD, rA, rB + evdotpwgasmfaa3 rD, rA, rB + evdotpwxgasmfaa3 rD, rA, rB + evdotpwgasmfraa3 rD, rA, rB + evdotpwxgasmfraa3 rD, rA, rB + evdotpwgssmfaa3 rD, rA, rB + evdotpwxgssmfaa3 rD, rA, rB + evdotpwgssmfraa3 rD, rA, rB + evdotpwxgssmfraa3 rD, rA, rB + evdotpwcssia rD, rA, rB + evdotpwcsmia rD, rA, rB + evdotpwcssfra rD, rA, rB + evdotpwcssfa rD, rA, rB + evdotpwgasmfa rD, rA, rB + evdotpwxgasmfa rD, rA, rB + evdotpwgasmfra rD, rA, rB + evdotpwxgasmfra rD, rA, rB + evdotpwgssmfa rD, rA, rB + evdotpwxgssmfa rD, rA, rB + evdotpwgssmfra rD, rA, rB + evdotpwxgssmfra rD, rA, rB + evdotpwcssiaaw rD, rA, rB + evdotpwcsmiaaw rD, rA, rB + evdotpwcssfraaw rD, rA, rB + evdotpwcssfaaw rD, rA, rB + evdotpwgasmfaa rD, rA, rB + evdotpwxgasmfaa rD, rA, rB + evdotpwgasmfraa rD, rA, rB + evdotpwxgasmfraa rD, rA, rB + evdotpwgssmfaa rD, rA, rB + evdotpwxgssmfaa rD, rA, rB + evdotpwgssmfraa rD, rA, rB + evdotpwxgssmfraa rD, rA, rB + evdotphihcssi rD, rA, rB + evdotplohcssi rD, rA, rB + evdotphihcssf rD, rA, rB + evdotplohcssf rD, rA, rB + evdotphihcsmi rD, rA, rB + evdotplohcsmi rD, rA, rB + evdotphihcssfr rD, rA, rB + evdotplohcssfr rD, rA, rB + evdotphihcssiaaw3 rD, rA, rB + evdotplohcssiaaw3 rD, rA, rB + evdotphihcssfaaw3 rD, rA, rB + evdotplohcssfaaw3 rD, rA, rB + evdotphihcsmiaaw3 rD, rA, rB + evdotplohcsmiaaw3 rD, rA, rB + evdotphihcssfraaw3 rD, rA, rB + evdotplohcssfraaw3 rD, rA, rB + evdotphihcssia rD, rA, rB + evdotplohcssia rD, rA, rB + evdotphihcssfa rD, rA, rB + evdotplohcssfa rD, rA, rB + evdotphihcsmia rD, rA, rB + evdotplohcsmia rD, rA, rB + evdotphihcssfra rD, rA, rB + evdotplohcssfra rD, rA, rB + evdotphihcssiaaw rD, rA, rB + evdotplohcssiaaw rD, rA, rB + evdotphihcssfaaw rD, rA, rB + evdotplohcssfaaw rD, rA, rB + evdotphihcsmiaaw rD, rA, rB + evdotplohcsmiaaw rD, rA, rB + evdotphihcssfraaw rD, rA, rB + evdotplohcssfraaw rD, rA, rB + evdotphausi rD, rA, rB + evdotphassi rD, rA, rB + evdotphasusi rD, rA, rB + evdotphassf rD, rA, rB + evdotphsssf rD, rA, rB + evdotphaumi rD, rA, rB + evdotphasmi rD, rA, rB + evdotphasumi rD, rA, rB + evdotphassfr rD, rA, rB + evdotphssmi rD, rA, rB + evdotphsssfr rD, rA, rB + evdotphausiaaw3 rD, rA, rB + evdotphassiaaw3 rD, rA, rB + evdotphasusiaaw3 rD, rA, rB + evdotphassfaaw3 rD, rA, rB + evdotphsssiaaw3 rD, rA, rB + evdotphsssfaaw3 rD, rA, rB + evdotphaumiaaw3 rD, rA, rB + evdotphasmiaaw3 rD, rA, rB + evdotphasumiaaw3 rD, rA, rB + evdotphassfraaw3 rD, rA, rB + evdotphssmiaaw3 rD, rA, rB + evdotphsssfraaw3 rD, rA, rB + evdotphausia rD, rA, rB + evdotphassia rD, rA, rB + evdotphasusia rD, rA, rB + evdotphassfa rD, rA, rB + evdotphsssfa rD, rA, rB + evdotphaumia rD, rA, rB + evdotphasmia rD, rA, rB + evdotphasumia rD, rA, rB + evdotphassfra rD, rA, rB + evdotphssmia rD, rA, rB + evdotphsssfra rD, rA, rB + evdotphausiaaw rD, rA, rB + evdotphassiaaw rD, rA, rB + evdotphasusiaaw rD, rA, rB + evdotphassfaaw rD, rA, rB + evdotphsssiaaw rD, rA, rB + evdotphsssfaaw rD, rA, rB + evdotphaumiaaw rD, rA, rB + evdotphasmiaaw rD, rA, rB + evdotphasumiaaw rD, rA, rB + evdotphassfraaw rD, rA, rB + evdotphssmiaaw rD, rA, rB + evdotphsssfraaw rD, rA, rB + evdotp4hgaumi rD, rA, rB + evdotp4hgasmi rD, rA, rB + evdotp4hgasumi rD, rA, rB + evdotp4hgasmf rD, rA, rB + evdotp4hgssmi rD, rA, rB + evdotp4hgssmf rD, rA, rB + evdotp4hxgasmi rD, rA, rB + evdotp4hxgasmf rD, rA, rB + evdotpbaumi rD, rA, rB + evdotpbasmi rD, rA, rB + evdotpbasumi rD, rA, rB + evdotp4hxgssmi rD, rA, rB + evdotp4hxgssmf rD, rA, rB + evdotp4hgaumiaa3 rD, rA, rB + evdotp4hgasmiaa3 rD, rA, rB + evdotp4hgasumiaa3 rD, rA, rB + evdotp4hgasmfaa3 rD, rA, rB + evdotp4hgssmiaa3 rD, rA, rB + evdotp4hgssmfaa3 rD, rA, rB + evdotp4hxgasmiaa3 rD, rA, rB + evdotp4hxgasmfaa3 rD, rA, rB + evdotpbaumiaaw3 rD, rA, rB + evdotpbasmiaaw3 rD, rA, rB + evdotpbasumiaaw3 rD, rA, rB + evdotp4hxgssmiaa3 rD, rA, rB + evdotp4hxgssmfaa3 rD, rA, rB + evdotp4hgaumia rD, rA, rB + evdotp4hgasmia rD, rA, rB + evdotp4hgasumia rD, rA, rB + evdotp4hgasmfa rD, rA, rB + evdotp4hgssmia rD, rA, rB + evdotp4hgssmfa rD, rA, rB + evdotp4hxgasmia rD, rA, rB + evdotp4hxgasmfa rD, rA, rB + evdotpbaumia rD, rA, rB + evdotpbasmia rD, rA, rB + evdotpbasumia rD, rA, rB + evdotp4hxgssmia rD, rA, rB + evdotp4hxgssmfa rD, rA, rB + evdotp4hgaumiaa rD, rA, rB + evdotp4hgasmiaa rD, rA, rB + evdotp4hgasumiaa rD, rA, rB + evdotp4hgasmfaa rD, rA, rB + evdotp4hgssmiaa rD, rA, rB + evdotp4hgssmfaa rD, rA, rB + evdotp4hxgasmiaa rD, rA, rB + evdotp4hxgasmfaa rD, rA, rB + evdotpbaumiaaw rD, rA, rB + evdotpbasmiaaw rD, rA, rB + evdotpbasumiaaw rD, rA, rB + evdotp4hxgssmiaa rD, rA, rB + evdotp4hxgssmfaa rD, rA, rB + evdotpwausi rD, rA, rB + evdotpwassi rD, rA, rB + evdotpwasusi rD, rA, rB + evdotpwaumi rD, rA, rB + evdotpwasmi rD, rA, rB + evdotpwasumi rD, rA, rB + evdotpwssmi rD, rA, rB + evdotpwausiaa3 rD, rA, rB + evdotpwassiaa3 rD, rA, rB + evdotpwasusiaa3 rD, rA, rB + evdotpwsssiaa3 rD, rA, rB + evdotpwaumiaa3 rD, rA, rB + evdotpwasmiaa3 rD, rA, rB + evdotpwasumiaa3 rD, rA, rB + evdotpwssmiaa3 rD, rA, rB + evdotpwausia rD, rA, rB + evdotpwassia rD, rA, rB + evdotpwasusia rD, rA, rB + evdotpwaumia rD, rA, rB + evdotpwasmia rD, rA, rB + evdotpwasumia rD, rA, rB + evdotpwssmia rD, rA, rB + evdotpwausiaa rD, rA, rB + evdotpwassiaa rD, rA, rB + evdotpwasusiaa rD, rA, rB + evdotpwsssiaa rD, rA, rB + evdotpwaumiaa rD, rA, rB + evdotpwasmiaa rD, rA, rB + evdotpwasumiaa rD, rA, rB + evdotpwssmiaa rD, rA, rB + evaddib rD, rB, UIMM + evaddih rD, rB, UIMM + evsubifh rD, UIMM, rB + evsubifb rD, UIMM, rB + evabsb rD, rA + evabsh rD, rA + evabsd rD, rA + evabss rD, rA + evabsbs rD, rA + evabshs rD, rA + evabsds rD, rA + evnegwo rD, rA + evnegb rD, rA + evnegbo rD, rA + evnegh rD, rA + evnegho rD, rA + evnegd rD, rA + evnegs rD, rA + evnegwos rD, rA + evnegbs rD, rA + evnegbos rD, rA + evneghs rD, rA + evneghos rD, rA + evnegds rD, rA + evextzb rD, rA + evextsbh rD, rA + evextsw rD, rA + evrndwh rD, rA + evrndhb rD, rA + evrnddw rD, rA + evrndwhus rD, rA + evrndwhss rD, rA + evrndhbus rD, rA + evrndhbss rD, rA + evrnddwus rD, rA + evrnddwss rD, rA + evrndwnh rD, rA + evrndhnb rD, rA + evrnddnw rD, rA + evrndwnhus rD, rA + evrndwnhss rD, rA + evrndhnbus rD, rA + evrndhnbss rD, rA + evrnddnwus rD, rA + evrnddnwss rD, rA + evcntlzh rD, rA + evcntlsh rD, rA + evpopcntb rD, rA + circinc rD, rA, rB + evunpkhibui rD, rA + evunpkhibsi rD, rA + evunpkhihui rD, rA + evunpkhihsi rD, rA + evunpklobui rD, rA + evunpklobsi rD, rA + evunpklohui rD, rA + evunpklohsi rD, rA + evunpklohf rD, rA + evunpkhihf rD, rA + evunpklowgsf rD, rA + evunpkhiwgsf rD, rA + evsatsduw rD, rA + evsatsdsw rD, rA + evsatshub rD, rA + evsatshsb rD, rA + evsatuwuh rD, rA + evsatswsh rD, rA + evsatswuh rD, rA + evsatuhub rD, rA + evsatuduw rD, rA + evsatuwsw rD, rA + evsatshuh rD, rA + evsatuhsh rD, rA + evsatswuw rD, rA + evsatswgsdf rD, rA + evsatsbub rD, rA + evsatubsb rD, rA + evmaxhpuw rD, rA + evmaxhpsw rD, rA + evmaxbpuh rD, rA + evmaxbpsh rD, rA + evmaxwpud rD, rA + evmaxwpsd rD, rA + evminhpuw rD, rA + evminhpsw rD, rA + evminbpuh rD, rA + evminbpsh rD, rA + evminwpud rD, rA + evminwpsd rD, rA + evmaxmagws rD, rA, rB + evsl rD, rA, rB + evsli rD, rA, UIMM + evsplatie rD, SIMM + evsplatib rD, SIMM + evsplatibe rD, SIMM + evsplatih rD, SIMM + evsplatihe rD, SIMM + evsplatid rD, SIMM + evsplatia rD, SIMM + evsplatiea rD, SIMM + evsplatiba rD, SIMM + evsplatibea rD, SIMM + evsplatiha rD, SIMM + evsplatihea rD, SIMM + evsplatida rD, SIMM + evsplatfio rD, SIMM + evsplatfib rD, SIMM + evsplatfibo rD, SIMM + evsplatfih rD, SIMM + evsplatfiho rD, SIMM + evsplatfid rD, SIMM + evsplatfia rD, SIMM + evsplatfioa rD, SIMM + evsplatfiba rD, SIMM + evsplatfiboa rD, SIMM + evsplatfiha rD, SIMM + evsplatfihoa rD, SIMM + evsplatfida rD, SIMM + evcmpgtdu crD, rA, rB + evcmpgtds crD, rA, rB + evcmpltdu crD, rA, rB + evcmpltds crD, rA, rB + evcmpeqd crD, rA, rB + evswapbhilo rD, rA, rB + evswapblohi rD, rA, rB + evswaphhilo rD, rA, rB + evswaphlohi rD, rA, rB + evswaphe rD, rA, rB + evswaphhi rD, rA, rB + evswaphlo rD, rA, rB + evswapho rD, rA, rB + evinsb rD, rA, Ddd, bbb + evxtrb rD, rA, Ddd, bbb + evsplath rD, rA, hh + evsplatb rD, rA, bbb + evinsh rD, rA, dd, hh + evclrbe rD, rA, mask + evclrbo rD, rA, mask + evclrh rD, rA, mask + evxtrh rD, rA, dd, hh + evselbitm0 rD, rA, rB + evselbitm1 rD, rA, rB + evselbit rD, rA, rB + evperm rD, rA, rB + evperm2 rD, rA, rB + evperm3 rD, rA, rB + evxtrd rD, rA, rB, offset + evsrbu rD, rA, rB + evsrbs rD, rA, rB + evsrbiu rD, rA, UIMM_LT8 + evsrbis rD, rA, UIMM_LT8 + evslb rD, rA, rB + evrlb rD, rA, rB + evslbi rD, rA, UIMM_LT8 + evrlbi rD, rA, UIMM_LT8 + evsrhu rD, rA, rB + evsrhs rD, rA, rB + evsrhiu rD, rA, UIMM_LT16 + evsrhis rD, rA, UIMM_LT16 + evslh rD, rA, rB + evrlh rD, rA, rB + evslhi rD, rA, UIMM_LT16 + evrlhi rD, rA, UIMM_LT16 + evsru rD, rA, rB + evsrs rD, rA, rB + evsriu rD, rA, UIMM + evsris rD, rA, UIMM + evlvsl rD, rA, rB + evlvsr rD, rA, rB + evsroiu rD, rA, nnn + evsrois rD, rA, nnn + evsloi rD, rA, nnn + evfssqrt rD, rA + evfscfh rD, rB + evfscth rD, rB + evfsmax rD, rA, rB + evfsmin rD, rA, rB + evfsaddsub rD, rA, rB + evfssubadd rD, rA, rB + evfssum rD, rA, rB + evfsdiff rD, rA, rB + evfssumdiff rD, rA, rB + evfsdiffsum rD, rA, rB + evfsaddx rD, rA, rB + evfssubx rD, rA, rB + evfsaddsubx rD, rA, rB + evfssubaddx rD, rA, rB + evfsmulx rD, rA, rB + evfsmule rD, rA, rB + evfsmulo rD, rA, rB + evldbx rD, rA, rB + evldb rD, UIMM_8 (rA) + evlhhsplathx rD, rA, rB + evlhhsplath rD, UIMM_2 (rA) + evlwbsplatwx rD, rA, rB + evlwbsplatw rD, UIMM_4 (rA) + evlwhsplatwx rD, rA, rB + evlwhsplatw rD, UIMM_4 (rA) + evlbbsplatbx rD, rA, rB + evlbbsplatb rD, UIMM_1 (rA) + evstdbx rS, rA, rB + evstdb rS, UIMM_8 (rA) + evlwbex rD, rA, rB + evlwbe rD, UIMM_4 (rA) + evlwboux rD, rA, rB + evlwbou rD, UIMM_4 (rA) + evlwbosx rD, rA, rB + evlwbos rD, UIMM_4 (rA) + evstwbex rS, rA, rB + evstwbe rS, UIMM_4 (rA) + evstwbox rS, rA, rB + evstwbo rS, UIMM_4 (rA) + evstwbx rS, rA, rB + evstwb rS, UIMM_4 (rA) + evsthbx rS, rA, rB + evsthb rS, UIMM_2 (rA) + evlddmx rD, rA, rB + evlddu rD, UIMM_8 (rA) + evldwmx rD, rA, rB + evldwu rD, UIMM_8 (rA) + evldhmx rD, rA, rB + evldhu rD, UIMM_8 (rA) + evldbmx rD, rA, rB + evldbu rD, UIMM_8 (rA) + evlhhesplatmx rD, rA, rB + evlhhesplatu rD, UIMM_2 (rA) + evlhhsplathmx rD, rA, rB + evlhhsplathu rD, UIMM_2 (rA) + evlhhousplatmx rD, rA, rB + evlhhousplatu rD, UIMM_2 (rA) + evlhhossplatmx rD, rA, rB + evlhhossplatu rD, UIMM_2 (rA) + evlwhemx rD, rA, rB + evlwheu rD, UIMM_4 (rA) + evlwbsplatwmx rD, rA, rB + evlwbsplatwu rD, UIMM_4 (rA) + evlwhoumx rD, rA, rB + evlwhouu rD, UIMM_4 (rA) + evlwhosmx rD, rA, rB + evlwhosu rD, UIMM_4 (rA) + evlwwsplatmx rD, rA, rB + evlwwsplatu rD, UIMM_4 (rA) + evlwhsplatwmx rD, rA, rB + evlwhsplatwu rD, UIMM_4 (rA) + evlwhsplatmx rD, rA, rB + evlwhsplatu rD, UIMM_4 (rA) + evlbbsplatbmx rD, rA, rB + evlbbsplatbu rD, UIMM_1 (rA) + evstddmx rS, rA, rB + evstddu rS, UIMM_8 (rA) + evstdwmx rS, rA, rB + evstdwu rS, UIMM_8 (rA) + evstdhmx rS, rA, rB + evstdhu rS, UIMM_8 (rA) + evstdbmx rS, rA, rB + evstdbu rS, UIMM_8 (rA) + evlwbemx rD, rA, rB + evlwbeu rD, UIMM_4 (rA) + evlwboumx rD, rA, rB + evlwbouu rD, UIMM_4 (rA) + evlwbosmx rD, rA, rB + evlwbosu rD, UIMM_4 (rA) + evstwhemx rS, rA, rB + evstwheu rS, UIMM_4 (rA) + evstwbemx rS, rA, rB + evstwbeu rS, UIMM_4 (rA) + evstwhomx rS, rA, rB + evstwhou rS, UIMM_4 (rA) + evstwbomx rS, rA, rB + evstwbou rS, UIMM_4 (rA) + evstwwemx rS, rA, rB + evstwweu rS, UIMM_4 (rA) + evstwbmx rS, rA, rB + evstwbu rS, UIMM_4 (rA) + evstwwomx rS, rA, rB + evstwwou rS, UIMM_4 (rA) + evsthbmx rS, rA, rB + evsthbu rS, UIMM_2 (rA) + evmhusi rD, rA, rB + evmhssi rD, rA, rB + evmhsusi rD, rA, rB + evmhssf rD, rA, rB + evmhumi rD, rA, rB + evmhssfr rD, rA, rB + evmhesumi rD, rA, rB + evmhosumi rD, rA, rB + evmbeumi rD, rA, rB + evmbesmi rD, rA, rB + evmbesumi rD, rA, rB + evmboumi rD, rA, rB + evmbosmi rD, rA, rB + evmbosumi rD, rA, rB + evmhesumia rD, rA, rB + evmhosumia rD, rA, rB + evmbeumia rD, rA, rB + evmbesmia rD, rA, rB + evmbesumia rD, rA, rB + evmboumia rD, rA, rB + evmbosmia rD, rA, rB + evmbosumia rD, rA, rB + evmwusiw rD, rA, rB + evmwssiw rD, rA, rB + evmwhssfr rD, rA, rB + evmwehgsmfr rD, rA, rB + evmwehgsmf rD, rA, rB + evmwohgsmfr rD, rA, rB + evmwohgsmf rD, rA, rB + evmwhssfra rD, rA, rB + evmwehgsmfra rD, rA, rB + evmwehgsmfa rD, rA, rB + evmwohgsmfra rD, rA, rB + evmwohgsmfa rD, rA, rB + evaddusiaa rD, rA + evaddssiaa rD, rA + evsubfusiaa rD, rA + evsubfssiaa rD, rA + evaddsmiaa rD, rA + evsubfsmiaa rD, rA + evaddh rD, rA, rB + evaddhss rD, rA, rB + evsubfh rD, rA, rB + evsubfhss rD, rA, rB + evaddhx rD, rA, rB + evaddhxss rD, rA, rB + evsubfhx rD, rA, rB + evsubfhxss rD, rA, rB + evaddd rD, rA, rB + evadddss rD, rA, rB + evsubfd rD, rA, rB + evsubfdss rD, rA, rB + evaddb rD, rA, rB + evaddbss rD, rA, rB + evsubfb rD, rA, rB + evsubfbss rD, rA, rB + evaddsubfh rD, rA, rB + evaddsubfhss rD, rA, rB + evsubfaddh rD, rA, rB + evsubfaddhss rD, rA, rB + evaddsubfhx rD, rA, rB + evaddsubfhxss rD, rA, rB + evsubfaddhx rD, rA, rB + evsubfaddhxss rD, rA, rB + evadddus rD, rA, rB + evaddbus rD, rA, rB + evsubfdus rD, rA, rB + evsubfbus rD, rA, rB + evaddwus rD, rA, rB + evaddwxus rD, rA, rB + evsubfwus rD, rA, rB + evsubfwxus rD, rA, rB + evadd2subf2h rD, rA, rB + evadd2subf2hss rD, rA, rB + evsubf2add2h rD, rA, rB + evsubf2add2hss rD, rA, rB + evaddhus rD, rA, rB + evaddhxus rD, rA, rB + evsubfhus rD, rA, rB + evsubfhxus rD, rA, rB + evaddwss rD, rA, rB + evsubfwss rD, rA, rB + evaddwx rD, rA, rB + evaddwxss rD, rA, rB + evsubfwx rD, rA, rB + evsubfwxss rD, rA, rB + evaddsubfw rD, rA, rB + evaddsubfwss rD, rA, rB + evsubfaddw rD, rA, rB + evsubfaddwss rD, rA, rB + evaddsubfwx rD, rA, rB + evaddsubfwxss rD, rA, rB + evsubfaddwx rD, rA, rB + evsubfaddwxss rD, rA, rB + evmar rD + evsumwu rD, rA + evsumws rD, rA + evsum4bu rD, rA + evsum4bs rD, rA + evsum2hu rD, rA + evsum2hs rD, rA + evdiff2his rD, rA + evsum2his rD, rA + evsumwua rD, rA + evsumwsa rD, rA + evsum4bua rD, rA + evsum4bsa rD, rA + evsum2hua rD, rA + evsum2hsa rD, rA + evdiff2hisa rD, rA + evsum2hisa rD, rA + evsumwuaa rD, rA + evsumwsaa rD, rA + evsum4buaaw rD, rA + evsum4bsaaw rD, rA + evsum2huaaw rD, rA + evsum2hsaaw rD, rA + evdiff2hisaaw rD, rA + evsum2hisaaw rD, rA + evdivwsf rD, rA, rB + evdivwuf rD, rA, rB + evdivs rD, rA, rB + evdivu rD, rA, rB + evaddwegsi rD, rA, rB + evaddwegsf rD, rA, rB + evsubfwegsi rD, rA, rB + evsubfwegsf rD, rA, rB + evaddwogsi rD, rA, rB + evaddwogsf rD, rA, rB + evsubfwogsi rD, rA, rB + evsubfwogsf rD, rA, rB + evaddhhiuw rD, rA, rB + evaddhhisw rD, rA, rB + evsubfhhiuw rD, rA, rB + evsubfhhisw rD, rA, rB + evaddhlouw rD, rA, rB + evaddhlosw rD, rA, rB + evsubfhlouw rD, rA, rB + evsubfhlosw rD, rA, rB + evmhesusiaaw rD, rA, rB + evmhosusiaaw rD, rA, rB + evmhesumiaaw rD, rA, rB + evmhosumiaaw rD, rA, rB + evmbeusiaah rD, rA, rB + evmbessiaah rD, rA, rB + evmbesusiaah rD, rA, rB + evmbousiaah rD, rA, rB + evmbossiaah rD, rA, rB + evmbosusiaah rD, rA, rB + evmbeumiaah rD, rA, rB + evmbesmiaah rD, rA, rB + evmbesumiaah rD, rA, rB + evmboumiaah rD, rA, rB + evmbosmiaah rD, rA, rB + evmbosumiaah rD, rA, rB + evmwlusiaaw3 rD, rA, rB + evmwlssiaaw3 rD, rA, rB + evmwhssfraaw3 rD, rA, rB + evmwhssfaaw3 rD, rA, rB + evmwhssfraaw rD, rA, rB + evmwhssfaaw rD, rA, rB + evmwlumiaaw3 rD, rA, rB + evmwlsmiaaw3 rD, rA, rB + evmwusiaa rD, rA, rB + evmwssiaa rD, rA, rB + evmwehgsmfraa rD, rA, rB + evmwehgsmfaa rD, rA, rB + evmwohgsmfraa rD, rA, rB + evmwohgsmfaa rD, rA, rB + evmhesusianw rD, rA, rB + evmhosusianw rD, rA, rB + evmhesumianw rD, rA, rB + evmhosumianw rD, rA, rB + evmbeusianh rD, rA, rB + evmbessianh rD, rA, rB + evmbesusianh rD, rA, rB + evmbousianh rD, rA, rB + evmbossianh rD, rA, rB + evmbosusianh rD, rA, rB + evmbeumianh rD, rA, rB + evmbesmianh rD, rA, rB + evmbesumianh rD, rA, rB + evmboumianh rD, rA, rB + evmbosmianh rD, rA, rB + evmbosumianh rD, rA, rB + evmwlusianw3 rD, rA, rB + evmwlssianw3 rD, rA, rB + evmwhssfranw3 rD, rA, rB + evmwhssfanw3 rD, rA, rB + evmwhssfranw rD, rA, rB + evmwhssfanw rD, rA, rB + evmwlumianw3 rD, rA, rB + evmwlsmianw3 rD, rA, rB + evmwusian rD, rA, rB + evmwssian rD, rA, rB + evmwehgsmfran rD, rA, rB + evmwehgsmfan rD, rA, rB + evmwohgsmfran rD, rA, rB + evmwohgsmfan rD, rA, rB + evseteqb rD, rA, rB + evseteqb. rD, rA, rB + evseteqh rD, rA, rB + evseteqh. rD, rA, rB + evseteqw rD, rA, rB + evseteqw. rD, rA, rB + evsetgthu rD, rA, rB + evsetgthu. rD, rA, rB + evsetgths rD, rA, rB + evsetgths. rD, rA, rB + evsetgtwu rD, rA, rB + evsetgtwu. rD, rA, rB + evsetgtws rD, rA, rB + evsetgtws. rD, rA, rB + evsetgtbu rD, rA, rB + evsetgtbu. rD, rA, rB + evsetgtbs rD, rA, rB + evsetgtbs. rD, rA, rB + evsetltbu rD, rA, rB + evsetltbu. rD, rA, rB + evsetltbs rD, rA, rB + evsetltbs. rD, rA, rB + evsetlthu rD, rA, rB + evsetlthu. rD, rA, rB + evsetlths rD, rA, rB + evsetlths. rD, rA, rB + evsetltwu rD, rA, rB + evsetltwu. rD, rA, rB + evsetltws rD, rA, rB + evsetltws. rD, rA, rB + evsaduw rD, rA, rB + evsadsw rD, rA, rB + evsad4ub rD, rA, rB + evsad4sb rD, rA, rB + evsad2uh rD, rA, rB + evsad2sh rD, rA, rB + evsaduwa rD, rA, rB + evsadswa rD, rA, rB + evsad4uba rD, rA, rB + evsad4sba rD, rA, rB + evsad2uha rD, rA, rB + evsad2sha rD, rA, rB + evabsdifuw rD, rA, rB + evabsdifsw rD, rA, rB + evabsdifub rD, rA, rB + evabsdifsb rD, rA, rB + evabsdifuh rD, rA, rB + evabsdifsh rD, rA, rB + evsaduwaa rD, rA, rB + evsadswaa rD, rA, rB + evsad4ubaaw rD, rA, rB + evsad4sbaaw rD, rA, rB + evsad2uhaaw rD, rA, rB + evsad2shaaw rD, rA, rB + evpkshubs rD, rA, rB + evpkshsbs rD, rA, rB + evpkswuhs rD, rA, rB + evpkswshs rD, rA, rB + evpkuhubs rD, rA, rB + evpkuwuhs rD, rA, rB + evpkswshilvs rD, rA, rB + evpkswgshefrs rD, rA, rB + evpkswshfrs rD, rA, rB + evpkswshilvfrs rD, rA, rB + evpksdswfrs rD, rA, rB + evpksdshefrs rD, rA, rB + evpkuduws rD, rA, rB + evpksdsws rD, rA, rB + evpkswgswfrs rD, rA, rB + evilveh rD, rA, rB + evilveoh rD, rA, rB + evilvhih rD, rA, rB + evilvhiloh rD, rA, rB + evilvloh rD, rA, rB + evilvlohih rD, rA, rB + evilvoeh rD, rA, rB + evilvoh rD, rA, rB + evdlveb rD, rA, rB + evdlveh rD, rA, rB + evdlveob rD, rA, rB + evdlveoh rD, rA, rB + evdlvob rD, rA, rB + evdlvoh rD, rA, rB + evdlvoeb rD, rA, rB + evdlvoeh rD, rA, rB + evmaxbu rD, rA, rB + evmaxbs rD, rA, rB + evmaxhu rD, rA, rB + evmaxhs rD, rA, rB + evmaxwu rD, rA, rB + evmaxws rD, rA, rB + evmaxdu rD, rA, rB + evmaxds rD, rA, rB + evminbu rD, rA, rB + evminbs rD, rA, rB + evminhu rD, rA, rB + evminhs rD, rA, rB + evminwu rD, rA, rB + evminws rD, rA, rB + evmindu rD, rA, rB + evminds rD, rA, rB + evavgwu rD, rA, rB + evavgws rD, rA, rB + evavgbu rD, rA, rB + evavgbs rD, rA, rB + evavghu rD, rA, rB + evavghs rD, rA, rB + evavgdu rD, rA, rB + evavgds rD, rA, rB + evavgwur rD, rA, rB + evavgwsr rD, rA, rB + evavgbur rD, rA, rB + evavgbsr rD, rA, rB + evavghur rD, rA, rB + evavghsr rD, rA, rB + evavgdur rD, rA, rB + evavgdsr rD, rA, rB + +;#SPE2 mapped by macro + evdotphsssi rD, rA, rB + evdotphsssia rD, rA, rB + evdotpwsssi rD, rA, rB + evdotpwsssia rD, rA, rB diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.d b/gas/testsuite/gas/ppc/spe_ambiguous.d new file mode 100644 index 0000000..cdfb005 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe_ambiguous.d @@ -0,0 +1,15 @@ +#as: -a32 -mvle +#objdump: -d -Mspe +#name: Validate SPE instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 12 04 evsubfw r0,r1,r2 + 4: 10 01 12 04 evsubw r0,r2,r1 + 8: 10 1f 12 06 evsubifw r0,31,r2 + c: 10 1f 12 06 evsubiw r0,r2,31 + 10: 10 01 12 18 evnor r0,r1,r2 + 14: 10 01 0a 18 evnot r0,r1 diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.s b/gas/testsuite/gas/ppc/spe_ambiguous.s new file mode 100644 index 0000000..b60e02b --- /dev/null +++ b/gas/testsuite/gas/ppc/spe_ambiguous.s @@ -0,0 +1,21 @@ +# PA SPE instructions + .section ".text" + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ rT,0 + .equ UIMM, 31 + .equ UIMM_2, 2 + .equ UIMM_4, 4 + .equ UIMM_8, 8 + .equ SIMM, -16 + .equ crD, 0 + .equ crS, 0 + + evsubfw rS, rA, rB + evsubw rS, rB, rA + evsubifw rS, UIMM, rB + evsubiw rS, rB, UIMM + evnor rS, rA, rB + evnot rS, rA diff --git a/include/ChangeLog b/include/ChangeLog index db500dc..78782db 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,13 @@ +2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com> + Edmar Wienskoski <edmar.wienskoski@nxp.com> + + * opcode/ppc.h: + (spe2_opcodes, spe2_num_opcodes): New. + (PPC_OPCODE_SPE2): New define. + (PPC_OPCODE_EFS2): Likewise. + (SPE2_XOP): Likewise. + (SPE2_XOP_TO_SEG): Likewise. + 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com> Edmar Wienskoski <edmar.wienskoski@nxp.com> diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 21b1221..5274cae 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -70,6 +70,8 @@ extern const struct powerpc_opcode powerpc_opcodes[]; extern const int powerpc_num_opcodes; extern const struct powerpc_opcode vle_opcodes[]; extern const int vle_num_opcodes; +extern const struct powerpc_opcode spe2_opcodes[]; +extern const int spe2_num_opcodes; /* Values defined for the flags field of a struct powerpc_opcode. */ @@ -218,6 +220,12 @@ extern const int vle_num_opcodes; /* Opcode is supported by PowerPC LSP */ #define PPC_OPCODE_LSP 0x80000000000ull +/* Opcode is only supported by Freescale SPE2 APU. */ +#define PPC_OPCODE_SPE2 0x100000000000ull + +/* Opcode is supported by EFS2. */ +#define PPC_OPCODE_EFS2 0x200000000000ull + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -229,6 +237,12 @@ extern const int vle_num_opcodes; /* A macro to convert a VLE opcode to a VLE opcode segment. */ #define VLE_OP_TO_SEG(i) ((i) >> 1) + +/* A macro to extract the extended opcode from a SPE2 instruction. */ +#define SPE2_XOP(i) ((i) & 0x7ff) + +/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */ +#define SPE2_XOP_TO_SEG(i) ((i) >> 7) /* The operands table is an array of struct powerpc_operand. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e49400a..e252089 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,63 @@ +2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com> + Edmar Wienskoski <edmar.wienskoski@nxp.com> + + * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and + PPC_OPCODE_EFS2 flag to "e200z4" entry. + New entries efs2 and spe2. + Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. + (SPE2_OPCD_SEGS): New macro. + (spe2_opcd_indices): New. + (disassemble_init_powerpc): Handle SPE2 opcodes. + (lookup_spe2): New function. + (print_insn_powerpc): call lookup_spe2. + * ppc-opc.c (insert_evuimm1_ex0): New function. + (extract_evuimm1_ex0): Likewise. + (insert_evuimm_lt8): Likewise. + (extract_evuimm_lt8): Likewise. + (insert_off_spe2): Likewise. + (extract_off_spe2): Likewise. + (insert_Ddd): Likewise. + (extract_Ddd): Likewise. + (DD): New operand. + (EVUIMM_LT8): Likewise. + (EVUIMM_LT16): Adjust. + (MMMM): New operand. + (EVUIMM_1): Likewise. + (EVUIMM_1_EX0): Likewise. + (EVUIMM_2): Adjust. + (NNN): New operand. + (VX_OFF_SPE2): Likewise. + (BBB): Likewise. + (DDD): Likewise. + (VX_MASK_DDD): New mask. + (HH): New operand. + (VX_RA_CONST): New macro. + (VX_RA_CONST_MASK): Likewise. + (VX_RB_CONST): Likewise. + (VX_RB_CONST_MASK): Likewise. + (VX_OFF_SPE2_MASK): Likewise. + (VX_SPE_CRFD): Likewise. + (VX_SPE_CRFD_MASK VX): Likewise. + (VX_SPE2_CLR): Likewise. + (VX_SPE2_CLR_MASK): Likewise. + (VX_SPE2_SPLATB): Likewise. + (VX_SPE2_SPLATB_MASK): Likewise. + (VX_SPE2_OCTET): Likewise. + (VX_SPE2_OCTET_MASK): Likewise. + (VX_SPE2_DDHH): Likewise. + (VX_SPE2_DDHH_MASK): Likewise. + (VX_SPE2_HH): Likewise. + (VX_SPE2_HH_MASK): Likewise. + (VX_SPE2_EVMAR): Likewise. + (VX_SPE2_EVMAR_MASK): Likewise. + (PPCSPE2): Likewise. + (PPCEFS2): Likewise. + (vle_opcodes): Add EFS2 and some missing SPE opcodes. + (powerpc_macros): Map old SPE instructions have new names + with the same opcodes. Add SPE2 instructions which just are + mapped to SPE2. + (spe2_opcodes): Add SPE2 opcodes. + 2017-08-23 Alan Modra <amodra@gmail.com> * ppc-opc.c: Formatting and comment fixes. Move insert and diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index d75e59d..0e2e185 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -120,7 +120,8 @@ struct ppc_mopt ppc_opts[] = { { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI - | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4), + | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4 + | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP), 0 }, { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300, 0 }, @@ -156,6 +157,8 @@ struct ppc_mopt ppc_opts[] = { 0 }, { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS, 0 }, + { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2, + 0 }, { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, 0 }, { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 @@ -227,13 +230,15 @@ struct ppc_mopt ppc_opts[] = { PPC_OPCODE_RAW }, { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS, PPC_OPCODE_SPE }, + { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE, + PPC_OPCODE_SPE2 }, { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), 0 }, { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI - | PPC_OPCODE_E500 | PPC_OPCODE_LSP), + | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2), PPC_OPCODE_VLE }, { "vsx", PPC_OPCODE_PPC, PPC_OPCODE_VSX }, @@ -362,6 +367,8 @@ powerpc_init_dialect (struct disassemble_info *info) static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; #define VLE_OPCD_SEGS 32 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; +#define SPE2_OPCD_SEGS 13 +static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1]; /* Calculate opcode table indices to speed up disassembly, and init dialect. */ @@ -409,6 +416,24 @@ disassemble_init_powerpc (struct disassemble_info *info) } } + /* SPE2 opcodes */ + i = spe2_num_opcodes; + while (--i >= 0) + { + unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode); + unsigned seg = SPE2_XOP_TO_SEG (xop); + + spe2_opcd_indices[seg] = i; + } + + last = spe2_num_opcodes; + for (i = SPE2_OPCD_SEGS; i > 1; --i) + { + if (spe2_opcd_indices[i] == 0) + spe2_opcd_indices[i] = last; + last = spe2_opcd_indices[i]; + } + if (info->arch == bfd_arch_powerpc) powerpc_init_dialect (info); } @@ -596,6 +621,58 @@ lookup_vle (unsigned long insn) return NULL; } +/* Find a match for INSN in the SPE2 opcode table. */ + +static const struct powerpc_opcode * +lookup_spe2 (unsigned long insn) +{ + const struct powerpc_opcode *opcode, *opcode_end; + unsigned op, xop, seg; + + op = PPC_OP (insn); + if (op != 0x4) + { + /* This is not SPE2 insn. + * All SPE2 instructions have OP=4 and differs by XOP */ + return NULL; + } + xop = SPE2_XOP (insn); + seg = SPE2_XOP_TO_SEG (xop); + + /* Find the first match in the opcode table for this major opcode. */ + opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1]; + for (opcode = spe2_opcodes + spe2_opcd_indices[seg]; + opcode < opcode_end; + ++opcode) + { + unsigned long table_opcd = opcode->opcode; + unsigned long table_mask = opcode->mask; + unsigned long insn2; + const unsigned char *opindex; + const struct powerpc_operand *operand; + int invalid; + + insn2 = insn; + if ((insn2 & table_mask) != table_opcd) + continue; + + /* Check validity of operands. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; ++opindex) + { + operand = powerpc_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); + } + if (invalid) + continue; + + return opcode; + } + + return NULL; +} + /* Print a PowerPC or POWER instruction. */ static int @@ -646,6 +723,8 @@ print_insn_powerpc (bfd_vma memaddr, if (opcode != NULL) insn_is_short = PPC_OP_SE_VLE(opcode->mask); } + if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0) + opcode = lookup_spe2 (insn); if (opcode == NULL) opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY); if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index b6ab79f..5edb1ad 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1478,6 +1478,33 @@ extract_vleil (unsigned long insn, } static unsigned long +insert_evuimm1_ex0 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value > 0 && value <= 0x1f) + return insn | ((value & 0x1f) << 11); + else + { + *errmsg = _("UIMM = 00000 is illegal"); + return 0; + } +} + +static long +extract_evuimm1_ex0 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value = ((insn >> 11) & 0x1f); + if (value == 0) + *invalid = 1; + + return value; +} + +static unsigned long insert_evuimm2_ex0 (unsigned long insn, long value, ppc_cpu_t dialect ATTRIBUTE_UNUSED, @@ -1559,6 +1586,33 @@ extract_evuimm8_ex0 (unsigned long insn, } static unsigned long +insert_evuimm_lt8 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value >= 0 && value <= 7) + return insn | ((value & 0x7) << 11); + else + { + *errmsg = _("UIMM values >7 are illegal"); + return 0; + } +} + +static long +extract_evuimm_lt8 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value = ((insn >> 11) & 0x1f); + if (value > 7) + *invalid = 1; + + return value; +} + +static unsigned long insert_evuimm_lt16 (unsigned long insn, long value, ppc_cpu_t dialect ATTRIBUTE_UNUSED, @@ -1638,6 +1692,56 @@ extract_off_lsp (unsigned long insn, return value; } + +static unsigned long +insert_off_spe2 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value > 0 && value <= 0x7) + return insn | (value & 0x7); + else + { + *errmsg = _("invalid offset"); + return 0; + } +} + +static long +extract_off_spe2 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value = (insn & 0x7); + if (value == 0) + *invalid = 1; + + return value; +} + +static unsigned long +insert_Ddd (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value >= 0 && value <= 0x7) + return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2); + else + { + *errmsg = _("invalid Ddd value"); + return 0; + } +} + +static long +extract_Ddd (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4); +} /* The operands table. @@ -1750,6 +1854,7 @@ const struct powerpc_operand powerpc_operands[] = /* The RM field in an X form instruction. */ #define RM BOE + 1 +#define DD RM { 0x3, 11, NULL, NULL, 0 }, #define BH RM + 1 @@ -2154,7 +2259,10 @@ const struct powerpc_operand powerpc_operands[] = #define FC SH { 0x1f, 11, NULL, NULL, 0 }, -#define EVUIMM_LT16 SH + 1 +#define EVUIMM_LT8 SH + 1 + { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 }, + +#define EVUIMM_LT16 EVUIMM_LT8 + 1 { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 }, /* The SI field in a HTM X form instruction. */ @@ -2294,6 +2402,7 @@ const struct powerpc_operand powerpc_operands[] = /* The SIX field in a VX form instruction. */ #define SIX UIM6 + 1 +#define MMMM SIX { 0xf, 11, NULL, NULL, 0 }, /* The PS field in a VX form instruction. */ @@ -2305,7 +2414,13 @@ const struct powerpc_operand powerpc_operands[] = { 0xf, 6, NULL, NULL, 0 }, /* The other UIMM field in a half word EVX form instruction. */ -#define EVUIMM_2 SHB + 1 +#define EVUIMM_1 SHB + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS }, + +#define EVUIMM_1_EX0 EVUIMM_1 + 1 + { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS }, + +#define EVUIMM_2 EVUIMM_1_EX0 + 1 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, #define EVUIMM_2_EX0 EVUIMM_2 + 1 @@ -2328,6 +2443,8 @@ const struct powerpc_operand powerpc_operands[] = /* The WS or DRM field in an X form instruction. */ #define WS EVUIMM_8_EX0 + 1 #define DRM WS + /* The NNN field in a VX form instruction for SPE2 */ +#define NNN WS { 0x7, 11, NULL, NULL, 0 }, /* PowerPC paired singles extensions. */ @@ -2498,6 +2615,19 @@ const struct powerpc_operand powerpc_operands[] = #define VX_OFF IMM8 + 1 { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 }, + +#define VX_OFF_SPE2 VX_OFF + 1 + { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 }, + +#define BBB VX_OFF_SPE2 + 1 + { 0x7, 13, NULL, NULL, 0 }, + +#define DDD BBB + 1 +#define VX_MASK_DDD (VX_MASK & ~0x1) + { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, + +#define HH DDD + 1 + { 0x3, 13, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -2793,6 +2923,66 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define VX_LSP_MASK VX_LSP(0x3f, 0xffff) #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc) +/* Additional format of VX SPE2 form instruction. */ +#define VX_RA_CONST(op, xop, bits11_15) \ + (OP (op) \ + | (((unsigned long)(bits11_15) & 0x1f) << 16) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f) + +#define VX_RB_CONST(op, xop, bits16_20) \ + (OP (op) \ + | (((unsigned long)(bits16_20) & 0x1f) << 11) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f) + +#define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8) + +#define VX_SPE_CRFD(op, xop, bits9_10) \ + (OP (op) \ + | (((unsigned long)(bits9_10) & 0x3) << 21) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3) + +#define VX_SPE2_CLR(op, xop, bit16) \ + (OP (op) \ + | (((unsigned long)(bit16) & 0x1) << 15) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1) + +#define VX_SPE2_SPLATB(op, xop, bits19_20) \ + (OP (op) \ + | (((unsigned long)(bits19_20) & 0x3) << 11) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3) + +#define VX_SPE2_OCTET(op, xop, bits16_17) \ + (OP (op) \ + | (((unsigned long)(bits16_17) & 0x3) << 14) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7) + +#define VX_SPE2_DDHH(op, xop, bit16) \ + (OP (op) \ + | (((unsigned long)(bit16) & 0x1) << 15) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1) + +#define VX_SPE2_HH(op, xop, bit16, bits19_20) \ + (OP (op) \ + | (((unsigned long)(bit16) & 0x1) << 15) \ + | (((unsigned long)(bits19_20) & 0x3) << 11) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3) + +#define VX_SPE2_EVMAR(op, xop) \ + (OP (op) \ + | ((unsigned long)(0x1) << 11) \ + | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_EVMAR_MASK \ + (VX_SPE2_EVMAR(0x3f, 0x7ff) \ + | ((unsigned long)(0x1) << 11)) + /* A VX_MASK with the VA field fixed. */ #define VXVA_MASK (VX_MASK | (0x1f << 16)) @@ -3313,8 +3503,10 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS #define PPCE300 PPC_OPCODE_E300 #define PPCSPE PPC_OPCODE_SPE +#define PPCSPE2 PPC_OPCODE_SPE2 #define PPCISEL PPC_OPCODE_ISEL #define PPCEFS PPC_OPCODE_EFS +#define PPCEFS2 PPC_OPCODE_EFS2 #define PPCBRLK PPC_OPCODE_BRLOCK #define PPCPMR PPC_OPCODE_PMR #define PPCTMR PPC_OPCODE_TMR @@ -3656,16 +3848,21 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, @@ -3673,10 +3870,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, +{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, +{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, @@ -3686,19 +3885,43 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, +{"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, +{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, +{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, +{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, @@ -3706,10 +3929,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, @@ -3721,30 +3946,41 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, -{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}}, +{"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}}, {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, +{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, -{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}}, +{"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}}, {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, +{"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, +{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, -{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, @@ -3873,6 +4109,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -3883,6 +4120,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -3898,8 +4136,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, +{"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -3984,16 +4224,24 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, +{"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -4002,6 +4250,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, +{"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -4038,21 +4290,33 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, +{"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, +{"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -6382,6 +6646,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, +{"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, @@ -6500,6 +6765,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, +{"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, @@ -8285,7 +8551,829 @@ const struct powerpc_macro powerpc_macros[] = { {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, + +/* old SPE instructions have new names with the same opcodes */ +{"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"}, +{"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"}, +{"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"}, +{"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"}, +{"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"}, +{"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"}, +{"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"}, +{"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"}, +{"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"}, +{"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"}, +{"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"}, +{"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"}, +{"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"}, +{"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"}, +{"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"}, +{"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"}, +{"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"}, +{"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"}, +{"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"}, +{"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"}, +{"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"}, +{"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"}, +{"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"}, + +/* SPE2 instructions which just are mapped to SPE2 */ +{"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"}, +{"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"}, +{"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"}, +{"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"} }; const int powerpc_num_macros = sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); + +/* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */ +const struct powerpc_opcode spe2_opcodes[] = { +{"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, +{"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, +{"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, +{"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, +{"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, +{"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, +{"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, +{"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}}, +{"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}}, +{"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, +{"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, +{"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, +{"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, +{"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, +{"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}}, +{"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, +{"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, +{"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, +{"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, +{"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, +{"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}}, +{"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}}, +{"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}}, +{"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}}, +{"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, +{"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, +{"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, +{"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}}, +{"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}}, +{"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}}, +{"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}}, +{"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +}; + +const int spe2_num_opcodes = + sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]); -- 2.7.4
On Wed, Aug 23, 2017 at 06:08:46PM +0300, Alexander Fedotov wrote: > Patch rebased to latest version of master due to a lot of changes were > done by Alan here Committed with a few small changes. -- Alan Modra Australia Development Lab, IBM
Out of interest, where is the current canonical documentation for the SPE2 and EFP2 instructions? (There's some in the e200z4 and e200z7 manuals, for example, but I don't know if that's the current canonical source.) -- Joseph S. Myers joseph@codesourcery.com
From 54a6a47e7ef3fc2823c69e3b1b0e97daaaa702a7 Mon Sep 17 00:00:00 2001 From: Alexander Fedotov-B55613 <b55613@freescale.com> Date: Wed, 23 Aug 2017 13:08:15 +0300 Subject: [PATCH] [PowerPC VLE] Add SPE2 and EFS2 instructions support --- gas/ChangeLog | 24 + gas/config/tc-ppc.c | 53 ++ gas/doc/as.texinfo | 2 +- gas/doc/c-ppc.texi | 3 + gas/testsuite/gas/ppc/efs.d | 25 + gas/testsuite/gas/ppc/efs.s | 29 + gas/testsuite/gas/ppc/efs2.d | 19 + gas/testsuite/gas/ppc/efs2.s | 18 + gas/testsuite/gas/ppc/ppc.exp | 8 + gas/testsuite/gas/ppc/spe.d | 267 ++++++++ gas/testsuite/gas/ppc/spe.s | 274 +++++++++ gas/testsuite/gas/ppc/spe2-checks.d | 4 + gas/testsuite/gas/ppc/spe2-checks.l | 73 +++ gas/testsuite/gas/ppc/spe2-checks.s | 99 +++ gas/testsuite/gas/ppc/spe2.d | 815 ++++++++++++++++++++++++ gas/testsuite/gas/ppc/spe2.s | 834 +++++++++++++++++++++++++ gas/testsuite/gas/ppc/spe_ambiguous.d | 15 + gas/testsuite/gas/ppc/spe_ambiguous.s | 21 + include/ChangeLog | 10 + include/opcode/ppc.h | 14 + opcodes/ChangeLog | 60 ++ opcodes/ppc-dis.c | 83 ++- opcodes/ppc-opc.c | 1088 ++++++++++++++++++++++++++++++++- 23 files changed, 3825 insertions(+), 13 deletions(-) create mode 100644 gas/testsuite/gas/ppc/efs.d create mode 100644 gas/testsuite/gas/ppc/efs.s create mode 100644 gas/testsuite/gas/ppc/efs2.d create mode 100644 gas/testsuite/gas/ppc/efs2.s create mode 100644 gas/testsuite/gas/ppc/spe.d create mode 100644 gas/testsuite/gas/ppc/spe.s create mode 100644 gas/testsuite/gas/ppc/spe2-checks.d create mode 100644 gas/testsuite/gas/ppc/spe2-checks.l create mode 100644 gas/testsuite/gas/ppc/spe2-checks.s create mode 100644 gas/testsuite/gas/ppc/spe2.d create mode 100644 gas/testsuite/gas/ppc/spe2.s create mode 100644 gas/testsuite/gas/ppc/spe_ambiguous.d create mode 100644 gas/testsuite/gas/ppc/spe_ambiguous.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 1f44c82..4201168 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,27 @@ +2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com> + Edmar Wienskoski <edmar.wienskoski@nxp.com + + * config/tc-ppc.c: + (md_parse_option): Add mspe2 switch. + (md_show_usage): Document -mspe2. + (ppc_setup_opcodes): Handle spe2_opcodes. + * doc/as.texinfo: Document -mspe2. + * doc/c-ppc.texi: Likewise. + * testsuite/gas/ppc/efs.d: New file. + * testsuite/gas/ppc/efs.s: Likewise. + * testsuite/gas/ppc/efs2.d: Likewise. + * testsuite/gas/ppc/efs2.s: Likewise. + * testsuite/gas/ppc/ppc.exp: Run new tests. + * testsuite/gas/ppc/spe.d: New file. + * testsuite/gas/ppc/spe.s: Likewise. + * testsuite/gas/ppc/spe2-checks.d: Likewise. + * testsuite/gas/ppc/spe2-checks.l: Likewise. + * testsuite/gas/ppc/spe2-checks.s: Likewise. + * testsuite/gas/ppc/spe2.d: Likewise. + * testsuite/gas/ppc/spe2.s: Likewise. + * testsuite/gas/ppc/spe_ambiguous.d: Likewise. + * testsuite/gas/ppc/spe_ambiguous.s: Likewise. + 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com> Edmar Wienskoski <edmar.wienskoski@nxp.com diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index e8dfbc4..d20fac6 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1258,6 +1258,10 @@ md_parse_option (int c, const char *arg) msolaris = FALSE; ppc_comment_chars = ppc_eabi_comment_chars; } + else if (strcmp (arg, "spe2") == 0) + { + ppc_cpu |= PPC_OPCODE_SPE2; + } #endif else { @@ -1353,6 +1357,7 @@ PowerPC options:\n\ -me5500, generate code for Freescale e5500 core complex\n\ -me6500, generate code for Freescale e6500 core complex\n\ -mspe generate code for Motorola SPE instructions\n\ +-mspe2 generate code for Freescale SPE2 instructions\n\ -mvle generate code for Freescale VLE instructions\n\ -mtitan generate code for AppliedMicro Titan core complex\n\ -mregnames Allow symbolic names for registers\n\ @@ -1688,6 +1693,54 @@ ppc_setup_opcodes (void) } } + /* SPE2 instructions */ + if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) + { + op_end = spe2_opcodes + spe2_num_opcodes; + for (op = spe2_opcodes; op < op_end; op++) + { + if (ENABLE_CHECKING) + { + if (op != spe2_opcodes) + { + unsigned old_seg, new_seg; + + old_seg = VLE_OP (op[-1].opcode, op[-1].mask); + old_seg = VLE_OP_TO_SEG (old_seg); + new_seg = VLE_OP (op[0].opcode, op[0].mask); + new_seg = VLE_OP_TO_SEG (new_seg); + + /* The major opcodes had better be sorted. Code in the + disassembler assumes the insns are sorted according to + major opcode. */ + if (new_seg < old_seg) + { + as_bad (_("major opcode is not sorted for %s"), op->name); + bad_insn = TRUE; + } + } + + bad_insn |= insn_validate (op); + } + + if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated)) + { + const char *retval; + + retval = hash_insert (ppc_hash, op->name, (void *) op); + if (retval != NULL) + { + as_bad (_("duplicate instruction %s"), + op->name); + bad_insn = TRUE; + } + } + } + + for (op = spe2_opcodes; op < op_end; op++) + hash_insert (ppc_hash, op->name, (void *) op); + } + /* Insert the macros into a hash table. */ ppc_macro_hash = hash_new (); diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 8aa83ef..8c125fd 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -487,7 +487,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}| @b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}| @b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}| - @b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}] + @b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-me300}|@b{-mcom}] [@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}] [@b{-mregnames}|@b{-mno-regnames}] [@b{-mrelocatable}|@b{-mrelocatable-lib}|@b{-K PIC}] [@b{-memb}] diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi index d94b418..7e66625 100644 --- a/gas/doc/c-ppc.texi +++ b/gas/doc/c-ppc.texi @@ -99,6 +99,9 @@ Generate code for Freescale e6500 core complex. @item -mspe Generate code for Motorola SPE instructions. +@item -mspe2 +Generate code for Freescale SPE2 instructions. + @item -mtitan Generate code for AppliedMicro Titan core complex. diff --git a/gas/testsuite/gas/ppc/efs.d b/gas/testsuite/gas/ppc/efs.d new file mode 100644 index 0000000..8d365a4 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs.d @@ -0,0 +1,25 @@ +#as: -mvle +#objdump: -d -Mefs -Mvle -Mefs2 +#name: Validate EFS instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 00 12 d1 efscfsi r0,r2 + 4: 10 00 12 d5 efsctsi r0,r2 + 8: 10 00 12 f1 efdcfsi r0,r2 + c: 10 00 12 f5 efdctsi r0,r2 + 10: 10 01 12 c2 efsmadd r0,r1,r2 + 14: 10 01 12 c3 efsmsub r0,r1,r2 + 18: 10 01 12 ca efsnmadd r0,r1,r2 + 1c: 10 01 12 cb efsnmsub r0,r1,r2 + 20: 10 01 12 e2 efdmadd r0,r1,r2 + 24: 10 01 12 e3 efdmsub r0,r1,r2 + 28: 10 01 12 ea efdnmadd r0,r1,r2 + 2c: 10 01 12 eb efdnmsub r0,r1,r2 + 30: 10 01 12 f0 efdcfuid r0,r2 + 34: 10 01 12 f1 efdcfsid r0,r2 + 38: 10 01 12 f8 efdctuidz r0,r2 + 3c: 10 01 12 fa efdctsidz r0,r2 \ No newline at end of file diff --git a/gas/testsuite/gas/ppc/efs.s b/gas/testsuite/gas/ppc/efs.s new file mode 100644 index 0000000..7afcfd8 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs.s @@ -0,0 +1,29 @@ +# PA EFS 1.0 and 1.1 instructions +# CMPE200GCC-62 + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + +;# EFS 1.0 instructions in accordance with EFP2_rev.1.4_spec + efscfsi rD, rB + efsctsi rD, rB + efdcfsi rD, rB + efdctsi rD, rB + +;# EFS 1.1 instructions in accordance with EFP2_rev.1.4_spec + efsmadd rD, rA, rB + efsmsub rD, rA, rB + efsnmadd rD, rA, rB + efsnmsub rD, rA, rB + efdmadd rD, rA, rB + efdmsub rD, rA, rB + efdnmadd rD, rA, rB + efdnmsub rD, rA, rB + +;# moved EFS opcodes in accordance with EFP2_rev.1.4_spec + efdcfuid rD, rB + efdcfsid rD, rB + efdctuidz rD, rB + efdctsidz rD, rB diff --git a/gas/testsuite/gas/ppc/efs2.d b/gas/testsuite/gas/ppc/efs2.d new file mode 100644 index 0000000..bfdfb14 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs2.d @@ -0,0 +1,19 @@ +#as: -mvle +#objdump: -d -Mvle -Mefs2 +#name: Validate EFS2 instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 12 b0 efsmax r0,r1,r2 + 4: 10 01 12 b1 efsmin r0,r1,r2 + 8: 10 01 12 b8 efdmax r0,r1,r2 + c: 10 01 12 b9 efdmin r0,r1,r2 + 10: 10 01 02 c7 efssqrt r0,r1 + 14: 10 04 12 d1 efscfh r0,r2 + 18: 10 04 12 d5 efscth r0,r2 + 1c: 10 01 02 e7 efdsqrt r0,r1 + 20: 10 04 12 f1 efdcfh r0,r2 + 24: 10 04 12 f5 efdcth r0,r2 \ No newline at end of file diff --git a/gas/testsuite/gas/ppc/efs2.s b/gas/testsuite/gas/ppc/efs2.s new file mode 100644 index 0000000..5d35e98 --- /dev/null +++ b/gas/testsuite/gas/ppc/efs2.s @@ -0,0 +1,18 @@ +# PA EFS2 instructions in accordance with EFP2_rev.1.4_spec +# CMPE200GCC-62 + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + + efsmax rD, rA, rB + efsmin rD, rA, rB + efdmax rD, rA, rB + efdmin rD, rA, rB + efssqrt rD, rA + efscfh rD, rB + efscth rD, rB + efdsqrt rD, rA + efdcfh rD, rB + efdcth rD, rB diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index bbe64be..cdcd8a1 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -65,6 +65,14 @@ if { [istarget powerpc*-*-*] } then { setup_xfail "*-*-*" run_dump_test "lsp" run_dump_test "lsp-checks" + run_dump_test "efs" + run_dump_test "efs2" + run_dump_test "spe2" + run_dump_test "spe2-checks" + run_dump_test "spe" + + setup_xfail "*-*-*" + run_dump_test "spe_ambiguous" } } diff --git a/gas/testsuite/gas/ppc/spe.d b/gas/testsuite/gas/ppc/spe.d new file mode 100644 index 0000000..7391028 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe.d @@ -0,0 +1,267 @@ +#as: -a32 -mvle +#objdump: -d -Mspe +#name: Validate SPE instructions + +.*: +file format elf.*-powerpc.* + + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 12 00 evaddw r0,r1,r2 + 4: 10 1f 12 02 evaddiw r0,r2,31 + 8: 10 01 12 04 evsubfw r0,r1,r2 + c: 10 01 12 04 evsubfw r0,r1,r2 + 10: 10 1f 12 06 evsubifw r0,31,r2 + 14: 10 1f 12 06 evsubifw r0,31,r2 + 18: 10 01 02 08 evabs r0,r1 + 1c: 10 01 02 09 evneg r0,r1 + 20: 10 01 02 0a evextsb r0,r1 + 24: 10 01 02 0b evextsh r0,r1 + 28: 10 01 02 0c evrndw r0,r1 + 2c: 10 01 02 0d evcntlzw r0,r1 + 30: 10 01 02 0e evcntlsw r0,r1 + 34: 10 01 12 0f brinc r0,r1,r2 + 38: 10 01 12 11 evand r0,r1,r2 + 3c: 10 01 12 12 evandc r0,r1,r2 + 40: 10 01 12 16 evxor r0,r1,r2 + 44: 10 01 0a 17 evmr r0,r1 + 48: 10 01 12 17 evor r0,r1,r2 + 4c: 10 01 12 18 evnor r0,r1,r2 + 50: 10 01 0a 18 evnor r0,r1,r1 + 54: 10 01 12 19 eveqv r0,r1,r2 + 58: 10 01 12 1b evorc r0,r1,r2 + 5c: 10 01 12 1e evnand r0,r1,r2 + 60: 10 01 12 20 evsrwu r0,r1,r2 + 64: 10 01 12 21 evsrws r0,r1,r2 + 68: 10 01 fa 22 evsrwiu r0,r1,31 + 6c: 10 01 fa 23 evsrwis r0,r1,31 + 70: 10 01 12 24 evslw r0,r1,r2 + 74: 10 01 fa 26 evslwi r0,r1,31 + 78: 10 01 12 28 evrlw r0,r1,r2 + 7c: 10 10 02 29 evsplati r0,-16 + 80: 10 01 fa 2a evrlwi r0,r1,31 + 84: 10 10 02 2b evsplatfi r0,-16 + 88: 10 01 12 2c evmergehi r0,r1,r2 + 8c: 10 01 12 2d evmergelo r0,r1,r2 + 90: 10 01 12 2e evmergehilo r0,r1,r2 + 94: 10 01 12 2f evmergelohi r0,r1,r2 + 98: 10 01 12 30 evcmpgtu cr0,r1,r2 + 9c: 10 01 12 31 evcmpgts cr0,r1,r2 + a0: 10 01 12 32 evcmpltu cr0,r1,r2 + a4: 10 01 12 33 evcmplts cr0,r1,r2 + a8: 10 01 12 34 evcmpeq cr0,r1,r2 + ac: 10 01 12 78 evsel r0,r1,r2,cr0 + b0: 10 01 12 80 evfsadd r0,r1,r2 + b4: 10 01 12 81 evfssub r0,r1,r2 + b8: 10 01 12 82 evfsmadd r0,r1,r2 + bc: 10 01 12 83 evfsmsub r0,r1,r2 + c0: 10 01 02 84 evfsabs r0,r1 + c4: 10 01 02 85 evfsnabs r0,r1 + c8: 10 01 02 86 evfsneg r0,r1 + cc: 10 01 12 88 evfsmul r0,r1,r2 + d0: 10 01 12 89 evfsdiv r0,r1,r2 + d4: 10 01 12 8a evfsnmadd r0,r1,r2 + d8: 10 01 12 8b evfsnmsub r0,r1,r2 + dc: 10 01 12 8c evfscmpgt cr0,r1,r2 + e0: 10 01 12 8d evfscmplt cr0,r1,r2 + e4: 10 01 12 8e evfscmpeq cr0,r1,r2 + e8: 10 00 12 90 evfscfui r0,r2 + ec: 10 00 12 91 evfscfsi r0,r2 + f0: 10 00 12 92 evfscfuf r0,r2 + f4: 10 00 12 93 evfscfsf r0,r2 + f8: 10 00 12 94 evfsctui r0,r2 + fc: 10 00 12 95 evfsctsi r0,r2 + 100: 10 00 12 96 evfsctuf r0,r2 + 104: 10 00 12 97 evfsctsf r0,r2 + 108: 10 00 12 98 evfsctuiz r0,r2 + 10c: 10 00 12 9a evfsctsiz r0,r2 + 110: 10 01 12 9c evfststgt cr0,r1,r2 + 114: 10 01 12 9d evfststlt cr0,r1,r2 + 118: 10 01 12 9e evfststeq cr0,r1,r2 + 11c: 10 01 13 00 evlddx r0,r1,r2 + 120: 10 01 0b 01 evldd r0,8\(r1\) + 124: 10 01 13 02 evldwx r0,r1,r2 + 128: 10 01 0b 03 evldw r0,8\(r1\) + 12c: 10 01 13 04 evldhx r0,r1,r2 + 130: 10 01 0b 05 evldh r0,8\(r1\) + 134: 10 01 13 08 evlhhesplatx r0,r1,r2 + 138: 10 01 0b 09 evlhhesplat r0,2\(r1\) + 13c: 10 01 13 0c evlhhousplatx r0,r1,r2 + 140: 10 01 0b 0d evlhhousplat r0,2\(r1\) + 144: 10 01 13 0e evlhhossplatx r0,r1,r2 + 148: 10 01 0b 0f evlhhossplat r0,2\(r1\) + 14c: 10 01 13 10 evlwhex r0,r1,r2 + 150: 10 01 0b 11 evlwhe r0,4\(r1\) + 154: 10 01 13 14 evlwhoux r0,r1,r2 + 158: 10 01 0b 15 evlwhou r0,4\(r1\) + 15c: 10 01 13 16 evlwhosx r0,r1,r2 + 160: 10 01 0b 17 evlwhos r0,4\(r1\) + 164: 10 01 13 18 evlwwsplatx r0,r1,r2 + 168: 10 01 0b 19 evlwwsplat r0,4\(r1\) + 16c: 10 01 13 1c evlwhsplatx r0,r1,r2 + 170: 10 01 0b 1d evlwhsplat r0,4\(r1\) + 174: 10 01 13 20 evstddx r0,r1,r2 + 178: 10 01 0b 21 evstdd r0,8\(r1\) + 17c: 10 01 13 22 evstdwx r0,r1,r2 + 180: 10 01 0b 23 evstdw r0,8\(r1\) + 184: 10 01 13 24 evstdhx r0,r1,r2 + 188: 10 01 0b 25 evstdh r0,8\(r1\) + 18c: 10 01 13 30 evstwhex r0,r1,r2 + 190: 10 01 0b 31 evstwhe r0,4\(r1\) + 194: 10 01 13 34 evstwhox r0,r1,r2 + 198: 10 01 0b 35 evstwho r0,4\(r1\) + 19c: 10 01 13 38 evstwwex r0,r1,r2 + 1a0: 10 01 0b 39 evstwwe r0,4\(r1\) + 1a4: 10 01 13 3c evstwwox r0,r1,r2 + 1a8: 10 01 0b 3d evstwwo r0,4\(r1\) + 1ac: 10 01 14 03 evmhessf r0,r1,r2 + 1b0: 10 01 14 07 evmhossf r0,r1,r2 + 1b4: 10 01 14 08 evmheumi r0,r1,r2 + 1b8: 10 01 14 09 evmhesmi r0,r1,r2 + 1bc: 10 01 14 0b evmhesmf r0,r1,r2 + 1c0: 10 01 14 0c evmhoumi r0,r1,r2 + 1c4: 10 01 14 0d evmhosmi r0,r1,r2 + 1c8: 10 01 14 0f evmhosmf r0,r1,r2 + 1cc: 10 01 14 23 evmhessfa r0,r1,r2 + 1d0: 10 01 14 27 evmhossfa r0,r1,r2 + 1d4: 10 01 14 28 evmheumia r0,r1,r2 + 1d8: 10 01 14 29 evmhesmia r0,r1,r2 + 1dc: 10 01 14 2b evmhesmfa r0,r1,r2 + 1e0: 10 01 14 2c evmhoumia r0,r1,r2 + 1e4: 10 01 14 2d evmhosmia r0,r1,r2 + 1e8: 10 01 14 2f evmhosmfa r0,r1,r2 + 1ec: 10 01 14 43 evmwlssf r0,r1,r2 + 1f0: 10 01 14 47 evmwhssf r0,r1,r2 + 1f4: 10 01 14 48 evmwlumi r0,r1,r2 + 1f8: 10 01 14 4b evmwlsmf r0,r1,r2 + 1fc: 10 01 14 4c evmwhumi r0,r1,r2 + 200: 10 01 14 4d evmwhsmi r0,r1,r2 + 204: 10 01 14 4f evmwhsmf r0,r1,r2 + 208: 10 01 14 53 evmwssf r0,r1,r2 + 20c: 10 01 14 58 evmwumi r0,r1,r2 + 210: 10 01 14 59 evmwsmi r0,r1,r2 + 214: 10 01 14 5b evmwsmf r0,r1,r2 + 218: 10 01 14 63 evmwlssfa r0,r1,r2 + 21c: 10 01 14 67 evmwhssfa r0,r1,r2 + 220: 10 01 14 68 evmwlumia r0,r1,r2 + 224: 10 01 14 6b evmwlsmfa r0,r1,r2 + 228: 10 01 14 6c evmwhumia r0,r1,r2 + 22c: 10 01 14 6d evmwhsmia r0,r1,r2 + 230: 10 01 14 6f evmwhsmfa r0,r1,r2 + 234: 10 01 14 73 evmwssfa r0,r1,r2 + 238: 10 01 14 78 evmwumia r0,r1,r2 + 23c: 10 01 14 79 evmwsmia r0,r1,r2 + 240: 10 01 14 7b evmwsmfa r0,r1,r2 + 244: 10 01 04 c0 evaddusiaaw r0,r1 + 248: 10 01 04 c1 evaddssiaaw r0,r1 + 24c: 10 01 04 c2 evsubfusiaaw r0,r1 + 250: 10 01 04 c3 evsubfssiaaw r0,r1 + 254: 10 01 04 c4 evmra r0,r1 + 258: 10 01 14 c6 evdivws r0,r1,r2 + 25c: 10 01 14 c7 evdivwu r0,r1,r2 + 260: 10 01 04 c8 evaddumiaaw r0,r1 + 264: 10 01 04 c9 evaddsmiaaw r0,r1 + 268: 10 01 04 ca evsubfumiaaw r0,r1 + 26c: 10 01 04 cb evsubfsmiaaw r0,r1 + 270: 10 01 15 00 evmheusiaaw r0,r1,r2 + 274: 10 01 15 01 evmhessiaaw r0,r1,r2 + 278: 10 01 15 03 evmhessfaaw r0,r1,r2 + 27c: 10 01 15 04 evmhousiaaw r0,r1,r2 + 280: 10 01 15 05 evmhossiaaw r0,r1,r2 + 284: 10 01 15 07 evmhossfaaw r0,r1,r2 + 288: 10 01 15 08 evmheumiaaw r0,r1,r2 + 28c: 10 01 15 09 evmhesmiaaw r0,r1,r2 + 290: 10 01 15 0b evmhesmfaaw r0,r1,r2 + 294: 10 01 15 0c evmhoumiaaw r0,r1,r2 + 298: 10 01 15 0d evmhosmiaaw r0,r1,r2 + 29c: 10 01 15 0f evmhosmfaaw r0,r1,r2 + 2a0: 10 01 15 28 evmhegumiaa r0,r1,r2 + 2a4: 10 01 15 29 evmhegsmiaa r0,r1,r2 + 2a8: 10 01 15 2b evmhegsmfaa r0,r1,r2 + 2ac: 10 01 15 2c evmhogumiaa r0,r1,r2 + 2b0: 10 01 15 2d evmhogsmiaa r0,r1,r2 + 2b4: 10 01 15 2f evmhogsmfaa r0,r1,r2 + 2b8: 10 01 15 40 evmwlusiaaw r0,r1,r2 + 2bc: 10 01 15 41 evmwlssiaaw r0,r1,r2 + 2c0: 10 01 15 43 evmwlssfaaw r0,r1,r2 + 2c4: 10 01 15 44 evmwhusiaa r0,r1,r2 + 2c8: 10 01 15 45 evmwhssmaa r0,r1,r2 + 2cc: 10 01 15 47 evmwhssfaa r0,r1,r2 + 2d0: 10 01 15 48 evmwlumiaaw r0,r1,r2 + 2d4: 10 01 15 49 evmwlsmiaaw r0,r1,r2 + 2d8: 10 01 15 4b evmwlsmfaaw r0,r1,r2 + 2dc: 10 01 15 4c evmwhumiaa r0,r1,r2 + 2e0: 10 01 15 4d evmwhsmiaa r0,r1,r2 + 2e4: 10 01 15 4f evmwhsmfaa r0,r1,r2 + 2e8: 10 01 15 53 evmwssfaa r0,r1,r2 + 2ec: 10 01 15 58 evmwumiaa r0,r1,r2 + 2f0: 10 01 15 59 evmwsmiaa r0,r1,r2 + 2f4: 10 01 15 5b evmwsmfaa r0,r1,r2 + 2f8: 10 01 15 64 evmwhgumiaa r0,r1,r2 + 2fc: 10 01 15 65 evmwhgsmiaa r0,r1,r2 + 300: 10 01 15 67 evmwhgssfaa r0,r1,r2 + 304: 10 01 15 6f evmwhgsmfaa r0,r1,r2 + 308: 10 01 15 80 evmheusianw r0,r1,r2 + 30c: 10 01 15 81 evmhessianw r0,r1,r2 + 310: 10 01 15 83 evmhessfanw r0,r1,r2 + 314: 10 01 15 84 evmhousianw r0,r1,r2 + 318: 10 01 15 85 evmhossianw r0,r1,r2 + 31c: 10 01 15 87 evmhossfanw r0,r1,r2 + 320: 10 01 15 88 evmheumianw r0,r1,r2 + 324: 10 01 15 89 evmhesmianw r0,r1,r2 + 328: 10 01 15 8b evmhesmfanw r0,r1,r2 + 32c: 10 01 15 8c evmhoumianw r0,r1,r2 + 330: 10 01 15 8d evmhosmianw r0,r1,r2 + 334: 10 01 15 8f evmhosmfanw r0,r1,r2 + 338: 10 01 15 a8 evmhegumian r0,r1,r2 + 33c: 10 01 15 a9 evmhegsmian r0,r1,r2 + 340: 10 01 15 ab evmhegsmfan r0,r1,r2 + 344: 10 01 15 ac evmhogumian r0,r1,r2 + 348: 10 01 15 ad evmhogsmian r0,r1,r2 + 34c: 10 01 15 af evmhogsmfan r0,r1,r2 + 350: 10 01 15 c0 evmwlusianw r0,r1,r2 + 354: 10 01 15 c1 evmwlssianw r0,r1,r2 + 358: 10 01 15 c3 evmwlssfanw r0,r1,r2 + 35c: 10 01 15 c4 evmwhusian r0,r1,r2 + 360: 10 01 15 c5 evmwhssian r0,r1,r2 + 364: 10 01 15 c7 evmwhssfan r0,r1,r2 + 368: 10 01 15 c8 evmwlumianw r0,r1,r2 + 36c: 10 01 15 c9 evmwlsmianw r0,r1,r2 + 370: 10 01 15 cb evmwlsmfanw r0,r1,r2 + 374: 10 01 15 cc evmwhumian r0,r1,r2 + 378: 10 01 15 cd evmwhsmian r0,r1,r2 + 37c: 10 01 15 cf evmwhsmfan r0,r1,r2 + 380: 10 01 15 d3 evmwssfan r0,r1,r2 + 384: 10 01 15 d8 evmwumian r0,r1,r2 + 388: 10 01 15 d9 evmwsmian r0,r1,r2 + 38c: 10 01 15 db evmwsmfan r0,r1,r2 + 390: 10 01 15 e4 evmwhgumian r0,r1,r2 + 394: 10 01 15 e5 evmwhgsmian r0,r1,r2 + 398: 10 01 15 e7 evmwhgssfan r0,r1,r2 + 39c: 10 01 15 ef evmwhgsmfan r0,r1,r2 + 3a0: 7c 01 16 3e evlddepx r0,r1,r2 + 3a4: 7c 01 17 3e evstddepx r0,r1,r2 + 3a8: 10 01 12 c0 efsadd r0,r1,r2 + 3ac: 10 01 12 c1 efssub r0,r1,r2 + 3b0: 10 01 02 c4 efsabs r0,r1 + 3b4: 10 01 02 c5 efsnabs r0,r1 + 3b8: 10 01 02 c6 efsneg r0,r1 + 3bc: 10 01 12 c8 efsmul r0,r1,r2 + 3c0: 10 01 12 c9 efsdiv r0,r1,r2 + 3c4: 10 01 12 cc efscmpgt cr0,r1,r2 + 3c8: 10 01 12 cd efscmplt cr0,r1,r2 + 3cc: 10 01 12 ce efscmpeq cr0,r1,r2 + 3d0: 10 00 12 d0 efscfui r0,r2 + 3d4: 10 00 12 d1 efscfsi r0,r2 + 3d8: 10 00 12 d2 efscfuf r0,r2 + 3dc: 10 00 12 d3 efscfsf r0,r2 + 3e0: 10 00 12 d4 efsctui r0,r2 + 3e4: 10 00 12 d5 efsctsi r0,r2 + 3e8: 10 00 12 d6 efsctuf r0,r2 + 3ec: 10 00 12 d7 efsctsf r0,r2 + 3f0: 10 00 12 d8 efsctuiz r0,r2 + 3f4: 10 00 12 da efsctsiz r0,r2 + 3f8: 10 01 12 dc efststgt cr0,r1,r2 + 3fc: 10 01 12 dd efststlt cr0,r1,r2 + 400: 10 01 12 de efststeq cr0,r1,r2 diff --git a/gas/testsuite/gas/ppc/spe.s b/gas/testsuite/gas/ppc/spe.s new file mode 100644 index 0000000..5be3386 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe.s @@ -0,0 +1,274 @@ +# PA SPE instructions + .section ".text" + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ rT,0 + .equ UIMM, 31 + .equ UIMM_2, 2 + .equ UIMM_4, 4 + .equ UIMM_8, 8 + .equ SIMM, -16 + .equ crD, 0 + .equ crS, 0 + + evaddw rS, rA, rB + evaddiw rS, rB, UIMM + evsubfw rS, rA, rB + evsubw rS, rB, rA + evsubifw rS, UIMM, rB + evsubiw rS, rB, UIMM + evabs rS, rA + evneg rS, rA + evextsb rS, rA + evextsh rS, rA + evrndw rS, rA + evcntlzw rS, rA + evcntlsw rS, rA + brinc rS, rA, rB + evand rS, rA, rB + evandc rS, rA, rB + evxor rS, rA, rB + evmr rS, rA + evor rS, rA, rB + evnor rS, rA, rB + evnot rS, rA + eveqv rS, rA, rB + evorc rS, rA, rB + evnand rS, rA, rB + evsrwu rS, rA, rB + evsrws rS, rA, rB + evsrwiu rS, rA, UIMM + evsrwis rS, rA, UIMM + evslw rS, rA, rB + evslwi rS, rA, UIMM + evrlw rS, rA, rB + evsplati rS, SIMM + evrlwi rS, rA, UIMM + evsplatfi rS, SIMM + evmergehi rS, rA, rB + evmergelo rS, rA, rB + evmergehilo rS, rA, rB + evmergelohi rS, rA, rB + evcmpgtu crD, rA, rB + evcmpgts crD, rA, rB + evcmpltu crD, rA, rB + evcmplts crD, rA, rB + evcmpeq crD, rA, rB + evsel rS, rA, rB, crS + evfsadd rS, rA, rB + evfssub rS, rA, rB + evfsmadd rS, rA, rB + evfsmsub rS, rA, rB + evfsabs rS, rA + evfsnabs rS, rA + evfsneg rS, rA + evfsmul rS, rA, rB + evfsdiv rS, rA, rB + evfsnmadd rS, rA, rB + evfsnmsub rS, rA, rB + evfscmpgt crD, rA, rB + evfscmplt crD, rA, rB + evfscmpeq crD, rA, rB + evfscfui rS, rB + evfscfsi rS, rB + evfscfuf rS, rB + evfscfsf rS, rB + evfsctui rS, rB + evfsctsi rS, rB + evfsctuf rS, rB + evfsctsf rS, rB + evfsctuiz rS, rB + evfsctsiz rS, rB + evfststgt crD, rA, rB + evfststlt crD, rA, rB + evfststeq crD, rA, rB + evlddx rS, rA, rB + evldd rS, UIMM_8(rA) + evldwx rS, rA, rB + evldw rS, UIMM_8(rA) + evldhx rS, rA, rB + evldh rS, UIMM_8(rA) + evlhhesplatx rS, rA, rB + evlhhesplat rS, UIMM_2(rA) + evlhhousplatx rS, rA, rB + evlhhousplat rS, UIMM_2(rA) + evlhhossplatx rS, rA, rB + evlhhossplat rS, UIMM_2(rA) + evlwhex rS, rA, rB + evlwhe rS, UIMM_4(rA) + evlwhoux rS, rA, rB + evlwhou rS, UIMM_4(rA) + evlwhosx rS, rA, rB + evlwhos rS, UIMM_4(rA) + evlwwsplatx rS, rA, rB + evlwwsplat rS, UIMM_4(rA) + evlwhsplatx rS, rA, rB + evlwhsplat rS, UIMM_4(rA) + evstddx rS, rA, rB + evstdd rS, UIMM_8(rA) + evstdwx rS, rA, rB + evstdw rS, UIMM_8(rA) + evstdhx rS, rA, rB + evstdh rS, UIMM_8(rA) + evstwhex rS, rA, rB + evstwhe rS, UIMM_4(rA) + evstwhox rS, rA, rB + evstwho rS, UIMM_4(rA) + evstwwex rS, rA, rB + evstwwe rS, UIMM_4(rA) + evstwwox rS, rA, rB + evstwwo rS, UIMM_4(rA) + evmhessf rS, rA, rB + evmhossf rS, rA, rB + evmheumi rS, rA, rB + evmhesmi rS, rA, rB + evmhesmf rS, rA, rB + evmhoumi rS, rA, rB + evmhosmi rS, rA, rB + evmhosmf rS, rA, rB + evmhessfa rS, rA, rB + evmhossfa rS, rA, rB + evmheumia rS, rA, rB + evmhesmia rS, rA, rB + evmhesmfa rS, rA, rB + evmhoumia rS, rA, rB + evmhosmia rS, rA, rB + evmhosmfa rS, rA, rB + evmwlssf rD, rA, rB + evmwhssf rS, rA, rB + evmwlumi rS, rA, rB + evmwlsmf rD, rA, rB + evmwhumi rS, rA, rB + evmwhsmi rS, rA, rB + evmwhsmf rS, rA, rB + evmwssf rS, rA, rB + evmwumi rS, rA, rB + evmwsmi rS, rA, rB + evmwsmf rS, rA, rB + evmwlssfa rD, rA, rB + evmwhssfa rS, rA, rB + evmwlumia rS, rA, rB + evmwlsmfa rD, rA, rB + evmwhumia rS, rA, rB + evmwhsmia rS, rA, rB + evmwhsmfa rS, rA, rB + evmwssfa rS, rA, rB + evmwumia rS, rA, rB + evmwsmia rS, rA, rB + evmwsmfa rS, rA, rB + evaddusiaaw rS, rA + evaddssiaaw rS, rA + evsubfusiaaw rS, rA + evsubfssiaaw rS, rA + evmra rS, rA + evdivws rS, rA, rB + evdivwu rS, rA, rB + evaddumiaaw rS, rA + evaddsmiaaw rS, rA + evsubfumiaaw rS, rA + evsubfsmiaaw rS, rA + evmheusiaaw rS, rA, rB + evmhessiaaw rS, rA, rB + evmhessfaaw rS, rA, rB + evmhousiaaw rS, rA, rB + evmhossiaaw rS, rA, rB + evmhossfaaw rS, rA, rB + evmheumiaaw rS, rA, rB + evmhesmiaaw rS, rA, rB + evmhesmfaaw rS, rA, rB + evmhoumiaaw rS, rA, rB + evmhosmiaaw rS, rA, rB + evmhosmfaaw rS, rA, rB + evmhegumiaa rS, rA, rB + evmhegsmiaa rS, rA, rB + evmhegsmfaa rS, rA, rB + evmhogumiaa rS, rA, rB + evmhogsmiaa rS, rA, rB + evmhogsmfaa rS, rA, rB + evmwlusiaaw rS, rA, rB + evmwlssiaaw rS, rA, rB + evmwlssfaaw rD, rA, rB + evmwhusiaa rD, rA, rB + evmwhssmaa rD, rA, rB + evmwhssfaa rD, rA, rB + evmwlumiaaw rS, rA, rB + evmwlsmiaaw rS, rA, rB + evmwlsmfaaw rD, rA, rB + evmwhumiaa rD, rA, rB + evmwhsmiaa rD, rA, rB + evmwhsmfaa rD, rA, rB + evmwssfaa rS, rA, rB + evmwumiaa rS, rA, rB + evmwsmiaa rS, rA, rB + evmwsmfaa rS, rA, rB + evmwhgumiaa rD, rA, rB + evmwhgsmiaa rD, rA, rB + evmwhgssfaa rD, rA, rB + evmwhgsmfaa rD, rA, rB + evmheusianw rS, rA, rB + evmhessianw rS, rA, rB + evmhessfanw rS, rA, rB + evmhousianw rS, rA, rB + evmhossianw rS, rA, rB + evmhossfanw rS, rA, rB + evmheumianw rS, rA, rB + evmhesmianw rS, rA, rB + evmhesmfanw rS, rA, rB + evmhoumianw rS, rA, rB + evmhosmianw rS, rA, rB + evmhosmfanw rS, rA, rB + evmhegumian rS, rA, rB + evmhegsmian rS, rA, rB + evmhegsmfan rS, rA, rB + evmhogumian rS, rA, rB + evmhogsmian rS, rA, rB + evmhogsmfan rS, rA, rB + evmwlusianw rS, rA, rB + evmwlssianw rS, rA, rB + evmwlssfanw rD, rA, rB + evmwhusian rD, rA, rB + evmwhssian rD, rA, rB + evmwhssfan rD, rA, rB + evmwlumianw rS, rA, rB + evmwlsmianw rS, rA, rB + evmwlsmfanw rD, rA, rB + evmwhumian rD, rA, rB + evmwhsmian rD, rA, rB + evmwhsmfan rD, rA, rB + evmwssfan rS, rA, rB + evmwumian rS, rA, rB + evmwsmian rS, rA, rB + evmwsmfan rS, rA, rB + evmwhgumian rD, rA, rB + evmwhgsmian rD, rA, rB + evmwhgssfan rD, rA, rB + evmwhgsmfan rD, rA, rB + evlddepx rT, rA, rB + evstddepx rT, rA, rB + +;#SPE mapped by macro + evsadd rS, rA, rB + evssub rS, rA, rB + evsabs rS, rA + evsnabs rS, rA + evsneg rS, rA + evsmul rS, rA, rB + evsdiv rS, rA, rB + evscmpgt crD, rA, rB + evsgmplt crD, rA, rB + evsgmpeq crD, rA, rB + evscfui rS, rB + evscfsi rS, rB + evscfuf rS, rB + evscfsf rS, rB + evsctui rS, rB + evsctsi rS, rB + evsctuf rS, rB + evsctsf rS, rB + evsctuiz rS, rB + evsctsiz rS, rB + evststgt crD, rA, rB + evststlt crD, rA, rB + evststeq crD, rA, rB diff --git a/gas/testsuite/gas/ppc/spe2-checks.d b/gas/testsuite/gas/ppc/spe2-checks.d new file mode 100644 index 0000000..6af4102 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2-checks.d @@ -0,0 +1,4 @@ +#as: -a32 -mvle -mspe2 +#name: Test SPE2 operands checks +#error-output: spe2-checks.l + diff --git a/gas/testsuite/gas/ppc/spe2-checks.l b/gas/testsuite/gas/ppc/spe2-checks.l new file mode 100644 index 0000000..276c650 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2-checks.l @@ -0,0 +1,73 @@ +[^:]*: Assembler messages: +.*:29: Error: operand out of range \(32 is not between 0 and 31\) +.*:30: Error: operand out of range \(32 is not between 0 and 31\) +.*:31: Error: operand out of range \(32 is not between 0 and 31\) +.*:32: Error: operand out of range \(32 is not between 0 and 31\) +.*:33: Error: operand out of range \(8 is not between 0 and 7\) +.*:34: Error: operand out of range \(8 is not between 0 and 7\) +.*:35: Error: operand out of range \(4 is not between 0 and 3\) +.*:36: Error: operand out of range \(8 is not between 0 and 7\) +.*:37: Error: operand out of range \(4 is not between 0 and 3\) +.*:38: Error: operand out of range \(16 is not between 0 and 15\) +.*:39: Error: operand out of range \(16 is not between 0 and 15\) +.*:40: Error: operand out of range \(16 is not between 0 and 15\) +.*:41: Error: operand out of range \(4 is not between 0 and 3\) +.*:42: Error: operand out of range \(4 is not between 0 and 3\) +.*:43: Error: invalid offset +.*:44: Error: operand out of range \(8 is not between 0 and 7\) +.*:44: Error: invalid offset +.*:45: Error: UIMM values >7 are illegal +.*:46: Error: UIMM values >7 are illegal +.*:47: Error: UIMM values >7 are illegal +.*:48: Error: UIMM values >7 are illegal +.*:49: Error: UIMM values >15 are illegal +.*:50: Error: UIMM values >15 are illegal +.*:51: Error: UIMM values >15 are illegal +.*:52: Error: UIMM values >15 are illegal +.*:53: Error: operand out of range \(8 is not between 0 and 7\) +.*:54: Error: operand out of range \(8 is not between 0 and 7\) +.*:55: Error: operand out of range \(8 is not between 0 and 7\) +.*:56: Error: operand out of domain \(7 is not a multiple of 8\) +.*:57: Error: operand out of domain \(1 is not a multiple of 2\) +.*:58: Error: operand out of domain \(3 is not a multiple of 4\) +.*:59: Error: operand out of domain \(3 is not a multiple of 4\) +.*:60: Error: operand out of range \(32 is not between 0 and 31\) +.*:61: Error: operand out of domain \(7 is not a multiple of 8\) +.*:62: Error: operand out of domain \(3 is not a multiple of 4\) +.*:63: Error: operand out of domain \(3 is not a multiple of 4\) +.*:64: Error: operand out of domain \(3 is not a multiple of 4\) +.*:65: Error: operand out of domain \(3 is not a multiple of 4\) +.*:66: Error: operand out of domain \(3 is not a multiple of 4\) +.*:67: Error: operand out of domain \(3 is not a multiple of 4\) +.*:68: Error: operand out of domain \(1 is not a multiple of 2\) +.*:69: Error: operand out of domain \(7 is not a multiple of 8\) +.*:70: Error: operand out of domain \(7 is not a multiple of 8\) +.*:71: Error: operand out of domain \(7 is not a multiple of 8\) +.*:72: Error: operand out of domain \(7 is not a multiple of 8\) +.*:73: Error: operand out of domain \(1 is not a multiple of 2\) +.*:74: Error: operand out of domain \(1 is not a multiple of 2\) +.*:75: Error: operand out of domain \(1 is not a multiple of 2\) +.*:76: Error: operand out of domain \(1 is not a multiple of 2\) +.*:77: Error: operand out of domain \(3 is not a multiple of 4\) +.*:78: Error: operand out of domain \(3 is not a multiple of 4\) +.*:79: Error: operand out of domain \(3 is not a multiple of 4\) +.*:80: Error: operand out of domain \(3 is not a multiple of 4\) +.*:81: Error: operand out of domain \(3 is not a multiple of 4\) +.*:82: Error: operand out of domain \(3 is not a multiple of 4\) +.*:83: Error: operand out of domain \(3 is not a multiple of 4\) +.*:84: Error: UIMM = 00000 is illegal +.*:85: Error: operand out of domain \(7 is not a multiple of 8\) +.*:86: Error: operand out of domain \(7 is not a multiple of 8\) +.*:87: Error: operand out of domain \(7 is not a multiple of 8\) +.*:88: Error: operand out of domain \(7 is not a multiple of 8\) +.*:89: Error: operand out of domain \(3 is not a multiple of 4\) +.*:90: Error: operand out of domain \(3 is not a multiple of 4\) +.*:91: Error: operand out of domain \(3 is not a multiple of 4\) +.*:92: Error: operand out of domain \(3 is not a multiple of 4\) +.*:93: Error: operand out of domain \(3 is not a multiple of 4\) +.*:94: Error: operand out of domain \(3 is not a multiple of 4\) +.*:95: Error: operand out of domain \(3 is not a multiple of 4\) +.*:96: Error: operand out of domain \(3 is not a multiple of 4\) +.*:97: Error: operand out of domain \(3 is not a multiple of 4\) +.*:98: Error: operand out of domain \(3 is not a multiple of 4\) +.*:99: Error: operand out of domain \(1 is not a multiple of 2\) \ No newline at end of file diff --git a/gas/testsuite/gas/ppc/spe2-checks.s b/gas/testsuite/gas/ppc/spe2-checks.s new file mode 100644 index 0000000..b1fd776 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2-checks.s @@ -0,0 +1,99 @@ +# PA SPE2 instructions + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ UIMM_ILL, 32 + .equ UIMM_1_ZERO, 0 + .equ UIMM_1_ILL, 32 + .equ UIMM_2_ILL, 1 + .equ UIMM_4_ILL, 3 + .equ UIMM_8_ILL, 7 + .equ UIMM_GT7, 8 + .equ UIMM_GT15, 16 + .equ nnn_ILL, 8 + .equ bbb_ILL, 8 + .equ dd, 3 + .equ dd_ILL, 4 + .equ Ddd, 7 + .equ Ddd_ILL, 8 + .equ hh, 3 + .equ hh_ILL, 4 + .equ mask_ILL, 16 + .equ offset_ILL0, 0 + .equ offset_ILL, 8 + + + evaddib rD, rB, UIMM_ILL + evaddih rD, rB, UIMM_ILL + evsubifh rD, UIMM_ILL, rB + evsubifb rD, UIMM_ILL, rB + evinsb rD, rA, Ddd, bbb_ILL + evxtrb rD, rA, Ddd, bbb_ILL + evsplath rD, rA, hh_ILL + evsplatb rD, rA, bbb_ILL + evinsh rD, rA, dd_ILL, hh + evclrbe rD, rA, mask_ILL + evclrbo rD, rA, mask_ILL + evclrh rD, rA, mask_ILL + evxtrh rD, rA, dd_ILL, hh + evxtrh rD, rA, dd, hh_ILL + evxtrd rD, rA, rB, offset_ILL0 + evxtrd rD, rA, rB, offset_ILL + evsrbiu rD, rA, UIMM_GT7 + evsrbis rD, rA, UIMM_GT7 + evslbi rD, rA, UIMM_GT7 + evrlbi rD, rA, UIMM_GT7 + evsrhiu rD, rA, UIMM_GT15 + evsrhis rD, rA, UIMM_GT15 + evslhi rD, rA, UIMM_GT15 + evrlhi rD, rA, UIMM_GT15 + evsroiu rD, rA, nnn_ILL + evsrois rD, rA, nnn_ILL + evsloi rD, rA, nnn_ILL + evldb rD, UIMM_8_ILL (rA) + evlhhsplath rD, UIMM_2_ILL (rA) + evlwbsplatw rD, UIMM_4_ILL (rA) + evlwhsplatw rD, UIMM_4_ILL (rA) + evlbbsplatb rD, UIMM_1_ILL (rA) + evstdb rS, UIMM_8_ILL (rA) + evlwbe rD, UIMM_4_ILL (rA) + evlwbou rD, UIMM_4_ILL (rA) + evlwbos rD, UIMM_4_ILL (rA) + evstwbe rS, UIMM_4_ILL (rA) + evstwbo rS, UIMM_4_ILL (rA) + evstwb rS, UIMM_4_ILL (rA) + evsthb rS, UIMM_2_ILL (rA) + evlddu rD, UIMM_8_ILL (rA) + evldwu rD, UIMM_8_ILL (rA) + evldhu rD, UIMM_8_ILL (rA) + evldbu rD, UIMM_8_ILL (rA) + evlhhesplatu rD, UIMM_2_ILL (rA) + evlhhsplathu rD, UIMM_2_ILL (rA) + evlhhousplatu rD, UIMM_2_ILL (rA) + evlhhossplatu rD, UIMM_2_ILL (rA) + evlwheu rD, UIMM_4_ILL (rA) + evlwbsplatwu rD, UIMM_4_ILL (rA) + evlwhouu rD, UIMM_4_ILL (rA) + evlwhosu rD, UIMM_4_ILL (rA) + evlwwsplatu rD, UIMM_4_ILL (rA) + evlwhsplatwu rD, UIMM_4_ILL (rA) + evlwhsplatu rD, UIMM_4_ILL (rA) + evlbbsplatbu rD, UIMM_1_ZERO (rA) + evstddu rS, UIMM_8_ILL (rA) + evstdwu rS, UIMM_8_ILL (rA) + evstdhu rS, UIMM_8_ILL (rA) + evstdbu rS, UIMM_8_ILL (rA) + evlwbeu rD, UIMM_4_ILL (rA) + evlwbouu rD, UIMM_4_ILL (rA) + evlwbosu rD, UIMM_4_ILL (rA) + evstwheu rS, UIMM_4_ILL (rA) + evstwbeu rS, UIMM_4_ILL (rA) + evstwhou rS, UIMM_4_ILL (rA) + evstwbou rS, UIMM_4_ILL (rA) + evstwweu rS, UIMM_4_ILL (rA) + evstwbu rS, UIMM_4_ILL (rA) + evstwwou rS, UIMM_4_ILL (rA) + evsthbu rS, UIMM_2_ILL (rA) diff --git a/gas/testsuite/gas/ppc/spe2.d b/gas/testsuite/gas/ppc/spe2.d new file mode 100644 index 0000000..e4c45de --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2.d @@ -0,0 +1,815 @@ +#as: -a32 -mvle -mspe2 +#objdump: -d -Mspe2 -Mefs2 +#name: Validate SPE2 instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 10 80 evdotpwcssi r0,r1,r2 + 4: 10 01 10 81 evdotpwcsmi r0,r1,r2 + 8: 10 01 10 82 evdotpwcssfr r0,r1,r2 + c: 10 01 10 83 evdotpwcssf r0,r1,r2 + 10: 10 01 10 88 evdotpwgasmf r0,r1,r2 + 14: 10 01 10 89 evdotpwxgasmf r0,r1,r2 + 18: 10 01 10 8a evdotpwgasmfr r0,r1,r2 + 1c: 10 01 10 8b evdotpwxgasmfr r0,r1,r2 + 20: 10 01 10 8c evdotpwgssmf r0,r1,r2 + 24: 10 01 10 8d evdotpwxgssmf r0,r1,r2 + 28: 10 01 10 8e evdotpwgssmfr r0,r1,r2 + 2c: 10 01 10 8f evdotpwxgssmfr r0,r1,r2 + 30: 10 01 10 90 evdotpwcssiaaw3 r0,r1,r2 + 34: 10 01 10 91 evdotpwcsmiaaw3 r0,r1,r2 + 38: 10 01 10 92 evdotpwcssfraaw3 r0,r1,r2 + 3c: 10 01 10 93 evdotpwcssfaaw3 r0,r1,r2 + 40: 10 01 10 98 evdotpwgasmfaa3 r0,r1,r2 + 44: 10 01 10 99 evdotpwxgasmfaa3 r0,r1,r2 + 48: 10 01 10 9a evdotpwgasmfraa3 r0,r1,r2 + 4c: 10 01 10 9b evdotpwxgasmfraa3 r0,r1,r2 + 50: 10 01 10 9c evdotpwgssmfaa3 r0,r1,r2 + 54: 10 01 10 9d evdotpwxgssmfaa3 r0,r1,r2 + 58: 10 01 10 9e evdotpwgssmfraa3 r0,r1,r2 + 5c: 10 01 10 9f evdotpwxgssmfraa3 r0,r1,r2 + 60: 10 01 10 a0 evdotpwcssia r0,r1,r2 + 64: 10 01 10 a1 evdotpwcsmia r0,r1,r2 + 68: 10 01 10 a2 evdotpwcssfra r0,r1,r2 + 6c: 10 01 10 a3 evdotpwcssfa r0,r1,r2 + 70: 10 01 10 a8 evdotpwgasmfa r0,r1,r2 + 74: 10 01 10 a9 evdotpwxgasmfa r0,r1,r2 + 78: 10 01 10 aa evdotpwgasmfra r0,r1,r2 + 7c: 10 01 10 ab evdotpwxgasmfra r0,r1,r2 + 80: 10 01 10 ac evdotpwgssmfa r0,r1,r2 + 84: 10 01 10 ad evdotpwxgssmfa r0,r1,r2 + 88: 10 01 10 ae evdotpwgssmfra r0,r1,r2 + 8c: 10 01 10 af evdotpwxgssmfra r0,r1,r2 + 90: 10 01 10 b0 evdotpwcssiaaw r0,r1,r2 + 94: 10 01 10 b1 evdotpwcsmiaaw r0,r1,r2 + 98: 10 01 10 b2 evdotpwcssfraaw r0,r1,r2 + 9c: 10 01 10 b3 evdotpwcssfaaw r0,r1,r2 + a0: 10 01 10 b8 evdotpwgasmfaa r0,r1,r2 + a4: 10 01 10 b9 evdotpwxgasmfaa r0,r1,r2 + a8: 10 01 10 ba evdotpwgasmfraa r0,r1,r2 + ac: 10 01 10 bb evdotpwxgasmfraa r0,r1,r2 + b0: 10 01 10 bc evdotpwgssmfaa r0,r1,r2 + b4: 10 01 10 bd evdotpwxgssmfaa r0,r1,r2 + b8: 10 01 10 be evdotpwgssmfraa r0,r1,r2 + bc: 10 01 10 bf evdotpwxgssmfraa r0,r1,r2 + c0: 10 01 11 00 evdotphihcssi r0,r1,r2 + c4: 10 01 11 01 evdotplohcssi r0,r1,r2 + c8: 10 01 11 02 evdotphihcssf r0,r1,r2 + cc: 10 01 11 03 evdotplohcssf r0,r1,r2 + d0: 10 01 11 08 evdotphihcsmi r0,r1,r2 + d4: 10 01 11 09 evdotplohcsmi r0,r1,r2 + d8: 10 01 11 0a evdotphihcssfr r0,r1,r2 + dc: 10 01 11 0b evdotplohcssfr r0,r1,r2 + e0: 10 01 11 10 evdotphihcssiaaw3 r0,r1,r2 + e4: 10 01 11 11 evdotplohcssiaaw3 r0,r1,r2 + e8: 10 01 11 12 evdotphihcssfaaw3 r0,r1,r2 + ec: 10 01 11 13 evdotplohcssfaaw3 r0,r1,r2 + f0: 10 01 11 18 evdotphihcsmiaaw3 r0,r1,r2 + f4: 10 01 11 19 evdotplohcsmiaaw3 r0,r1,r2 + f8: 10 01 11 1a evdotphihcssfraaw3 r0,r1,r2 + fc: 10 01 11 1b evdotplohcssfraaw3 r0,r1,r2 + 100: 10 01 11 20 evdotphihcssia r0,r1,r2 + 104: 10 01 11 21 evdotplohcssia r0,r1,r2 + 108: 10 01 11 22 evdotphihcssfa r0,r1,r2 + 10c: 10 01 11 23 evdotplohcssfa r0,r1,r2 + 110: 10 01 11 28 evdotphihcsmia r0,r1,r2 + 114: 10 01 11 29 evdotplohcsmia r0,r1,r2 + 118: 10 01 11 2a evdotphihcssfra r0,r1,r2 + 11c: 10 01 11 2b evdotplohcssfra r0,r1,r2 + 120: 10 01 11 30 evdotphihcssiaaw r0,r1,r2 + 124: 10 01 11 31 evdotplohcssiaaw r0,r1,r2 + 128: 10 01 11 32 evdotphihcssfaaw r0,r1,r2 + 12c: 10 01 11 33 evdotplohcssfaaw r0,r1,r2 + 130: 10 01 11 38 evdotphihcsmiaaw r0,r1,r2 + 134: 10 01 11 39 evdotplohcsmiaaw r0,r1,r2 + 138: 10 01 11 3a evdotphihcssfraaw r0,r1,r2 + 13c: 10 01 11 3b evdotplohcssfraaw r0,r1,r2 + 140: 10 01 11 40 evdotphausi r0,r1,r2 + 144: 10 01 11 41 evdotphassi r0,r1,r2 + 148: 10 01 11 42 evdotphasusi r0,r1,r2 + 14c: 10 01 11 43 evdotphassf r0,r1,r2 + 150: 10 01 11 47 evdotphsssf r0,r1,r2 + 154: 10 01 11 48 evdotphaumi r0,r1,r2 + 158: 10 01 11 49 evdotphasmi r0,r1,r2 + 15c: 10 01 11 4a evdotphasumi r0,r1,r2 + 160: 10 01 11 4b evdotphassfr r0,r1,r2 + 164: 10 01 11 4d evdotphssmi r0,r1,r2 + 168: 10 01 11 4f evdotphsssfr r0,r1,r2 + 16c: 10 01 11 50 evdotphausiaaw3 r0,r1,r2 + 170: 10 01 11 51 evdotphassiaaw3 r0,r1,r2 + 174: 10 01 11 52 evdotphasusiaaw3 r0,r1,r2 + 178: 10 01 11 53 evdotphassfaaw3 r0,r1,r2 + 17c: 10 01 11 55 evdotphsssiaaw3 r0,r1,r2 + 180: 10 01 11 57 evdotphsssfaaw3 r0,r1,r2 + 184: 10 01 11 58 evdotphaumiaaw3 r0,r1,r2 + 188: 10 01 11 59 evdotphasmiaaw3 r0,r1,r2 + 18c: 10 01 11 5a evdotphasumiaaw3 r0,r1,r2 + 190: 10 01 11 5b evdotphassfraaw3 r0,r1,r2 + 194: 10 01 11 5d evdotphssmiaaw3 r0,r1,r2 + 198: 10 01 11 5f evdotphsssfraaw3 r0,r1,r2 + 19c: 10 01 11 60 evdotphausia r0,r1,r2 + 1a0: 10 01 11 61 evdotphassia r0,r1,r2 + 1a4: 10 01 11 62 evdotphasusia r0,r1,r2 + 1a8: 10 01 11 63 evdotphassfa r0,r1,r2 + 1ac: 10 01 11 67 evdotphsssfa r0,r1,r2 + 1b0: 10 01 11 68 evdotphaumia r0,r1,r2 + 1b4: 10 01 11 69 evdotphasmia r0,r1,r2 + 1b8: 10 01 11 6a evdotphasumia r0,r1,r2 + 1bc: 10 01 11 6b evdotphassfra r0,r1,r2 + 1c0: 10 01 11 6d evdotphssmia r0,r1,r2 + 1c4: 10 01 11 6f evdotphsssfra r0,r1,r2 + 1c8: 10 01 11 70 evdotphausiaaw r0,r1,r2 + 1cc: 10 01 11 71 evdotphassiaaw r0,r1,r2 + 1d0: 10 01 11 72 evdotphasusiaaw r0,r1,r2 + 1d4: 10 01 11 73 evdotphassfaaw r0,r1,r2 + 1d8: 10 01 11 75 evdotphsssiaaw r0,r1,r2 + 1dc: 10 01 11 77 evdotphsssfaaw r0,r1,r2 + 1e0: 10 01 11 78 evdotphaumiaaw r0,r1,r2 + 1e4: 10 01 11 79 evdotphasmiaaw r0,r1,r2 + 1e8: 10 01 11 7a evdotphasumiaaw r0,r1,r2 + 1ec: 10 01 11 7b evdotphassfraaw r0,r1,r2 + 1f0: 10 01 11 7d evdotphssmiaaw r0,r1,r2 + 1f4: 10 01 11 7f evdotphsssfraaw r0,r1,r2 + 1f8: 10 01 11 80 evdotp4hgaumi r0,r1,r2 + 1fc: 10 01 11 81 evdotp4hgasmi r0,r1,r2 + 200: 10 01 11 82 evdotp4hgasumi r0,r1,r2 + 204: 10 01 11 83 evdotp4hgasmf r0,r1,r2 + 208: 10 01 11 84 evdotp4hgssmi r0,r1,r2 + 20c: 10 01 11 85 evdotp4hgssmf r0,r1,r2 + 210: 10 01 11 86 evdotp4hxgasmi r0,r1,r2 + 214: 10 01 11 87 evdotp4hxgasmf r0,r1,r2 + 218: 10 01 11 88 evdotpbaumi r0,r1,r2 + 21c: 10 01 11 89 evdotpbasmi r0,r1,r2 + 220: 10 01 11 8a evdotpbasumi r0,r1,r2 + 224: 10 01 11 8e evdotp4hxgssmi r0,r1,r2 + 228: 10 01 11 8f evdotp4hxgssmf r0,r1,r2 + 22c: 10 01 11 90 evdotp4hgaumiaa3 r0,r1,r2 + 230: 10 01 11 91 evdotp4hgasmiaa3 r0,r1,r2 + 234: 10 01 11 92 evdotp4hgasumiaa3 r0,r1,r2 + 238: 10 01 11 93 evdotp4hgasmfaa3 r0,r1,r2 + 23c: 10 01 11 94 evdotp4hgssmiaa3 r0,r1,r2 + 240: 10 01 11 95 evdotp4hgssmfaa3 r0,r1,r2 + 244: 10 01 11 96 evdotp4hxgasmiaa3 r0,r1,r2 + 248: 10 01 11 97 evdotp4hxgasmfaa3 r0,r1,r2 + 24c: 10 01 11 98 evdotpbaumiaaw3 r0,r1,r2 + 250: 10 01 11 99 evdotpbasmiaaw3 r0,r1,r2 + 254: 10 01 11 9a evdotpbasumiaaw3 r0,r1,r2 + 258: 10 01 11 9e evdotp4hxgssmiaa3 r0,r1,r2 + 25c: 10 01 11 9f evdotp4hxgssmfaa3 r0,r1,r2 + 260: 10 01 11 a0 evdotp4hgaumia r0,r1,r2 + 264: 10 01 11 a1 evdotp4hgasmia r0,r1,r2 + 268: 10 01 11 a2 evdotp4hgasumia r0,r1,r2 + 26c: 10 01 11 a3 evdotp4hgasmfa r0,r1,r2 + 270: 10 01 11 a4 evdotp4hgssmia r0,r1,r2 + 274: 10 01 11 a5 evdotp4hgssmfa r0,r1,r2 + 278: 10 01 11 a6 evdotp4hxgasmia r0,r1,r2 + 27c: 10 01 11 a7 evdotp4hxgasmfa r0,r1,r2 + 280: 10 01 11 a8 evdotpbaumia r0,r1,r2 + 284: 10 01 11 a9 evdotpbasmia r0,r1,r2 + 288: 10 01 11 aa evdotpbasumia r0,r1,r2 + 28c: 10 01 11 ae evdotp4hxgssmia r0,r1,r2 + 290: 10 01 11 af evdotp4hxgssmfa r0,r1,r2 + 294: 10 01 11 b0 evdotp4hgaumiaa r0,r1,r2 + 298: 10 01 11 b1 evdotp4hgasmiaa r0,r1,r2 + 29c: 10 01 11 b2 evdotp4hgasumiaa r0,r1,r2 + 2a0: 10 01 11 b3 evdotp4hgasmfaa r0,r1,r2 + 2a4: 10 01 11 b4 evdotp4hgssmiaa r0,r1,r2 + 2a8: 10 01 11 b5 evdotp4hgssmfaa r0,r1,r2 + 2ac: 10 01 11 b6 evdotp4hxgasmiaa r0,r1,r2 + 2b0: 10 01 11 b7 evdotp4hxgasmfaa r0,r1,r2 + 2b4: 10 01 11 b8 evdotpbaumiaaw r0,r1,r2 + 2b8: 10 01 11 b9 evdotpbasmiaaw r0,r1,r2 + 2bc: 10 01 11 ba evdotpbasumiaaw r0,r1,r2 + 2c0: 10 01 11 be evdotp4hxgssmiaa r0,r1,r2 + 2c4: 10 01 11 bf evdotp4hxgssmfaa r0,r1,r2 + 2c8: 10 01 11 c0 evdotpwausi r0,r1,r2 + 2cc: 10 01 11 c1 evdotpwassi r0,r1,r2 + 2d0: 10 01 11 c2 evdotpwasusi r0,r1,r2 + 2d4: 10 01 11 c8 evdotpwaumi r0,r1,r2 + 2d8: 10 01 11 c9 evdotpwasmi r0,r1,r2 + 2dc: 10 01 11 ca evdotpwasumi r0,r1,r2 + 2e0: 10 01 11 cd evdotpwssmi r0,r1,r2 + 2e4: 10 01 11 d0 evdotpwausiaa3 r0,r1,r2 + 2e8: 10 01 11 d1 evdotpwassiaa3 r0,r1,r2 + 2ec: 10 01 11 d2 evdotpwasusiaa3 r0,r1,r2 + 2f0: 10 01 11 d5 evdotpwsssiaa3 r0,r1,r2 + 2f4: 10 01 11 d8 evdotpwaumiaa3 r0,r1,r2 + 2f8: 10 01 11 d9 evdotpwasmiaa3 r0,r1,r2 + 2fc: 10 01 11 da evdotpwasumiaa3 r0,r1,r2 + 300: 10 01 11 dd evdotpwssmiaa3 r0,r1,r2 + 304: 10 01 11 e0 evdotpwausia r0,r1,r2 + 308: 10 01 11 e1 evdotpwassia r0,r1,r2 + 30c: 10 01 11 e2 evdotpwasusia r0,r1,r2 + 310: 10 01 11 e8 evdotpwaumia r0,r1,r2 + 314: 10 01 11 e9 evdotpwasmia r0,r1,r2 + 318: 10 01 11 ea evdotpwasumia r0,r1,r2 + 31c: 10 01 11 ed evdotpwssmia r0,r1,r2 + 320: 10 01 11 f0 evdotpwausiaa r0,r1,r2 + 324: 10 01 11 f1 evdotpwassiaa r0,r1,r2 + 328: 10 01 11 f2 evdotpwasusiaa r0,r1,r2 + 32c: 10 01 11 f5 evdotpwsssiaa r0,r1,r2 + 330: 10 01 11 f8 evdotpwaumiaa r0,r1,r2 + 334: 10 01 11 f9 evdotpwasmiaa r0,r1,r2 + 338: 10 01 11 fa evdotpwasumiaa r0,r1,r2 + 33c: 10 01 11 fd evdotpwssmiaa r0,r1,r2 + 340: 10 1f 12 03 evaddib r0,r2,31 + 344: 10 1f 12 01 evaddih r0,r2,31 + 348: 10 1f 12 05 evsubifh r0,31,r2 + 34c: 10 1f 12 07 evsubifb r0,31,r2 + 350: 10 01 12 08 evabsb r0,r1 + 354: 10 01 22 08 evabsh r0,r1 + 358: 10 01 32 08 evabsd r0,r1 + 35c: 10 01 42 08 evabss r0,r1 + 360: 10 01 52 08 evabsbs r0,r1 + 364: 10 01 62 08 evabshs r0,r1 + 368: 10 01 72 08 evabsds r0,r1 + 36c: 10 01 0a 09 evnegwo r0,r1 + 370: 10 01 12 09 evnegb r0,r1 + 374: 10 01 1a 09 evnegbo r0,r1 + 378: 10 01 22 09 evnegh r0,r1 + 37c: 10 01 2a 09 evnegho r0,r1 + 380: 10 01 32 09 evnegd r0,r1 + 384: 10 01 42 09 evnegs r0,r1 + 388: 10 01 4a 09 evnegwos r0,r1 + 38c: 10 01 52 09 evnegbs r0,r1 + 390: 10 01 5a 09 evnegbos r0,r1 + 394: 10 01 62 09 evneghs r0,r1 + 398: 10 01 6a 09 evneghos r0,r1 + 39c: 10 01 72 09 evnegds r0,r1 + 3a0: 10 01 0a 0a evextzb r0,r1 + 3a4: 10 01 22 0a evextsbh r0,r1 + 3a8: 10 01 32 0b evextsw r0,r1 + 3ac: 10 01 02 0c evrndwh r0,r1 + 3b0: 10 01 22 0c evrndhb r0,r1 + 3b4: 10 01 32 0c evrnddw r0,r1 + 3b8: 10 01 42 0c evrndwhus r0,r1 + 3bc: 10 01 4a 0c evrndwhss r0,r1 + 3c0: 10 01 62 0c evrndhbus r0,r1 + 3c4: 10 01 6a 0c evrndhbss r0,r1 + 3c8: 10 01 72 0c evrnddwus r0,r1 + 3cc: 10 01 7a 0c evrnddwss r0,r1 + 3d0: 10 01 82 0c evrndwnh r0,r1 + 3d4: 10 01 a2 0c evrndhnb r0,r1 + 3d8: 10 01 b2 0c evrnddnw r0,r1 + 3dc: 10 01 c2 0c evrndwnhus r0,r1 + 3e0: 10 01 ca 0c evrndwnhss r0,r1 + 3e4: 10 01 e2 0c evrndhnbus r0,r1 + 3e8: 10 01 ea 0c evrndhnbss r0,r1 + 3ec: 10 01 f2 0c evrnddnwus r0,r1 + 3f0: 10 01 fa 0c evrnddnwss r0,r1 + 3f4: 10 01 22 0d evcntlzh r0,r1 + 3f8: 10 01 22 0e evcntlsh r0,r1 + 3fc: 10 01 d2 0e evpopcntb r0,r1 + 400: 10 01 12 10 circinc r0,r1,r2 + 404: 10 01 02 1c evunpkhibui r0,r1 + 408: 10 01 0a 1c evunpkhibsi r0,r1 + 40c: 10 01 12 1c evunpkhihui r0,r1 + 410: 10 01 1a 1c evunpkhihsi r0,r1 + 414: 10 01 22 1c evunpklobui r0,r1 + 418: 10 01 2a 1c evunpklobsi r0,r1 + 41c: 10 01 32 1c evunpklohui r0,r1 + 420: 10 01 3a 1c evunpklohsi r0,r1 + 424: 10 01 42 1c evunpklohf r0,r1 + 428: 10 01 4a 1c evunpkhihf r0,r1 + 42c: 10 01 62 1c evunpklowgsf r0,r1 + 430: 10 01 6a 1c evunpkhiwgsf r0,r1 + 434: 10 01 82 1c evsatsduw r0,r1 + 438: 10 01 8a 1c evsatsdsw r0,r1 + 43c: 10 01 92 1c evsatshub r0,r1 + 440: 10 01 9a 1c evsatshsb r0,r1 + 444: 10 01 a2 1c evsatuwuh r0,r1 + 448: 10 01 aa 1c evsatswsh r0,r1 + 44c: 10 01 b2 1c evsatswuh r0,r1 + 450: 10 01 ba 1c evsatuhub r0,r1 + 454: 10 01 c2 1c evsatuduw r0,r1 + 458: 10 01 ca 1c evsatuwsw r0,r1 + 45c: 10 01 d2 1c evsatshuh r0,r1 + 460: 10 01 da 1c evsatuhsh r0,r1 + 464: 10 01 e2 1c evsatswuw r0,r1 + 468: 10 01 ea 1c evsatswgsdf r0,r1 + 46c: 10 01 f2 1c evsatsbub r0,r1 + 470: 10 01 fa 1c evsatubsb r0,r1 + 474: 10 01 02 1d evmaxhpuw r0,r1 + 478: 10 01 0a 1d evmaxhpsw r0,r1 + 47c: 10 01 22 1d evmaxbpuh r0,r1 + 480: 10 01 2a 1d evmaxbpsh r0,r1 + 484: 10 01 32 1d evmaxwpud r0,r1 + 488: 10 01 3a 1d evmaxwpsd r0,r1 + 48c: 10 01 42 1d evminhpuw r0,r1 + 490: 10 01 4a 1d evminhpsw r0,r1 + 494: 10 01 62 1d evminbpuh r0,r1 + 498: 10 01 6a 1d evminbpsh r0,r1 + 49c: 10 01 72 1d evminwpud r0,r1 + 4a0: 10 01 7a 1d evminwpsd r0,r1 + 4a4: 10 01 12 1f evmaxmagws r0,r1,r2 + 4a8: 10 01 12 25 evsl r0,r1,r2 + 4ac: 10 01 fa 27 evsli r0,r1,31 + 4b0: 10 10 0a 29 evsplatie r0,-16 + 4b4: 10 10 12 29 evsplatib r0,-16 + 4b8: 10 10 1a 29 evsplatibe r0,-16 + 4bc: 10 10 22 29 evsplatih r0,-16 + 4c0: 10 10 2a 29 evsplatihe r0,-16 + 4c4: 10 10 32 29 evsplatid r0,-16 + 4c8: 10 10 82 29 evsplatia r0,-16 + 4cc: 10 10 8a 29 evsplatiea r0,-16 + 4d0: 10 10 92 29 evsplatiba r0,-16 + 4d4: 10 10 9a 29 evsplatibea r0,-16 + 4d8: 10 10 a2 29 evsplatiha r0,-16 + 4dc: 10 10 aa 29 evsplatihea r0,-16 + 4e0: 10 10 b2 29 evsplatida r0,-16 + 4e4: 10 10 0a 2b evsplatfio r0,-16 + 4e8: 10 10 12 2b evsplatfib r0,-16 + 4ec: 10 10 1a 2b evsplatfibo r0,-16 + 4f0: 10 10 22 2b evsplatfih r0,-16 + 4f4: 10 10 2a 2b evsplatfiho r0,-16 + 4f8: 10 10 32 2b evsplatfid r0,-16 + 4fc: 10 10 82 2b evsplatfia r0,-16 + 500: 10 10 8a 2b evsplatfioa r0,-16 + 504: 10 10 92 2b evsplatfiba r0,-16 + 508: 10 10 9a 2b evsplatfiboa r0,-16 + 50c: 10 10 a2 2b evsplatfiha r0,-16 + 510: 10 10 aa 2b evsplatfihoa r0,-16 + 514: 10 10 b2 2b evsplatfida r0,-16 + 518: 10 21 12 30 evcmpgtdu cr0,r1,r2 + 51c: 10 21 12 31 evcmpgtds cr0,r1,r2 + 520: 10 21 12 32 evcmpltdu cr0,r1,r2 + 524: 10 21 12 33 evcmpltds cr0,r1,r2 + 528: 10 21 12 34 evcmpeqd cr0,r1,r2 + 52c: 10 01 12 38 evswapbhilo r0,r1,r2 + 530: 10 01 12 39 evswapblohi r0,r1,r2 + 534: 10 01 12 3a evswaphhilo r0,r1,r2 + 538: 10 01 12 3b evswaphlohi r0,r1,r2 + 53c: 10 01 12 3c evswaphe r0,r1,r2 + 540: 10 01 12 3d evswaphhi r0,r1,r2 + 544: 10 01 12 3e evswaphlo r0,r1,r2 + 548: 10 01 12 3f evswapho r0,r1,r2 + 54c: 10 01 fa 49 evinsb r0,r1,7,7 + 550: 10 01 fa 4b evxtrb r0,r1,7,7 + 554: 10 01 62 4c evsplath r0,r1,3 + 558: 10 01 f2 4c evsplatb r0,r1,7 + 55c: 10 01 7a 4d evinsh r0,r1,3,3 + 560: 10 01 7a 4e evclrbe r0,r1,15 + 564: 10 01 fa 4e evclrbo r0,r1,15 + 568: 10 01 fa 4f evclrh r0,r1,15 + 56c: 10 01 7a 4f evxtrh r0,r1,3,3 + 570: 10 01 12 50 evselbitm0 r0,r1,r2 + 574: 10 01 12 51 evselbitm1 r0,r1,r2 + 578: 10 01 12 52 evselbit r0,r1,r2 + 57c: 10 01 12 54 evperm r0,r1,r2 + 580: 10 01 12 55 evperm2 r0,r1,r2 + 584: 10 01 12 56 evperm3 r0,r1,r2 + 588: 10 01 12 5f evxtrd r0,r1,r2,7 + 58c: 10 01 12 60 evsrbu r0,r1,r2 + 590: 10 01 12 61 evsrbs r0,r1,r2 + 594: 10 01 3a 62 evsrbiu r0,r1,7 + 598: 10 01 3a 63 evsrbis r0,r1,7 + 59c: 10 01 12 64 evslb r0,r1,r2 + 5a0: 10 01 12 65 evrlb r0,r1,r2 + 5a4: 10 01 3a 66 evslbi r0,r1,7 + 5a8: 10 01 3a 67 evrlbi r0,r1,7 + 5ac: 10 01 12 68 evsrhu r0,r1,r2 + 5b0: 10 01 12 69 evsrhs r0,r1,r2 + 5b4: 10 01 7a 6a evsrhiu r0,r1,15 + 5b8: 10 01 7a 6b evsrhis r0,r1,15 + 5bc: 10 01 12 6c evslh r0,r1,r2 + 5c0: 10 01 12 6d evrlh r0,r1,r2 + 5c4: 10 01 7a 6e evslhi r0,r1,15 + 5c8: 10 01 7a 6f evrlhi r0,r1,15 + 5cc: 10 01 12 70 evsru r0,r1,r2 + 5d0: 10 01 12 71 evsrs r0,r1,r2 + 5d4: 10 01 fa 72 evsriu r0,r1,31 + 5d8: 10 01 fa 73 evsris r0,r1,31 + 5dc: 10 01 12 74 evlvsl r0,r1,r2 + 5e0: 10 01 12 75 evlvsr r0,r1,r2 + 5e4: 10 01 3a 77 evsroiu r0,r1,7 + 5e8: 10 01 7a 77 evsrois r0,r1,7 + 5ec: 10 01 ba 77 evsloi r0,r1,7 + 5f0: 10 01 02 87 evfssqrt r0,r1 + 5f4: 10 04 12 91 evfscfh r0,r2 + 5f8: 10 04 12 95 evfscth r0,r2 + 5fc: 10 01 12 a0 evfsmax r0,r1,r2 + 600: 10 01 12 a1 evfsmin r0,r1,r2 + 604: 10 01 12 a2 evfsaddsub r0,r1,r2 + 608: 10 01 12 a3 evfssubadd r0,r1,r2 + 60c: 10 01 12 a4 evfssum r0,r1,r2 + 610: 10 01 12 a5 evfsdiff r0,r1,r2 + 614: 10 01 12 a6 evfssumdiff r0,r1,r2 + 618: 10 01 12 a7 evfsdiffsum r0,r1,r2 + 61c: 10 01 12 a8 evfsaddx r0,r1,r2 + 620: 10 01 12 a9 evfssubx r0,r1,r2 + 624: 10 01 12 aa evfsaddsubx r0,r1,r2 + 628: 10 01 12 ab evfssubaddx r0,r1,r2 + 62c: 10 01 12 ac evfsmulx r0,r1,r2 + 630: 10 01 12 ae evfsmule r0,r1,r2 + 634: 10 01 12 af evfsmulo r0,r1,r2 + 638: 10 01 13 06 evldbx r0,r1,r2 + 63c: 10 01 0b 07 evldb r0,8\(r1\) + 640: 10 01 13 0a evlhhsplathx r0,r1,r2 + 644: 10 01 0b 0b evlhhsplath r0,2\(r1\) + 648: 10 01 13 12 evlwbsplatwx r0,r1,r2 + 64c: 10 01 0b 13 evlwbsplatw r0,4\(r1\) + 650: 10 01 13 1a evlwhsplatwx r0,r1,r2 + 654: 10 01 0b 1b evlwhsplatw r0,4\(r1\) + 658: 10 01 13 1e evlbbsplatbx r0,r1,r2 + 65c: 10 01 0b 1f evlbbsplatb r0,1\(r1\) + 660: 10 01 13 26 evstdbx r0,r1,r2 + 664: 10 01 0b 27 evstdb r0,8\(r1\) + 668: 10 01 13 2a evlwbex r0,r1,r2 + 66c: 10 01 0b 2b evlwbe r0,4\(r1\) + 670: 10 01 13 2c evlwboux r0,r1,r2 + 674: 10 01 0b 2d evlwbou r0,4\(r1\) + 678: 10 01 13 2e evlwbosx r0,r1,r2 + 67c: 10 01 0b 2f evlwbos r0,4\(r1\) + 680: 10 01 13 32 evstwbex r0,r1,r2 + 684: 10 01 0b 33 evstwbe r0,4\(r1\) + 688: 10 01 13 36 evstwbox r0,r1,r2 + 68c: 10 01 0b 37 evstwbo r0,4\(r1\) + 690: 10 01 13 3a evstwbx r0,r1,r2 + 694: 10 01 0b 3b evstwb r0,4\(r1\) + 698: 10 01 13 3e evsthbx r0,r1,r2 + 69c: 10 01 0b 3f evsthb r0,2\(r1\) + 6a0: 10 01 13 40 evlddmx r0,r1,r2 + 6a4: 10 01 0b 41 evlddu r0,8\(r1\) + 6a8: 10 01 13 42 evldwmx r0,r1,r2 + 6ac: 10 01 0b 43 evldwu r0,8\(r1\) + 6b0: 10 01 13 44 evldhmx r0,r1,r2 + 6b4: 10 01 0b 45 evldhu r0,8\(r1\) + 6b8: 10 01 13 46 evldbmx r0,r1,r2 + 6bc: 10 01 0b 47 evldbu r0,8\(r1\) + 6c0: 10 01 13 48 evlhhesplatmx r0,r1,r2 + 6c4: 10 01 0b 49 evlhhesplatu r0,2\(r1\) + 6c8: 10 01 13 4a evlhhsplathmx r0,r1,r2 + 6cc: 10 01 0b 4b evlhhsplathu r0,2\(r1\) + 6d0: 10 01 13 4c evlhhousplatmx r0,r1,r2 + 6d4: 10 01 0b 4d evlhhousplatu r0,2\(r1\) + 6d8: 10 01 13 4e evlhhossplatmx r0,r1,r2 + 6dc: 10 01 0b 4f evlhhossplatu r0,2\(r1\) + 6e0: 10 01 13 50 evlwhemx r0,r1,r2 + 6e4: 10 01 0b 51 evlwheu r0,4\(r1\) + 6e8: 10 01 13 52 evlwbsplatwmx r0,r1,r2 + 6ec: 10 01 0b 53 evlwbsplatwu r0,4\(r1\) + 6f0: 10 01 13 54 evlwhoumx r0,r1,r2 + 6f4: 10 01 0b 55 evlwhouu r0,4\(r1\) + 6f8: 10 01 13 56 evlwhosmx r0,r1,r2 + 6fc: 10 01 0b 57 evlwhosu r0,4\(r1\) + 700: 10 01 13 58 evlwwsplatmx r0,r1,r2 + 704: 10 01 0b 59 evlwwsplatu r0,4\(r1\) + 708: 10 01 13 5a evlwhsplatwmx r0,r1,r2 + 70c: 10 01 0b 5b evlwhsplatwu r0,4\(r1\) + 710: 10 01 13 5c evlwhsplatmx r0,r1,r2 + 714: 10 01 0b 5d evlwhsplatu r0,4\(r1\) + 718: 10 01 13 5e evlbbsplatbmx r0,r1,r2 + 71c: 10 01 0b 5f evlbbsplatbu r0,1\(r1\) + 720: 10 01 13 60 evstddmx r0,r1,r2 + 724: 10 01 0b 61 evstddu r0,8\(r1\) + 728: 10 01 13 62 evstdwmx r0,r1,r2 + 72c: 10 01 0b 63 evstdwu r0,8\(r1\) + 730: 10 01 13 64 evstdhmx r0,r1,r2 + 734: 10 01 0b 65 evstdhu r0,8\(r1\) + 738: 10 01 13 66 evstdbmx r0,r1,r2 + 73c: 10 01 0b 67 evstdbu r0,8\(r1\) + 740: 10 01 13 6a evlwbemx r0,r1,r2 + 744: 10 01 0b 6b evlwbeu r0,4\(r1\) + 748: 10 01 13 6c evlwboumx r0,r1,r2 + 74c: 10 01 0b 6d evlwbouu r0,4\(r1\) + 750: 10 01 13 6e evlwbosmx r0,r1,r2 + 754: 10 01 0b 6f evlwbosu r0,4\(r1\) + 758: 10 01 13 70 evstwhemx r0,r1,r2 + 75c: 10 01 0b 71 evstwheu r0,4\(r1\) + 760: 10 01 13 72 evstwbemx r0,r1,r2 + 764: 10 01 0b 73 evstwbeu r0,4\(r1\) + 768: 10 01 13 74 evstwhomx r0,r1,r2 + 76c: 10 01 0b 75 evstwhou r0,4\(r1\) + 770: 10 01 13 76 evstwbomx r0,r1,r2 + 774: 10 01 0b 77 evstwbou r0,4\(r1\) + 778: 10 01 13 78 evstwwemx r0,r1,r2 + 77c: 10 01 0b 79 evstwweu r0,4\(r1\) + 780: 10 01 13 7a evstwbmx r0,r1,r2 + 784: 10 01 0b 7b evstwbu r0,4\(r1\) + 788: 10 01 13 7c evstwwomx r0,r1,r2 + 78c: 10 01 0b 7d evstwwou r0,4\(r1\) + 790: 10 01 13 7e evsthbmx r0,r1,r2 + 794: 10 01 0b 7f evsthbu r0,2\(r1\) + 798: 10 01 14 00 evmhusi r0,r1,r2 + 79c: 10 01 14 01 evmhssi r0,r1,r2 + 7a0: 10 01 14 02 evmhsusi r0,r1,r2 + 7a4: 10 01 14 04 evmhssf r0,r1,r2 + 7a8: 10 01 14 05 evmhumi r0,r1,r2 + 7ac: 10 01 14 06 evmhssfr r0,r1,r2 + 7b0: 10 01 14 0a evmhesumi r0,r1,r2 + 7b4: 10 01 14 0e evmhosumi r0,r1,r2 + 7b8: 10 01 14 18 evmbeumi r0,r1,r2 + 7bc: 10 01 14 19 evmbesmi r0,r1,r2 + 7c0: 10 01 14 1a evmbesumi r0,r1,r2 + 7c4: 10 01 14 1c evmboumi r0,r1,r2 + 7c8: 10 01 14 1d evmbosmi r0,r1,r2 + 7cc: 10 01 14 1e evmbosumi r0,r1,r2 + 7d0: 10 01 14 2a evmhesumia r0,r1,r2 + 7d4: 10 01 14 2e evmhosumia r0,r1,r2 + 7d8: 10 01 14 38 evmbeumia r0,r1,r2 + 7dc: 10 01 14 39 evmbesmia r0,r1,r2 + 7e0: 10 01 14 3a evmbesumia r0,r1,r2 + 7e4: 10 01 14 3c evmboumia r0,r1,r2 + 7e8: 10 01 14 3d evmbosmia r0,r1,r2 + 7ec: 10 01 14 3e evmbosumia r0,r1,r2 + 7f0: 10 01 14 40 evmwusiw r0,r1,r2 + 7f4: 10 01 14 41 evmwssiw r0,r1,r2 + 7f8: 10 01 14 46 evmwhssfr r0,r1,r2 + 7fc: 10 01 14 56 evmwehgsmfr r0,r1,r2 + 800: 10 01 14 57 evmwehgsmf r0,r1,r2 + 804: 10 01 14 5e evmwohgsmfr r0,r1,r2 + 808: 10 01 14 5f evmwohgsmf r0,r1,r2 + 80c: 10 01 14 66 evmwhssfra r0,r1,r2 + 810: 10 01 14 76 evmwehgsmfra r0,r1,r2 + 814: 10 01 14 77 evmwehgsmfa r0,r1,r2 + 818: 10 01 14 7e evmwohgsmfra r0,r1,r2 + 81c: 10 01 14 7f evmwohgsmfa r0,r1,r2 + 820: 10 01 04 80 evaddusiaa r0,r1 + 824: 10 01 04 81 evaddssiaa r0,r1 + 828: 10 01 04 82 evsubfusiaa r0,r1 + 82c: 10 01 04 83 evsubfssiaa r0,r1 + 830: 10 01 04 84 evaddsmiaa r0,r1 + 834: 10 01 04 86 evsubfsmiaa r0,r1 + 838: 10 01 14 88 evaddh r0,r1,r2 + 83c: 10 01 14 89 evaddhss r0,r1,r2 + 840: 10 01 14 8a evsubfh r0,r1,r2 + 844: 10 01 14 8b evsubfhss r0,r1,r2 + 848: 10 01 14 8c evaddhx r0,r1,r2 + 84c: 10 01 14 8d evaddhxss r0,r1,r2 + 850: 10 01 14 8e evsubfhx r0,r1,r2 + 854: 10 01 14 8f evsubfhxss r0,r1,r2 + 858: 10 01 14 90 evaddd r0,r1,r2 + 85c: 10 01 14 91 evadddss r0,r1,r2 + 860: 10 01 14 92 evsubfd r0,r1,r2 + 864: 10 01 14 93 evsubfdss r0,r1,r2 + 868: 10 01 14 94 evaddb r0,r1,r2 + 86c: 10 01 14 95 evaddbss r0,r1,r2 + 870: 10 01 14 96 evsubfb r0,r1,r2 + 874: 10 01 14 97 evsubfbss r0,r1,r2 + 878: 10 01 14 98 evaddsubfh r0,r1,r2 + 87c: 10 01 14 99 evaddsubfhss r0,r1,r2 + 880: 10 01 14 9a evsubfaddh r0,r1,r2 + 884: 10 01 14 9b evsubfaddhss r0,r1,r2 + 888: 10 01 14 9c evaddsubfhx r0,r1,r2 + 88c: 10 01 14 9d evaddsubfhxss r0,r1,r2 + 890: 10 01 14 9e evsubfaddhx r0,r1,r2 + 894: 10 01 14 9f evsubfaddhxss r0,r1,r2 + 898: 10 01 14 a0 evadddus r0,r1,r2 + 89c: 10 01 14 a1 evaddbus r0,r1,r2 + 8a0: 10 01 14 a2 evsubfdus r0,r1,r2 + 8a4: 10 01 14 a3 evsubfbus r0,r1,r2 + 8a8: 10 01 14 a4 evaddwus r0,r1,r2 + 8ac: 10 01 14 a5 evaddwxus r0,r1,r2 + 8b0: 10 01 14 a6 evsubfwus r0,r1,r2 + 8b4: 10 01 14 a7 evsubfwxus r0,r1,r2 + 8b8: 10 01 14 a8 evadd2subf2h r0,r1,r2 + 8bc: 10 01 14 a9 evadd2subf2hss r0,r1,r2 + 8c0: 10 01 14 aa evsubf2add2h r0,r1,r2 + 8c4: 10 01 14 ab evsubf2add2hss r0,r1,r2 + 8c8: 10 01 14 ac evaddhus r0,r1,r2 + 8cc: 10 01 14 ad evaddhxus r0,r1,r2 + 8d0: 10 01 14 ae evsubfhus r0,r1,r2 + 8d4: 10 01 14 af evsubfhxus r0,r1,r2 + 8d8: 10 01 14 b1 evaddwss r0,r1,r2 + 8dc: 10 01 14 b3 evsubfwss r0,r1,r2 + 8e0: 10 01 14 b4 evaddwx r0,r1,r2 + 8e4: 10 01 14 b5 evaddwxss r0,r1,r2 + 8e8: 10 01 14 b6 evsubfwx r0,r1,r2 + 8ec: 10 01 14 b7 evsubfwxss r0,r1,r2 + 8f0: 10 01 14 b8 evaddsubfw r0,r1,r2 + 8f4: 10 01 14 b9 evaddsubfwss r0,r1,r2 + 8f8: 10 01 14 ba evsubfaddw r0,r1,r2 + 8fc: 10 01 14 bb evsubfaddwss r0,r1,r2 + 900: 10 01 14 bc evaddsubfwx r0,r1,r2 + 904: 10 01 14 bd evaddsubfwxss r0,r1,r2 + 908: 10 01 14 be evsubfaddwx r0,r1,r2 + 90c: 10 01 14 bf evsubfaddwxss r0,r1,r2 + 910: 10 00 0c c4 evmar r0 + 914: 10 01 04 c5 evsumwu r0,r1 + 918: 10 01 0c c5 evsumws r0,r1 + 91c: 10 01 14 c5 evsum4bu r0,r1 + 920: 10 01 1c c5 evsum4bs r0,r1 + 924: 10 01 24 c5 evsum2hu r0,r1 + 928: 10 01 2c c5 evsum2hs r0,r1 + 92c: 10 01 34 c5 evdiff2his r0,r1 + 930: 10 01 3c c5 evsum2his r0,r1 + 934: 10 01 84 c5 evsumwua r0,r1 + 938: 10 01 8c c5 evsumwsa r0,r1 + 93c: 10 01 94 c5 evsum4bua r0,r1 + 940: 10 01 9c c5 evsum4bsa r0,r1 + 944: 10 01 a4 c5 evsum2hua r0,r1 + 948: 10 01 ac c5 evsum2hsa r0,r1 + 94c: 10 01 b4 c5 evdiff2hisa r0,r1 + 950: 10 01 bc c5 evsum2hisa r0,r1 + 954: 10 01 c4 c5 evsumwuaa r0,r1 + 958: 10 01 cc c5 evsumwsaa r0,r1 + 95c: 10 01 d4 c5 evsum4buaaw r0,r1 + 960: 10 01 dc c5 evsum4bsaaw r0,r1 + 964: 10 01 e4 c5 evsum2huaaw r0,r1 + 968: 10 01 ec c5 evsum2hsaaw r0,r1 + 96c: 10 01 f4 c5 evdiff2hisaaw r0,r1 + 970: 10 01 fc c5 evsum2hisaaw r0,r1 + 974: 10 01 14 cc evdivwsf r0,r1,r2 + 978: 10 01 14 cd evdivwuf r0,r1,r2 + 97c: 10 01 14 ce evdivs r0,r1,r2 + 980: 10 01 14 cf evdivu r0,r1,r2 + 984: 10 01 14 d0 evaddwegsi r0,r1,r2 + 988: 10 01 14 d1 evaddwegsf r0,r1,r2 + 98c: 10 01 14 d2 evsubfwegsi r0,r1,r2 + 990: 10 01 14 d3 evsubfwegsf r0,r1,r2 + 994: 10 01 14 d4 evaddwogsi r0,r1,r2 + 998: 10 01 14 d5 evaddwogsf r0,r1,r2 + 99c: 10 01 14 d6 evsubfwogsi r0,r1,r2 + 9a0: 10 01 14 d7 evsubfwogsf r0,r1,r2 + 9a4: 10 01 14 d8 evaddhhiuw r0,r1,r2 + 9a8: 10 01 14 d9 evaddhhisw r0,r1,r2 + 9ac: 10 01 14 da evsubfhhiuw r0,r1,r2 + 9b0: 10 01 14 db evsubfhhisw r0,r1,r2 + 9b4: 10 01 14 dc evaddhlouw r0,r1,r2 + 9b8: 10 01 14 dd evaddhlosw r0,r1,r2 + 9bc: 10 01 14 de evsubfhlouw r0,r1,r2 + 9c0: 10 01 14 df evsubfhlosw r0,r1,r2 + 9c4: 10 01 15 02 evmhesusiaaw r0,r1,r2 + 9c8: 10 01 15 06 evmhosusiaaw r0,r1,r2 + 9cc: 10 01 15 0a evmhesumiaaw r0,r1,r2 + 9d0: 10 01 15 0e evmhosumiaaw r0,r1,r2 + 9d4: 10 01 15 10 evmbeusiaah r0,r1,r2 + 9d8: 10 01 15 11 evmbessiaah r0,r1,r2 + 9dc: 10 01 15 12 evmbesusiaah r0,r1,r2 + 9e0: 10 01 15 14 evmbousiaah r0,r1,r2 + 9e4: 10 01 15 15 evmbossiaah r0,r1,r2 + 9e8: 10 01 15 16 evmbosusiaah r0,r1,r2 + 9ec: 10 01 15 18 evmbeumiaah r0,r1,r2 + 9f0: 10 01 15 19 evmbesmiaah r0,r1,r2 + 9f4: 10 01 15 1a evmbesumiaah r0,r1,r2 + 9f8: 10 01 15 1c evmboumiaah r0,r1,r2 + 9fc: 10 01 15 1d evmbosmiaah r0,r1,r2 + a00: 10 01 15 1e evmbosumiaah r0,r1,r2 + a04: 10 01 15 42 evmwlusiaaw3 r0,r1,r2 + a08: 10 01 15 43 evmwlssiaaw3 r0,r1,r2 + a0c: 10 01 15 44 evmwhssfraaw3 r0,r1,r2 + a10: 10 01 15 45 evmwhssfaaw3 r0,r1,r2 + a14: 10 01 15 46 evmwhssfraaw r0,r1,r2 + a18: 10 01 15 47 evmwhssfaaw r0,r1,r2 + a1c: 10 01 15 4a evmwlumiaaw3 r0,r1,r2 + a20: 10 01 15 4b evmwlsmiaaw3 r0,r1,r2 + a24: 10 01 15 50 evmwusiaa r0,r1,r2 + a28: 10 01 15 51 evmwssiaa r0,r1,r2 + a2c: 10 01 15 56 evmwehgsmfraa r0,r1,r2 + a30: 10 01 15 57 evmwehgsmfaa r0,r1,r2 + a34: 10 01 15 5e evmwohgsmfraa r0,r1,r2 + a38: 10 01 15 5f evmwohgsmfaa r0,r1,r2 + a3c: 10 01 15 82 evmhesusianw r0,r1,r2 + a40: 10 01 15 86 evmhosusianw r0,r1,r2 + a44: 10 01 15 8a evmhesumianw r0,r1,r2 + a48: 10 01 15 8e evmhosumianw r0,r1,r2 + a4c: 10 01 15 90 evmbeusianh r0,r1,r2 + a50: 10 01 15 91 evmbessianh r0,r1,r2 + a54: 10 01 15 92 evmbesusianh r0,r1,r2 + a58: 10 01 15 94 evmbousianh r0,r1,r2 + a5c: 10 01 15 95 evmbossianh r0,r1,r2 + a60: 10 01 15 96 evmbosusianh r0,r1,r2 + a64: 10 01 15 98 evmbeumianh r0,r1,r2 + a68: 10 01 15 99 evmbesmianh r0,r1,r2 + a6c: 10 01 15 9a evmbesumianh r0,r1,r2 + a70: 10 01 15 9c evmboumianh r0,r1,r2 + a74: 10 01 15 9d evmbosmianh r0,r1,r2 + a78: 10 01 15 9e evmbosumianh r0,r1,r2 + a7c: 10 01 15 c2 evmwlusianw3 r0,r1,r2 + a80: 10 01 15 c3 evmwlssianw3 r0,r1,r2 + a84: 10 01 15 c4 evmwhssfranw3 r0,r1,r2 + a88: 10 01 15 c5 evmwhssfanw3 r0,r1,r2 + a8c: 10 01 15 c6 evmwhssfranw r0,r1,r2 + a90: 10 01 15 c7 evmwhssfanw r0,r1,r2 + a94: 10 01 15 ca evmwlumianw3 r0,r1,r2 + a98: 10 01 15 cb evmwlsmianw3 r0,r1,r2 + a9c: 10 01 15 d0 evmwusian r0,r1,r2 + aa0: 10 01 15 d1 evmwssian r0,r1,r2 + aa4: 10 01 15 d6 evmwehgsmfran r0,r1,r2 + aa8: 10 01 15 d7 evmwehgsmfan r0,r1,r2 + aac: 10 01 15 de evmwohgsmfran r0,r1,r2 + ab0: 10 01 15 df evmwohgsmfan r0,r1,r2 + ab4: 10 01 16 00 evseteqb r0,r1,r2 + ab8: 10 01 16 01 evseteqb. r0,r1,r2 + abc: 10 01 16 02 evseteqh r0,r1,r2 + ac0: 10 01 16 03 evseteqh. r0,r1,r2 + ac4: 10 01 16 04 evseteqw r0,r1,r2 + ac8: 10 01 16 05 evseteqw. r0,r1,r2 + acc: 10 01 16 08 evsetgthu r0,r1,r2 + ad0: 10 01 16 09 evsetgthu. r0,r1,r2 + ad4: 10 01 16 0a evsetgths r0,r1,r2 + ad8: 10 01 16 0b evsetgths. r0,r1,r2 + adc: 10 01 16 0c evsetgtwu r0,r1,r2 + ae0: 10 01 16 0d evsetgtwu. r0,r1,r2 + ae4: 10 01 16 0e evsetgtws r0,r1,r2 + ae8: 10 01 16 0f evsetgtws. r0,r1,r2 + aec: 10 01 16 10 evsetgtbu r0,r1,r2 + af0: 10 01 16 11 evsetgtbu. r0,r1,r2 + af4: 10 01 16 12 evsetgtbs r0,r1,r2 + af8: 10 01 16 13 evsetgtbs. r0,r1,r2 + afc: 10 01 16 14 evsetltbu r0,r1,r2 + b00: 10 01 16 15 evsetltbu. r0,r1,r2 + b04: 10 01 16 16 evsetltbs r0,r1,r2 + b08: 10 01 16 17 evsetltbs. r0,r1,r2 + b0c: 10 01 16 18 evsetlthu r0,r1,r2 + b10: 10 01 16 19 evsetlthu. r0,r1,r2 + b14: 10 01 16 1a evsetlths r0,r1,r2 + b18: 10 01 16 1b evsetlths. r0,r1,r2 + b1c: 10 01 16 1c evsetltwu r0,r1,r2 + b20: 10 01 16 1d evsetltwu. r0,r1,r2 + b24: 10 01 16 1e evsetltws r0,r1,r2 + b28: 10 01 16 1f evsetltws. r0,r1,r2 + b2c: 10 01 16 20 evsaduw r0,r1,r2 + b30: 10 01 16 21 evsadsw r0,r1,r2 + b34: 10 01 16 22 evsad4ub r0,r1,r2 + b38: 10 01 16 23 evsad4sb r0,r1,r2 + b3c: 10 01 16 24 evsad2uh r0,r1,r2 + b40: 10 01 16 25 evsad2sh r0,r1,r2 + b44: 10 01 16 28 evsaduwa r0,r1,r2 + b48: 10 01 16 29 evsadswa r0,r1,r2 + b4c: 10 01 16 2a evsad4uba r0,r1,r2 + b50: 10 01 16 2b evsad4sba r0,r1,r2 + b54: 10 01 16 2c evsad2uha r0,r1,r2 + b58: 10 01 16 2d evsad2sha r0,r1,r2 + b5c: 10 01 16 30 evabsdifuw r0,r1,r2 + b60: 10 01 16 31 evabsdifsw r0,r1,r2 + b64: 10 01 16 32 evabsdifub r0,r1,r2 + b68: 10 01 16 33 evabsdifsb r0,r1,r2 + b6c: 10 01 16 34 evabsdifuh r0,r1,r2 + b70: 10 01 16 35 evabsdifsh r0,r1,r2 + b74: 10 01 16 38 evsaduwaa r0,r1,r2 + b78: 10 01 16 39 evsadswaa r0,r1,r2 + b7c: 10 01 16 3a evsad4ubaaw r0,r1,r2 + b80: 10 01 16 3b evsad4sbaaw r0,r1,r2 + b84: 10 01 16 3c evsad2uhaaw r0,r1,r2 + b88: 10 01 16 3d evsad2shaaw r0,r1,r2 + b8c: 10 01 16 40 evpkshubs r0,r1,r2 + b90: 10 01 16 41 evpkshsbs r0,r1,r2 + b94: 10 01 16 42 evpkswuhs r0,r1,r2 + b98: 10 01 16 43 evpkswshs r0,r1,r2 + b9c: 10 01 16 44 evpkuhubs r0,r1,r2 + ba0: 10 01 16 45 evpkuwuhs r0,r1,r2 + ba4: 10 01 16 46 evpkswshilvs r0,r1,r2 + ba8: 10 01 16 47 evpkswgshefrs r0,r1,r2 + bac: 10 01 16 48 evpkswshfrs r0,r1,r2 + bb0: 10 01 16 49 evpkswshilvfrs r0,r1,r2 + bb4: 10 01 16 4a evpksdswfrs r0,r1,r2 + bb8: 10 01 16 4b evpksdshefrs r0,r1,r2 + bbc: 10 01 16 4c evpkuduws r0,r1,r2 + bc0: 10 01 16 4d evpksdsws r0,r1,r2 + bc4: 10 01 16 4e evpkswgswfrs r0,r1,r2 + bc8: 10 01 16 50 evilveh r0,r1,r2 + bcc: 10 01 16 51 evilveoh r0,r1,r2 + bd0: 10 01 16 52 evilvhih r0,r1,r2 + bd4: 10 01 16 53 evilvhiloh r0,r1,r2 + bd8: 10 01 16 54 evilvloh r0,r1,r2 + bdc: 10 01 16 55 evilvlohih r0,r1,r2 + be0: 10 01 16 56 evilvoeh r0,r1,r2 + be4: 10 01 16 57 evilvoh r0,r1,r2 + be8: 10 01 16 58 evdlveb r0,r1,r2 + bec: 10 01 16 59 evdlveh r0,r1,r2 + bf0: 10 01 16 5a evdlveob r0,r1,r2 + bf4: 10 01 16 5b evdlveoh r0,r1,r2 + bf8: 10 01 16 5c evdlvob r0,r1,r2 + bfc: 10 01 16 5d evdlvoh r0,r1,r2 + c00: 10 01 16 5e evdlvoeb r0,r1,r2 + c04: 10 01 16 5f evdlvoeh r0,r1,r2 + c08: 10 01 16 60 evmaxbu r0,r1,r2 + c0c: 10 01 16 61 evmaxbs r0,r1,r2 + c10: 10 01 16 62 evmaxhu r0,r1,r2 + c14: 10 01 16 63 evmaxhs r0,r1,r2 + c18: 10 01 16 64 evmaxwu r0,r1,r2 + c1c: 10 01 16 65 evmaxws r0,r1,r2 + c20: 10 01 16 66 evmaxdu r0,r1,r2 + c24: 10 01 16 67 evmaxds r0,r1,r2 + c28: 10 01 16 68 evminbu r0,r1,r2 + c2c: 10 01 16 69 evminbs r0,r1,r2 + c30: 10 01 16 6a evminhu r0,r1,r2 + c34: 10 01 16 6b evminhs r0,r1,r2 + c38: 10 01 16 6c evminwu r0,r1,r2 + c3c: 10 01 16 6d evminws r0,r1,r2 + c40: 10 01 16 6e evmindu r0,r1,r2 + c44: 10 01 16 6f evminds r0,r1,r2 + c48: 10 01 16 70 evavgwu r0,r1,r2 + c4c: 10 01 16 71 evavgws r0,r1,r2 + c50: 10 01 16 72 evavgbu r0,r1,r2 + c54: 10 01 16 73 evavgbs r0,r1,r2 + c58: 10 01 16 74 evavghu r0,r1,r2 + c5c: 10 01 16 75 evavghs r0,r1,r2 + c60: 10 01 16 76 evavgdu r0,r1,r2 + c64: 10 01 16 77 evavgds r0,r1,r2 + c68: 10 01 16 78 evavgwur r0,r1,r2 + c6c: 10 01 16 79 evavgwsr r0,r1,r2 + c70: 10 01 16 7a evavgbur r0,r1,r2 + c74: 10 01 16 7b evavgbsr r0,r1,r2 + c78: 10 01 16 7c evavghur r0,r1,r2 + c7c: 10 01 16 7d evavghsr r0,r1,r2 + c80: 10 01 16 7e evavgdur r0,r1,r2 + c84: 10 01 16 7f evavgdsr r0,r1,r2 + c88: 10 01 11 4d evdotphssmi r0,r1,r2 + c8c: 10 01 11 6d evdotphssmia r0,r1,r2 + c90: 10 01 11 cd evdotpwssmi r0,r1,r2 + c94: 10 01 11 ed evdotpwssmia r0,r1,r2 diff --git a/gas/testsuite/gas/ppc/spe2.s b/gas/testsuite/gas/ppc/spe2.s new file mode 100644 index 0000000..37b6cdb --- /dev/null +++ b/gas/testsuite/gas/ppc/spe2.s @@ -0,0 +1,834 @@ +# PA SPE2 instructions +# Testcase for CMPE200GCC-5, CMPE200GCC-62 + + .section ".text" + + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ UIMM, 31 + .equ UIMM_LT8, 7 + .equ UIMM_LT16, 15 + .equ UIMM_1, 1 + .equ UIMM_2, 2 + .equ UIMM_4, 4 + .equ UIMM_8, 8 + .equ SIMM, -16 + .equ crD, 0 + .equ nnn, 7 + .equ bbb, 7 + .equ dd, 3 + .equ Ddd, 7 + .equ hh, 3 + .equ mask, 15 + .equ offset, 7 + + evdotpwcssi rD, rA, rB + evdotpwcsmi rD, rA, rB + evdotpwcssfr rD, rA, rB + evdotpwcssf rD, rA, rB + evdotpwgasmf rD, rA, rB + evdotpwxgasmf rD, rA, rB + evdotpwgasmfr rD, rA, rB + evdotpwxgasmfr rD, rA, rB + evdotpwgssmf rD, rA, rB + evdotpwxgssmf rD, rA, rB + evdotpwgssmfr rD, rA, rB + evdotpwxgssmfr rD, rA, rB + evdotpwcssiaaw3 rD, rA, rB + evdotpwcsmiaaw3 rD, rA, rB + evdotpwcssfraaw3 rD, rA, rB + evdotpwcssfaaw3 rD, rA, rB + evdotpwgasmfaa3 rD, rA, rB + evdotpwxgasmfaa3 rD, rA, rB + evdotpwgasmfraa3 rD, rA, rB + evdotpwxgasmfraa3 rD, rA, rB + evdotpwgssmfaa3 rD, rA, rB + evdotpwxgssmfaa3 rD, rA, rB + evdotpwgssmfraa3 rD, rA, rB + evdotpwxgssmfraa3 rD, rA, rB + evdotpwcssia rD, rA, rB + evdotpwcsmia rD, rA, rB + evdotpwcssfra rD, rA, rB + evdotpwcssfa rD, rA, rB + evdotpwgasmfa rD, rA, rB + evdotpwxgasmfa rD, rA, rB + evdotpwgasmfra rD, rA, rB + evdotpwxgasmfra rD, rA, rB + evdotpwgssmfa rD, rA, rB + evdotpwxgssmfa rD, rA, rB + evdotpwgssmfra rD, rA, rB + evdotpwxgssmfra rD, rA, rB + evdotpwcssiaaw rD, rA, rB + evdotpwcsmiaaw rD, rA, rB + evdotpwcssfraaw rD, rA, rB + evdotpwcssfaaw rD, rA, rB + evdotpwgasmfaa rD, rA, rB + evdotpwxgasmfaa rD, rA, rB + evdotpwgasmfraa rD, rA, rB + evdotpwxgasmfraa rD, rA, rB + evdotpwgssmfaa rD, rA, rB + evdotpwxgssmfaa rD, rA, rB + evdotpwgssmfraa rD, rA, rB + evdotpwxgssmfraa rD, rA, rB + evdotphihcssi rD, rA, rB + evdotplohcssi rD, rA, rB + evdotphihcssf rD, rA, rB + evdotplohcssf rD, rA, rB + evdotphihcsmi rD, rA, rB + evdotplohcsmi rD, rA, rB + evdotphihcssfr rD, rA, rB + evdotplohcssfr rD, rA, rB + evdotphihcssiaaw3 rD, rA, rB + evdotplohcssiaaw3 rD, rA, rB + evdotphihcssfaaw3 rD, rA, rB + evdotplohcssfaaw3 rD, rA, rB + evdotphihcsmiaaw3 rD, rA, rB + evdotplohcsmiaaw3 rD, rA, rB + evdotphihcssfraaw3 rD, rA, rB + evdotplohcssfraaw3 rD, rA, rB + evdotphihcssia rD, rA, rB + evdotplohcssia rD, rA, rB + evdotphihcssfa rD, rA, rB + evdotplohcssfa rD, rA, rB + evdotphihcsmia rD, rA, rB + evdotplohcsmia rD, rA, rB + evdotphihcssfra rD, rA, rB + evdotplohcssfra rD, rA, rB + evdotphihcssiaaw rD, rA, rB + evdotplohcssiaaw rD, rA, rB + evdotphihcssfaaw rD, rA, rB + evdotplohcssfaaw rD, rA, rB + evdotphihcsmiaaw rD, rA, rB + evdotplohcsmiaaw rD, rA, rB + evdotphihcssfraaw rD, rA, rB + evdotplohcssfraaw rD, rA, rB + evdotphausi rD, rA, rB + evdotphassi rD, rA, rB + evdotphasusi rD, rA, rB + evdotphassf rD, rA, rB + evdotphsssf rD, rA, rB + evdotphaumi rD, rA, rB + evdotphasmi rD, rA, rB + evdotphasumi rD, rA, rB + evdotphassfr rD, rA, rB + evdotphssmi rD, rA, rB + evdotphsssfr rD, rA, rB + evdotphausiaaw3 rD, rA, rB + evdotphassiaaw3 rD, rA, rB + evdotphasusiaaw3 rD, rA, rB + evdotphassfaaw3 rD, rA, rB + evdotphsssiaaw3 rD, rA, rB + evdotphsssfaaw3 rD, rA, rB + evdotphaumiaaw3 rD, rA, rB + evdotphasmiaaw3 rD, rA, rB + evdotphasumiaaw3 rD, rA, rB + evdotphassfraaw3 rD, rA, rB + evdotphssmiaaw3 rD, rA, rB + evdotphsssfraaw3 rD, rA, rB + evdotphausia rD, rA, rB + evdotphassia rD, rA, rB + evdotphasusia rD, rA, rB + evdotphassfa rD, rA, rB + evdotphsssfa rD, rA, rB + evdotphaumia rD, rA, rB + evdotphasmia rD, rA, rB + evdotphasumia rD, rA, rB + evdotphassfra rD, rA, rB + evdotphssmia rD, rA, rB + evdotphsssfra rD, rA, rB + evdotphausiaaw rD, rA, rB + evdotphassiaaw rD, rA, rB + evdotphasusiaaw rD, rA, rB + evdotphassfaaw rD, rA, rB + evdotphsssiaaw rD, rA, rB + evdotphsssfaaw rD, rA, rB + evdotphaumiaaw rD, rA, rB + evdotphasmiaaw rD, rA, rB + evdotphasumiaaw rD, rA, rB + evdotphassfraaw rD, rA, rB + evdotphssmiaaw rD, rA, rB + evdotphsssfraaw rD, rA, rB + evdotp4hgaumi rD, rA, rB + evdotp4hgasmi rD, rA, rB + evdotp4hgasumi rD, rA, rB + evdotp4hgasmf rD, rA, rB + evdotp4hgssmi rD, rA, rB + evdotp4hgssmf rD, rA, rB + evdotp4hxgasmi rD, rA, rB + evdotp4hxgasmf rD, rA, rB + evdotpbaumi rD, rA, rB + evdotpbasmi rD, rA, rB + evdotpbasumi rD, rA, rB + evdotp4hxgssmi rD, rA, rB + evdotp4hxgssmf rD, rA, rB + evdotp4hgaumiaa3 rD, rA, rB + evdotp4hgasmiaa3 rD, rA, rB + evdotp4hgasumiaa3 rD, rA, rB + evdotp4hgasmfaa3 rD, rA, rB + evdotp4hgssmiaa3 rD, rA, rB + evdotp4hgssmfaa3 rD, rA, rB + evdotp4hxgasmiaa3 rD, rA, rB + evdotp4hxgasmfaa3 rD, rA, rB + evdotpbaumiaaw3 rD, rA, rB + evdotpbasmiaaw3 rD, rA, rB + evdotpbasumiaaw3 rD, rA, rB + evdotp4hxgssmiaa3 rD, rA, rB + evdotp4hxgssmfaa3 rD, rA, rB + evdotp4hgaumia rD, rA, rB + evdotp4hgasmia rD, rA, rB + evdotp4hgasumia rD, rA, rB + evdotp4hgasmfa rD, rA, rB + evdotp4hgssmia rD, rA, rB + evdotp4hgssmfa rD, rA, rB + evdotp4hxgasmia rD, rA, rB + evdotp4hxgasmfa rD, rA, rB + evdotpbaumia rD, rA, rB + evdotpbasmia rD, rA, rB + evdotpbasumia rD, rA, rB + evdotp4hxgssmia rD, rA, rB + evdotp4hxgssmfa rD, rA, rB + evdotp4hgaumiaa rD, rA, rB + evdotp4hgasmiaa rD, rA, rB + evdotp4hgasumiaa rD, rA, rB + evdotp4hgasmfaa rD, rA, rB + evdotp4hgssmiaa rD, rA, rB + evdotp4hgssmfaa rD, rA, rB + evdotp4hxgasmiaa rD, rA, rB + evdotp4hxgasmfaa rD, rA, rB + evdotpbaumiaaw rD, rA, rB + evdotpbasmiaaw rD, rA, rB + evdotpbasumiaaw rD, rA, rB + evdotp4hxgssmiaa rD, rA, rB + evdotp4hxgssmfaa rD, rA, rB + evdotpwausi rD, rA, rB + evdotpwassi rD, rA, rB + evdotpwasusi rD, rA, rB + evdotpwaumi rD, rA, rB + evdotpwasmi rD, rA, rB + evdotpwasumi rD, rA, rB + evdotpwssmi rD, rA, rB + evdotpwausiaa3 rD, rA, rB + evdotpwassiaa3 rD, rA, rB + evdotpwasusiaa3 rD, rA, rB + evdotpwsssiaa3 rD, rA, rB + evdotpwaumiaa3 rD, rA, rB + evdotpwasmiaa3 rD, rA, rB + evdotpwasumiaa3 rD, rA, rB + evdotpwssmiaa3 rD, rA, rB + evdotpwausia rD, rA, rB + evdotpwassia rD, rA, rB + evdotpwasusia rD, rA, rB + evdotpwaumia rD, rA, rB + evdotpwasmia rD, rA, rB + evdotpwasumia rD, rA, rB + evdotpwssmia rD, rA, rB + evdotpwausiaa rD, rA, rB + evdotpwassiaa rD, rA, rB + evdotpwasusiaa rD, rA, rB + evdotpwsssiaa rD, rA, rB + evdotpwaumiaa rD, rA, rB + evdotpwasmiaa rD, rA, rB + evdotpwasumiaa rD, rA, rB + evdotpwssmiaa rD, rA, rB + evaddib rD, rB, UIMM + evaddih rD, rB, UIMM + evsubifh rD, UIMM, rB + evsubifb rD, UIMM, rB + evabsb rD, rA + evabsh rD, rA + evabsd rD, rA + evabss rD, rA + evabsbs rD, rA + evabshs rD, rA + evabsds rD, rA + evnegwo rD, rA + evnegb rD, rA + evnegbo rD, rA + evnegh rD, rA + evnegho rD, rA + evnegd rD, rA + evnegs rD, rA + evnegwos rD, rA + evnegbs rD, rA + evnegbos rD, rA + evneghs rD, rA + evneghos rD, rA + evnegds rD, rA + evextzb rD, rA + evextsbh rD, rA + evextsw rD, rA + evrndwh rD, rA + evrndhb rD, rA + evrnddw rD, rA + evrndwhus rD, rA + evrndwhss rD, rA + evrndhbus rD, rA + evrndhbss rD, rA + evrnddwus rD, rA + evrnddwss rD, rA + evrndwnh rD, rA + evrndhnb rD, rA + evrnddnw rD, rA + evrndwnhus rD, rA + evrndwnhss rD, rA + evrndhnbus rD, rA + evrndhnbss rD, rA + evrnddnwus rD, rA + evrnddnwss rD, rA + evcntlzh rD, rA + evcntlsh rD, rA + evpopcntb rD, rA + circinc rD, rA, rB + evunpkhibui rD, rA + evunpkhibsi rD, rA + evunpkhihui rD, rA + evunpkhihsi rD, rA + evunpklobui rD, rA + evunpklobsi rD, rA + evunpklohui rD, rA + evunpklohsi rD, rA + evunpklohf rD, rA + evunpkhihf rD, rA + evunpklowgsf rD, rA + evunpkhiwgsf rD, rA + evsatsduw rD, rA + evsatsdsw rD, rA + evsatshub rD, rA + evsatshsb rD, rA + evsatuwuh rD, rA + evsatswsh rD, rA + evsatswuh rD, rA + evsatuhub rD, rA + evsatuduw rD, rA + evsatuwsw rD, rA + evsatshuh rD, rA + evsatuhsh rD, rA + evsatswuw rD, rA + evsatswgsdf rD, rA + evsatsbub rD, rA + evsatubsb rD, rA + evmaxhpuw rD, rA + evmaxhpsw rD, rA + evmaxbpuh rD, rA + evmaxbpsh rD, rA + evmaxwpud rD, rA + evmaxwpsd rD, rA + evminhpuw rD, rA + evminhpsw rD, rA + evminbpuh rD, rA + evminbpsh rD, rA + evminwpud rD, rA + evminwpsd rD, rA + evmaxmagws rD, rA, rB + evsl rD, rA, rB + evsli rD, rA, UIMM + evsplatie rD, SIMM + evsplatib rD, SIMM + evsplatibe rD, SIMM + evsplatih rD, SIMM + evsplatihe rD, SIMM + evsplatid rD, SIMM + evsplatia rD, SIMM + evsplatiea rD, SIMM + evsplatiba rD, SIMM + evsplatibea rD, SIMM + evsplatiha rD, SIMM + evsplatihea rD, SIMM + evsplatida rD, SIMM + evsplatfio rD, SIMM + evsplatfib rD, SIMM + evsplatfibo rD, SIMM + evsplatfih rD, SIMM + evsplatfiho rD, SIMM + evsplatfid rD, SIMM + evsplatfia rD, SIMM + evsplatfioa rD, SIMM + evsplatfiba rD, SIMM + evsplatfiboa rD, SIMM + evsplatfiha rD, SIMM + evsplatfihoa rD, SIMM + evsplatfida rD, SIMM + evcmpgtdu crD, rA, rB + evcmpgtds crD, rA, rB + evcmpltdu crD, rA, rB + evcmpltds crD, rA, rB + evcmpeqd crD, rA, rB + evswapbhilo rD, rA, rB + evswapblohi rD, rA, rB + evswaphhilo rD, rA, rB + evswaphlohi rD, rA, rB + evswaphe rD, rA, rB + evswaphhi rD, rA, rB + evswaphlo rD, rA, rB + evswapho rD, rA, rB + evinsb rD, rA, Ddd, bbb + evxtrb rD, rA, Ddd, bbb + evsplath rD, rA, hh + evsplatb rD, rA, bbb + evinsh rD, rA, dd, hh + evclrbe rD, rA, mask + evclrbo rD, rA, mask + evclrh rD, rA, mask + evxtrh rD, rA, dd, hh + evselbitm0 rD, rA, rB + evselbitm1 rD, rA, rB + evselbit rD, rA, rB + evperm rD, rA, rB + evperm2 rD, rA, rB + evperm3 rD, rA, rB + evxtrd rD, rA, rB, offset + evsrbu rD, rA, rB + evsrbs rD, rA, rB + evsrbiu rD, rA, UIMM_LT8 + evsrbis rD, rA, UIMM_LT8 + evslb rD, rA, rB + evrlb rD, rA, rB + evslbi rD, rA, UIMM_LT8 + evrlbi rD, rA, UIMM_LT8 + evsrhu rD, rA, rB + evsrhs rD, rA, rB + evsrhiu rD, rA, UIMM_LT16 + evsrhis rD, rA, UIMM_LT16 + evslh rD, rA, rB + evrlh rD, rA, rB + evslhi rD, rA, UIMM_LT16 + evrlhi rD, rA, UIMM_LT16 + evsru rD, rA, rB + evsrs rD, rA, rB + evsriu rD, rA, UIMM + evsris rD, rA, UIMM + evlvsl rD, rA, rB + evlvsr rD, rA, rB + evsroiu rD, rA, nnn + evsrois rD, rA, nnn + evsloi rD, rA, nnn + evfssqrt rD, rA + evfscfh rD, rB + evfscth rD, rB + evfsmax rD, rA, rB + evfsmin rD, rA, rB + evfsaddsub rD, rA, rB + evfssubadd rD, rA, rB + evfssum rD, rA, rB + evfsdiff rD, rA, rB + evfssumdiff rD, rA, rB + evfsdiffsum rD, rA, rB + evfsaddx rD, rA, rB + evfssubx rD, rA, rB + evfsaddsubx rD, rA, rB + evfssubaddx rD, rA, rB + evfsmulx rD, rA, rB + evfsmule rD, rA, rB + evfsmulo rD, rA, rB + evldbx rD, rA, rB + evldb rD, UIMM_8 (rA) + evlhhsplathx rD, rA, rB + evlhhsplath rD, UIMM_2 (rA) + evlwbsplatwx rD, rA, rB + evlwbsplatw rD, UIMM_4 (rA) + evlwhsplatwx rD, rA, rB + evlwhsplatw rD, UIMM_4 (rA) + evlbbsplatbx rD, rA, rB + evlbbsplatb rD, UIMM_1 (rA) + evstdbx rS, rA, rB + evstdb rS, UIMM_8 (rA) + evlwbex rD, rA, rB + evlwbe rD, UIMM_4 (rA) + evlwboux rD, rA, rB + evlwbou rD, UIMM_4 (rA) + evlwbosx rD, rA, rB + evlwbos rD, UIMM_4 (rA) + evstwbex rS, rA, rB + evstwbe rS, UIMM_4 (rA) + evstwbox rS, rA, rB + evstwbo rS, UIMM_4 (rA) + evstwbx rS, rA, rB + evstwb rS, UIMM_4 (rA) + evsthbx rS, rA, rB + evsthb rS, UIMM_2 (rA) + evlddmx rD, rA, rB + evlddu rD, UIMM_8 (rA) + evldwmx rD, rA, rB + evldwu rD, UIMM_8 (rA) + evldhmx rD, rA, rB + evldhu rD, UIMM_8 (rA) + evldbmx rD, rA, rB + evldbu rD, UIMM_8 (rA) + evlhhesplatmx rD, rA, rB + evlhhesplatu rD, UIMM_2 (rA) + evlhhsplathmx rD, rA, rB + evlhhsplathu rD, UIMM_2 (rA) + evlhhousplatmx rD, rA, rB + evlhhousplatu rD, UIMM_2 (rA) + evlhhossplatmx rD, rA, rB + evlhhossplatu rD, UIMM_2 (rA) + evlwhemx rD, rA, rB + evlwheu rD, UIMM_4 (rA) + evlwbsplatwmx rD, rA, rB + evlwbsplatwu rD, UIMM_4 (rA) + evlwhoumx rD, rA, rB + evlwhouu rD, UIMM_4 (rA) + evlwhosmx rD, rA, rB + evlwhosu rD, UIMM_4 (rA) + evlwwsplatmx rD, rA, rB + evlwwsplatu rD, UIMM_4 (rA) + evlwhsplatwmx rD, rA, rB + evlwhsplatwu rD, UIMM_4 (rA) + evlwhsplatmx rD, rA, rB + evlwhsplatu rD, UIMM_4 (rA) + evlbbsplatbmx rD, rA, rB + evlbbsplatbu rD, UIMM_1 (rA) + evstddmx rS, rA, rB + evstddu rS, UIMM_8 (rA) + evstdwmx rS, rA, rB + evstdwu rS, UIMM_8 (rA) + evstdhmx rS, rA, rB + evstdhu rS, UIMM_8 (rA) + evstdbmx rS, rA, rB + evstdbu rS, UIMM_8 (rA) + evlwbemx rD, rA, rB + evlwbeu rD, UIMM_4 (rA) + evlwboumx rD, rA, rB + evlwbouu rD, UIMM_4 (rA) + evlwbosmx rD, rA, rB + evlwbosu rD, UIMM_4 (rA) + evstwhemx rS, rA, rB + evstwheu rS, UIMM_4 (rA) + evstwbemx rS, rA, rB + evstwbeu rS, UIMM_4 (rA) + evstwhomx rS, rA, rB + evstwhou rS, UIMM_4 (rA) + evstwbomx rS, rA, rB + evstwbou rS, UIMM_4 (rA) + evstwwemx rS, rA, rB + evstwweu rS, UIMM_4 (rA) + evstwbmx rS, rA, rB + evstwbu rS, UIMM_4 (rA) + evstwwomx rS, rA, rB + evstwwou rS, UIMM_4 (rA) + evsthbmx rS, rA, rB + evsthbu rS, UIMM_2 (rA) + evmhusi rD, rA, rB + evmhssi rD, rA, rB + evmhsusi rD, rA, rB + evmhssf rD, rA, rB + evmhumi rD, rA, rB + evmhssfr rD, rA, rB + evmhesumi rD, rA, rB + evmhosumi rD, rA, rB + evmbeumi rD, rA, rB + evmbesmi rD, rA, rB + evmbesumi rD, rA, rB + evmboumi rD, rA, rB + evmbosmi rD, rA, rB + evmbosumi rD, rA, rB + evmhesumia rD, rA, rB + evmhosumia rD, rA, rB + evmbeumia rD, rA, rB + evmbesmia rD, rA, rB + evmbesumia rD, rA, rB + evmboumia rD, rA, rB + evmbosmia rD, rA, rB + evmbosumia rD, rA, rB + evmwusiw rD, rA, rB + evmwssiw rD, rA, rB + evmwhssfr rD, rA, rB + evmwehgsmfr rD, rA, rB + evmwehgsmf rD, rA, rB + evmwohgsmfr rD, rA, rB + evmwohgsmf rD, rA, rB + evmwhssfra rD, rA, rB + evmwehgsmfra rD, rA, rB + evmwehgsmfa rD, rA, rB + evmwohgsmfra rD, rA, rB + evmwohgsmfa rD, rA, rB + evaddusiaa rD, rA + evaddssiaa rD, rA + evsubfusiaa rD, rA + evsubfssiaa rD, rA + evaddsmiaa rD, rA + evsubfsmiaa rD, rA + evaddh rD, rA, rB + evaddhss rD, rA, rB + evsubfh rD, rA, rB + evsubfhss rD, rA, rB + evaddhx rD, rA, rB + evaddhxss rD, rA, rB + evsubfhx rD, rA, rB + evsubfhxss rD, rA, rB + evaddd rD, rA, rB + evadddss rD, rA, rB + evsubfd rD, rA, rB + evsubfdss rD, rA, rB + evaddb rD, rA, rB + evaddbss rD, rA, rB + evsubfb rD, rA, rB + evsubfbss rD, rA, rB + evaddsubfh rD, rA, rB + evaddsubfhss rD, rA, rB + evsubfaddh rD, rA, rB + evsubfaddhss rD, rA, rB + evaddsubfhx rD, rA, rB + evaddsubfhxss rD, rA, rB + evsubfaddhx rD, rA, rB + evsubfaddhxss rD, rA, rB + evadddus rD, rA, rB + evaddbus rD, rA, rB + evsubfdus rD, rA, rB + evsubfbus rD, rA, rB + evaddwus rD, rA, rB + evaddwxus rD, rA, rB + evsubfwus rD, rA, rB + evsubfwxus rD, rA, rB + evadd2subf2h rD, rA, rB + evadd2subf2hss rD, rA, rB + evsubf2add2h rD, rA, rB + evsubf2add2hss rD, rA, rB + evaddhus rD, rA, rB + evaddhxus rD, rA, rB + evsubfhus rD, rA, rB + evsubfhxus rD, rA, rB + evaddwss rD, rA, rB + evsubfwss rD, rA, rB + evaddwx rD, rA, rB + evaddwxss rD, rA, rB + evsubfwx rD, rA, rB + evsubfwxss rD, rA, rB + evaddsubfw rD, rA, rB + evaddsubfwss rD, rA, rB + evsubfaddw rD, rA, rB + evsubfaddwss rD, rA, rB + evaddsubfwx rD, rA, rB + evaddsubfwxss rD, rA, rB + evsubfaddwx rD, rA, rB + evsubfaddwxss rD, rA, rB + evmar rD + evsumwu rD, rA + evsumws rD, rA + evsum4bu rD, rA + evsum4bs rD, rA + evsum2hu rD, rA + evsum2hs rD, rA + evdiff2his rD, rA + evsum2his rD, rA + evsumwua rD, rA + evsumwsa rD, rA + evsum4bua rD, rA + evsum4bsa rD, rA + evsum2hua rD, rA + evsum2hsa rD, rA + evdiff2hisa rD, rA + evsum2hisa rD, rA + evsumwuaa rD, rA + evsumwsaa rD, rA + evsum4buaaw rD, rA + evsum4bsaaw rD, rA + evsum2huaaw rD, rA + evsum2hsaaw rD, rA + evdiff2hisaaw rD, rA + evsum2hisaaw rD, rA + evdivwsf rD, rA, rB + evdivwuf rD, rA, rB + evdivs rD, rA, rB + evdivu rD, rA, rB + evaddwegsi rD, rA, rB + evaddwegsf rD, rA, rB + evsubfwegsi rD, rA, rB + evsubfwegsf rD, rA, rB + evaddwogsi rD, rA, rB + evaddwogsf rD, rA, rB + evsubfwogsi rD, rA, rB + evsubfwogsf rD, rA, rB + evaddhhiuw rD, rA, rB + evaddhhisw rD, rA, rB + evsubfhhiuw rD, rA, rB + evsubfhhisw rD, rA, rB + evaddhlouw rD, rA, rB + evaddhlosw rD, rA, rB + evsubfhlouw rD, rA, rB + evsubfhlosw rD, rA, rB + evmhesusiaaw rD, rA, rB + evmhosusiaaw rD, rA, rB + evmhesumiaaw rD, rA, rB + evmhosumiaaw rD, rA, rB + evmbeusiaah rD, rA, rB + evmbessiaah rD, rA, rB + evmbesusiaah rD, rA, rB + evmbousiaah rD, rA, rB + evmbossiaah rD, rA, rB + evmbosusiaah rD, rA, rB + evmbeumiaah rD, rA, rB + evmbesmiaah rD, rA, rB + evmbesumiaah rD, rA, rB + evmboumiaah rD, rA, rB + evmbosmiaah rD, rA, rB + evmbosumiaah rD, rA, rB + evmwlusiaaw3 rD, rA, rB + evmwlssiaaw3 rD, rA, rB + evmwhssfraaw3 rD, rA, rB + evmwhssfaaw3 rD, rA, rB + evmwhssfraaw rD, rA, rB + evmwhssfaaw rD, rA, rB + evmwlumiaaw3 rD, rA, rB + evmwlsmiaaw3 rD, rA, rB + evmwusiaa rD, rA, rB + evmwssiaa rD, rA, rB + evmwehgsmfraa rD, rA, rB + evmwehgsmfaa rD, rA, rB + evmwohgsmfraa rD, rA, rB + evmwohgsmfaa rD, rA, rB + evmhesusianw rD, rA, rB + evmhosusianw rD, rA, rB + evmhesumianw rD, rA, rB + evmhosumianw rD, rA, rB + evmbeusianh rD, rA, rB + evmbessianh rD, rA, rB + evmbesusianh rD, rA, rB + evmbousianh rD, rA, rB + evmbossianh rD, rA, rB + evmbosusianh rD, rA, rB + evmbeumianh rD, rA, rB + evmbesmianh rD, rA, rB + evmbesumianh rD, rA, rB + evmboumianh rD, rA, rB + evmbosmianh rD, rA, rB + evmbosumianh rD, rA, rB + evmwlusianw3 rD, rA, rB + evmwlssianw3 rD, rA, rB + evmwhssfranw3 rD, rA, rB + evmwhssfanw3 rD, rA, rB + evmwhssfranw rD, rA, rB + evmwhssfanw rD, rA, rB + evmwlumianw3 rD, rA, rB + evmwlsmianw3 rD, rA, rB + evmwusian rD, rA, rB + evmwssian rD, rA, rB + evmwehgsmfran rD, rA, rB + evmwehgsmfan rD, rA, rB + evmwohgsmfran rD, rA, rB + evmwohgsmfan rD, rA, rB + evseteqb rD, rA, rB + evseteqb. rD, rA, rB + evseteqh rD, rA, rB + evseteqh. rD, rA, rB + evseteqw rD, rA, rB + evseteqw. rD, rA, rB + evsetgthu rD, rA, rB + evsetgthu. rD, rA, rB + evsetgths rD, rA, rB + evsetgths. rD, rA, rB + evsetgtwu rD, rA, rB + evsetgtwu. rD, rA, rB + evsetgtws rD, rA, rB + evsetgtws. rD, rA, rB + evsetgtbu rD, rA, rB + evsetgtbu. rD, rA, rB + evsetgtbs rD, rA, rB + evsetgtbs. rD, rA, rB + evsetltbu rD, rA, rB + evsetltbu. rD, rA, rB + evsetltbs rD, rA, rB + evsetltbs. rD, rA, rB + evsetlthu rD, rA, rB + evsetlthu. rD, rA, rB + evsetlths rD, rA, rB + evsetlths. rD, rA, rB + evsetltwu rD, rA, rB + evsetltwu. rD, rA, rB + evsetltws rD, rA, rB + evsetltws. rD, rA, rB + evsaduw rD, rA, rB + evsadsw rD, rA, rB + evsad4ub rD, rA, rB + evsad4sb rD, rA, rB + evsad2uh rD, rA, rB + evsad2sh rD, rA, rB + evsaduwa rD, rA, rB + evsadswa rD, rA, rB + evsad4uba rD, rA, rB + evsad4sba rD, rA, rB + evsad2uha rD, rA, rB + evsad2sha rD, rA, rB + evabsdifuw rD, rA, rB + evabsdifsw rD, rA, rB + evabsdifub rD, rA, rB + evabsdifsb rD, rA, rB + evabsdifuh rD, rA, rB + evabsdifsh rD, rA, rB + evsaduwaa rD, rA, rB + evsadswaa rD, rA, rB + evsad4ubaaw rD, rA, rB + evsad4sbaaw rD, rA, rB + evsad2uhaaw rD, rA, rB + evsad2shaaw rD, rA, rB + evpkshubs rD, rA, rB + evpkshsbs rD, rA, rB + evpkswuhs rD, rA, rB + evpkswshs rD, rA, rB + evpkuhubs rD, rA, rB + evpkuwuhs rD, rA, rB + evpkswshilvs rD, rA, rB + evpkswgshefrs rD, rA, rB + evpkswshfrs rD, rA, rB + evpkswshilvfrs rD, rA, rB + evpksdswfrs rD, rA, rB + evpksdshefrs rD, rA, rB + evpkuduws rD, rA, rB + evpksdsws rD, rA, rB + evpkswgswfrs rD, rA, rB + evilveh rD, rA, rB + evilveoh rD, rA, rB + evilvhih rD, rA, rB + evilvhiloh rD, rA, rB + evilvloh rD, rA, rB + evilvlohih rD, rA, rB + evilvoeh rD, rA, rB + evilvoh rD, rA, rB + evdlveb rD, rA, rB + evdlveh rD, rA, rB + evdlveob rD, rA, rB + evdlveoh rD, rA, rB + evdlvob rD, rA, rB + evdlvoh rD, rA, rB + evdlvoeb rD, rA, rB + evdlvoeh rD, rA, rB + evmaxbu rD, rA, rB + evmaxbs rD, rA, rB + evmaxhu rD, rA, rB + evmaxhs rD, rA, rB + evmaxwu rD, rA, rB + evmaxws rD, rA, rB + evmaxdu rD, rA, rB + evmaxds rD, rA, rB + evminbu rD, rA, rB + evminbs rD, rA, rB + evminhu rD, rA, rB + evminhs rD, rA, rB + evminwu rD, rA, rB + evminws rD, rA, rB + evmindu rD, rA, rB + evminds rD, rA, rB + evavgwu rD, rA, rB + evavgws rD, rA, rB + evavgbu rD, rA, rB + evavgbs rD, rA, rB + evavghu rD, rA, rB + evavghs rD, rA, rB + evavgdu rD, rA, rB + evavgds rD, rA, rB + evavgwur rD, rA, rB + evavgwsr rD, rA, rB + evavgbur rD, rA, rB + evavgbsr rD, rA, rB + evavghur rD, rA, rB + evavghsr rD, rA, rB + evavgdur rD, rA, rB + evavgdsr rD, rA, rB + +;#SPE2 mapped by macro + evdotphsssi rD, rA, rB + evdotphsssia rD, rA, rB + evdotpwsssi rD, rA, rB + evdotpwsssia rD, rA, rB diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.d b/gas/testsuite/gas/ppc/spe_ambiguous.d new file mode 100644 index 0000000..cdfb005 --- /dev/null +++ b/gas/testsuite/gas/ppc/spe_ambiguous.d @@ -0,0 +1,15 @@ +#as: -a32 -mvle +#objdump: -d -Mspe +#name: Validate SPE instructions + +.*: +file format elf.*-powerpc.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 10 01 12 04 evsubfw r0,r1,r2 + 4: 10 01 12 04 evsubw r0,r2,r1 + 8: 10 1f 12 06 evsubifw r0,31,r2 + c: 10 1f 12 06 evsubiw r0,r2,31 + 10: 10 01 12 18 evnor r0,r1,r2 + 14: 10 01 0a 18 evnot r0,r1 diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.s b/gas/testsuite/gas/ppc/spe_ambiguous.s new file mode 100644 index 0000000..b60e02b --- /dev/null +++ b/gas/testsuite/gas/ppc/spe_ambiguous.s @@ -0,0 +1,21 @@ +# PA SPE instructions + .section ".text" + .equ rA,1 + .equ rB,2 + .equ rD,0 + .equ rS,0 + .equ rT,0 + .equ UIMM, 31 + .equ UIMM_2, 2 + .equ UIMM_4, 4 + .equ UIMM_8, 8 + .equ SIMM, -16 + .equ crD, 0 + .equ crS, 0 + + evsubfw rS, rA, rB + evsubw rS, rB, rA + evsubifw rS, UIMM, rB + evsubiw rS, rB, UIMM + evnor rS, rA, rB + evnot rS, rA diff --git a/include/ChangeLog b/include/ChangeLog index db500dc..78782db 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,13 @@ +2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com> + Edmar Wienskoski <edmar.wienskoski@nxp.com> + + * opcode/ppc.h: + (spe2_opcodes, spe2_num_opcodes): New. + (PPC_OPCODE_SPE2): New define. + (PPC_OPCODE_EFS2): Likewise. + (SPE2_XOP): Likewise. + (SPE2_XOP_TO_SEG): Likewise. + 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com> Edmar Wienskoski <edmar.wienskoski@nxp.com> diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 21b1221..5274cae 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -70,6 +70,8 @@ extern const struct powerpc_opcode powerpc_opcodes[]; extern const int powerpc_num_opcodes; extern const struct powerpc_opcode vle_opcodes[]; extern const int vle_num_opcodes; +extern const struct powerpc_opcode spe2_opcodes[]; +extern const int spe2_num_opcodes; /* Values defined for the flags field of a struct powerpc_opcode. */ @@ -218,6 +220,12 @@ extern const int vle_num_opcodes; /* Opcode is supported by PowerPC LSP */ #define PPC_OPCODE_LSP 0x80000000000ull +/* Opcode is only supported by Freescale SPE2 APU. */ +#define PPC_OPCODE_SPE2 0x100000000000ull + +/* Opcode is supported by EFS2. */ +#define PPC_OPCODE_EFS2 0x200000000000ull + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -229,6 +237,12 @@ extern const int vle_num_opcodes; /* A macro to convert a VLE opcode to a VLE opcode segment. */ #define VLE_OP_TO_SEG(i) ((i) >> 1) + +/* A macro to extract the extended opcode from a SPE2 instruction. */ +#define SPE2_XOP(i) ((i) & 0x7ff) + +/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */ +#define SPE2_XOP_TO_SEG(i) ((i) >> 7) /* The operands table is an array of struct powerpc_operand. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1ea12bb..5a3ab08 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,63 @@ +2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com> + Edmar Wienskoski <edmar.wienskoski@nxp.com> + + * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and + PPC_OPCODE_EFS2 flag to "e200z4" entry. + New entries efs2 and spe2. + Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. + (SPE2_OPCD_SEGS): New macro. + (spe2_opcd_indices): New. + (disassemble_init_powerpc): Handle SPE2 opcodes. + (lookup_spe2): New function. + (print_insn_powerpc): call lookup_spe2. + * ppc-opc.c (insert_evuimm1_ex0): New function. + (extract_evuimm1_ex0): Likewise. + (insert_evuimm_lt8): Likewise. + (extract_evuimm_lt8): Likewise. + (insert_off_spe2): Likewise. + (extract_off_spe2): Likewise. + (insert_Ddd): Likewise. + (extract_Ddd): Likewise. + (DD): New operand. + (EVUIMM_LT8): Likewise. + (EVUIMM_LT16): Adjust. + (MMMM): New operand. + (EVUIMM_1): Likewise. + (EVUIMM_1_EX0): Likewise. + (EVUIMM_2): Adjust. + (NNN): New operand. + (VX_OFF_SPE2): Likewise. + (BBB): Likewise. + (DDD): Likewise. + (VX_MASK_DDD): New mask. + (HH): New operand. + (VX_RA_CONST): New macro. + (VX_RA_CONST_MASK): Likewise. + (VX_RB_CONST): Likewise. + (VX_RB_CONST_MASK): Likewise. + (VX_OFF_SPE2_MASK): Likewise. + (VX_SPE_CRFD): Likewise. + (VX_SPE_CRFD_MASK VX): Likewise. + (VX_SPE2_CLR): Likewise. + (VX_SPE2_CLR_MASK): Likewise. + (VX_SPE2_SPLATB): Likewise. + (VX_SPE2_SPLATB_MASK): Likewise. + (VX_SPE2_OCTET): Likewise. + (VX_SPE2_OCTET_MASK): Likewise. + (VX_SPE2_DDHH): Likewise. + (VX_SPE2_DDHH_MASK): Likewise. + (VX_SPE2_HH): Likewise. + (VX_SPE2_HH_MASK): Likewise. + (VX_SPE2_EVMAR): Likewise. + (VX_SPE2_EVMAR_MASK): Likewise. + (PPCSPE2): Likewise. + (PPCEFS2): Likewise. + (vle_opcodes): Add EFS2 and some missing SPE opcodes. + (powerpc_macros): Map old SPE instructions have new names + with the same opcodes. Add SPE2 instructions which just are + mapped to SPE2. + (spe2_opcodes): Add SPE2 opcodes. + 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com> Edmar Wienskoski <edmar.wienskoski@nxp.com> diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index d75e59d..0e2e185 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -120,7 +120,8 @@ struct ppc_mopt ppc_opts[] = { { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI - | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4), + | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4 + | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP), 0 }, { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300, 0 }, @@ -156,6 +157,8 @@ struct ppc_mopt ppc_opts[] = { 0 }, { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS, 0 }, + { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2, + 0 }, { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, 0 }, { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 @@ -227,13 +230,15 @@ struct ppc_mopt ppc_opts[] = { PPC_OPCODE_RAW }, { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS, PPC_OPCODE_SPE }, + { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE, + PPC_OPCODE_SPE2 }, { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), 0 }, { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI - | PPC_OPCODE_E500 | PPC_OPCODE_LSP), + | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2), PPC_OPCODE_VLE }, { "vsx", PPC_OPCODE_PPC, PPC_OPCODE_VSX }, @@ -362,6 +367,8 @@ powerpc_init_dialect (struct disassemble_info *info) static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; #define VLE_OPCD_SEGS 32 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; +#define SPE2_OPCD_SEGS 13 +static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1]; /* Calculate opcode table indices to speed up disassembly, and init dialect. */ @@ -409,6 +416,24 @@ disassemble_init_powerpc (struct disassemble_info *info) } } + /* SPE2 opcodes */ + i = spe2_num_opcodes; + while (--i >= 0) + { + unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode); + unsigned seg = SPE2_XOP_TO_SEG (xop); + + spe2_opcd_indices[seg] = i; + } + + last = spe2_num_opcodes; + for (i = SPE2_OPCD_SEGS; i > 1; --i) + { + if (spe2_opcd_indices[i] == 0) + spe2_opcd_indices[i] = last; + last = spe2_opcd_indices[i]; + } + if (info->arch == bfd_arch_powerpc) powerpc_init_dialect (info); } @@ -596,6 +621,58 @@ lookup_vle (unsigned long insn) return NULL; } +/* Find a match for INSN in the SPE2 opcode table. */ + +static const struct powerpc_opcode * +lookup_spe2 (unsigned long insn) +{ + const struct powerpc_opcode *opcode, *opcode_end; + unsigned op, xop, seg; + + op = PPC_OP (insn); + if (op != 0x4) + { + /* This is not SPE2 insn. + * All SPE2 instructions have OP=4 and differs by XOP */ + return NULL; + } + xop = SPE2_XOP (insn); + seg = SPE2_XOP_TO_SEG (xop); + + /* Find the first match in the opcode table for this major opcode. */ + opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1]; + for (opcode = spe2_opcodes + spe2_opcd_indices[seg]; + opcode < opcode_end; + ++opcode) + { + unsigned long table_opcd = opcode->opcode; + unsigned long table_mask = opcode->mask; + unsigned long insn2; + const unsigned char *opindex; + const struct powerpc_operand *operand; + int invalid; + + insn2 = insn; + if ((insn2 & table_mask) != table_opcd) + continue; + + /* Check validity of operands. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; ++opindex) + { + operand = powerpc_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); + } + if (invalid) + continue; + + return opcode; + } + + return NULL; +} + /* Print a PowerPC or POWER instruction. */ static int @@ -646,6 +723,8 @@ print_insn_powerpc (bfd_vma memaddr, if (opcode != NULL) insn_is_short = PPC_OP_SE_VLE(opcode->mask); } + if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0) + opcode = lookup_spe2 (insn); if (opcode == NULL) opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY); if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 12eb1af..8938ebf 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -131,18 +131,26 @@ static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char ** static long extract_vleui (unsigned long, ppc_cpu_t, int *); static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **); static long extract_vleil (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_evuimm1_ex0 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_evuimm1_ex0 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_evuimm2_ex0 (unsigned long, long, ppc_cpu_t, const char **); static long extract_evuimm2_ex0 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_evuimm4_ex0 (unsigned long, long, ppc_cpu_t, const char **); static long extract_evuimm4_ex0 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_evuimm8_ex0 (unsigned long, long, ppc_cpu_t, const char **); static long extract_evuimm8_ex0 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_evuimm_lt8 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_evuimm_lt8 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_evuimm_lt16 (unsigned long, long, ppc_cpu_t, const char **); static long extract_evuimm_lt16 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_rD_rS_even (unsigned long, long, ppc_cpu_t, const char **); static long extract_rD_rS_even (unsigned long, ppc_cpu_t, int *); static unsigned long insert_off_lsp (unsigned long, long, ppc_cpu_t, const char **); static long extract_off_lsp (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_off_spe2 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_off_spe2 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_Ddd (unsigned long, long, ppc_cpu_t, const char **); +static long extract_Ddd (unsigned long, ppc_cpu_t, int *); /* The operands table. @@ -255,6 +263,7 @@ const struct powerpc_operand powerpc_operands[] = /* The RM field in an X form instruction. */ #define RM BOE + 1 +#define DD RM { 0x3, 11, NULL, NULL, 0 }, #define BH RM + 1 @@ -659,7 +668,10 @@ const struct powerpc_operand powerpc_operands[] = #define FC SH { 0x1f, 11, NULL, NULL, 0 }, -#define EVUIMM_LT16 SH + 1 +#define EVUIMM_LT8 SH + 1 + { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 }, + +#define EVUIMM_LT16 EVUIMM_LT8 + 1 { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 }, /* The SI field in a HTM X form instruction. */ @@ -799,6 +811,8 @@ const struct powerpc_operand powerpc_operands[] = /* The SIX field in a VX form instruction. */ #define SIX UIM6 + 1 + /* The MMMM field in a VX form instruction for SPE2 */ +#define MMMM SIX { 0xf, 11, NULL, NULL, 0 }, /* The PS field in a VX form instruction. */ @@ -810,7 +824,13 @@ const struct powerpc_operand powerpc_operands[] = { 0xf, 6, NULL, NULL, 0 }, /* The other UIMM field in a half word EVX form instruction. */ -#define EVUIMM_2 SHB + 1 +#define EVUIMM_1 SHB + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS }, + +#define EVUIMM_1_EX0 EVUIMM_1 + 1 + { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS }, + +#define EVUIMM_2 EVUIMM_1_EX0 + 1 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, #define EVUIMM_2_EX0 EVUIMM_2 + 1 @@ -833,6 +853,8 @@ const struct powerpc_operand powerpc_operands[] = /* The WS or DRM field in an X form instruction. */ #define WS EVUIMM_8_EX0 + 1 #define DRM WS + /* The NNN field in a VX form instruction for SPE2 */ +#define NNN WS { 0x7, 11, NULL, NULL, 0 }, /* PowerPC paired singles extensions. */ @@ -1001,6 +1023,20 @@ const struct powerpc_operand powerpc_operands[] = #define VX_OFF IMM8 + 1 { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 }, + +#define VX_OFF_SPE2 VX_OFF + 1 + { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 }, + +#define BBB VX_OFF_SPE2 + 1 + { 0x7, 13, NULL, NULL, 0 }, + +#define DDD BBB + 1 +#define VX_MASK_DDD (VX_MASK & ~0x1) + { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, + +#define HH DDD + 1 + { 0x3, 13, NULL, NULL, 0 }, + }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -2443,6 +2479,33 @@ extract_vleil (unsigned long insn, } static unsigned long +insert_evuimm1_ex0 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value > 0 && value <= 0x1f) + return insn | ((value & 0x1f) << 11); + else + { + *errmsg = _("UIMM = 00000 is illegal"); + return 0; + } +} + +static long +extract_evuimm1_ex0 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value = ((insn >> 11) & 0x1f); + if (value == 0) + *invalid = 1; + + return value; +} + +static unsigned long insert_evuimm2_ex0 (unsigned long insn, long value, ppc_cpu_t dialect ATTRIBUTE_UNUSED, @@ -2524,6 +2587,33 @@ extract_evuimm8_ex0 (unsigned long insn, } static unsigned long +insert_evuimm_lt8 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value >= 0 && value <= 7) + return insn | ((value & 0x7) << 11); + else + { + *errmsg = _("UIMM values >7 are illegal"); + return 0; + } +} + +static long +extract_evuimm_lt8 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value = ((insn >> 11) & 0x1f); + if (value > 7) + *invalid = 1; + + return value; +} + +static unsigned long insert_evuimm_lt16 (unsigned long insn, long value, ppc_cpu_t dialect ATTRIBUTE_UNUSED, @@ -2603,6 +2693,56 @@ extract_off_lsp (unsigned long insn, return value; } + +static unsigned long +insert_off_spe2 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value > 0 && value <= 0x7) + return insn | (value & 0x7); + else + { + *errmsg = _("invalid offset"); + return 0; + } +} + +static long +extract_off_spe2 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value = (insn & 0x7); + if (value == 0) + *invalid = 1; + + return value; +} + +static unsigned long +insert_Ddd (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value >= 0 && value <= 0x7) + return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2); + else + { + *errmsg = _("invalid Ddd value"); + return 0; + } +} + +static long +extract_Ddd (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4); +} /* Macros used to form opcodes. */ @@ -2844,6 +2984,36 @@ extract_off_lsp (unsigned long insn, #define VX_LSP_MASK VX_LSP(0x3f, 0xffff) #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc) +/* Additional format of VX SPE2 form instruction. */ +#define VX_RA_CONST(op, xop, bits11_15) (OP (op) | (((unsigned long)(bits11_15) & 0x1f) << 16) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f) + +#define VX_RB_CONST(op, xop, bits16_20) (OP (op) | (((unsigned long)(bits16_20) & 0x1f) << 11) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f) + +#define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8) + +#define VX_SPE_CRFD(op, xop, bits9_10) (OP (op) | (((unsigned long)(bits9_10) & 0x3) << 21) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3) + +#define VX_SPE2_CLR(op, xop, bit16) (OP (op) | (((unsigned long)(bit16) & 0x1) << 15) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1) + +#define VX_SPE2_SPLATB(op, xop, bits19_20) (OP (op) | (((unsigned long)(bits19_20) & 0x3) << 11) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3) + +#define VX_SPE2_OCTET(op, xop, bits16_17) (OP (op) | (((unsigned long)(bits16_17) & 0x3) << 14) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7) + +#define VX_SPE2_DDHH(op, xop, bit16) (OP (op) | (((unsigned long)(bit16) & 0x1) << 15) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1) + +#define VX_SPE2_HH(op, xop, bit16, bits19_20) (OP (op) |(((unsigned long)(bit16) & 0x1) << 15) | (((unsigned long)(bits19_20) & 0x3) << 11) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3) + +#define VX_SPE2_EVMAR(op, xop) (OP (op) | ((unsigned long)(0x1) << 11) | (((unsigned long)(xop)) & 0x7ff)) +#define VX_SPE2_EVMAR_MASK (VX_SPE2_EVMAR(0x3f, 0x7ff) | ((unsigned long)(0x1) << 11)) + /* A VX_MASK with the VA field fixed. */ #define VXVA_MASK (VX_MASK | (0x1f << 16)) @@ -3308,8 +3478,10 @@ extract_off_lsp (unsigned long insn, #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS #define PPCE300 PPC_OPCODE_E300 #define PPCSPE PPC_OPCODE_SPE +#define PPCSPE2 PPC_OPCODE_SPE2 #define PPCISEL PPC_OPCODE_ISEL #define PPCEFS PPC_OPCODE_EFS +#define PPCEFS2 PPC_OPCODE_EFS2 #define PPCBRLK PPC_OPCODE_BRLOCK #define PPCPMR PPC_OPCODE_PMR #define PPCTMR PPC_OPCODE_TMR @@ -3651,16 +3823,21 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, @@ -3668,10 +3845,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, +{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, +{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, @@ -3681,19 +3860,43 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, +{"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, +{"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, +{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, +{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, +{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, @@ -3701,10 +3904,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, @@ -3716,30 +3921,41 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, -{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}}, +{"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}}, {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, +{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, -{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}}, +{"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, +{"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}}, {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, +{"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, +{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, -{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, -{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, +{"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, @@ -3868,6 +4084,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -3878,6 +4095,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -3893,8 +4111,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, +{"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -3979,16 +4199,24 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, +{"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -3997,6 +4225,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, +{"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -4033,21 +4265,33 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, +{"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, +{"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, +{"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -6377,6 +6621,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, +{"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, @@ -6495,6 +6740,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, +{"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, @@ -8280,7 +8526,829 @@ const struct powerpc_macro powerpc_macros[] = { {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, + +/* old SPE instructions have new names with the same opcodes */ +{"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"}, +{"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"}, +{"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"}, +{"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"}, +{"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"}, +{"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"}, +{"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"}, +{"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"}, +{"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"}, +{"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"}, +{"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"}, +{"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"}, +{"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"}, +{"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"}, +{"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"}, +{"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"}, +{"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"}, +{"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"}, +{"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"}, +{"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"}, +{"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"}, +{"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"}, +{"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"}, + +/* SPE2 instructions which just are mapped to SPE2 */ +{"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"}, +{"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"}, +{"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"}, +{"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"} }; const int powerpc_num_macros = sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); + +/* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */ +const struct powerpc_opcode spe2_opcodes[] = { +{"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, +{"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, +{"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, +{"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, +{"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, +{"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, +{"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, +{"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, +{"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, +{"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}}, +{"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}}, +{"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, +{"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, +{"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, +{"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, +{"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, +{"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}}, +{"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, +{"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, +{"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, +{"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, +{"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, +{"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, +{"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, +{"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}}, +{"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}}, +{"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}}, +{"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}}, +{"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, +{"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, +{"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, +{"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, +{"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}}, +{"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, +{"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, +{"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}}, +{"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, +{"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, +{"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, +{"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, +{"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}}, +{"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}}, +{"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, +{"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +{"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, +}; + +const int spe2_num_opcodes = + sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]); -- 2.7.4