diff mbox series

[v4,6/9] arm: Support Capstone in disas_set_info

Message ID 20170928165414.7339-7-richard.henderson@linaro.org
State Superseded
Headers show
Series Support the Capstone disassembler | expand

Commit Message

Richard Henderson Sept. 28, 2017, 4:54 p.m. UTC
Tested-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 disas.c          |  3 +++
 target/arm/cpu.c | 21 ++++++++++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

-- 
2.13.5

Comments

Philippe Mathieu-Daudé Oct. 2, 2017, 1:37 p.m. UTC | #1
On 09/28/2017 01:54 PM, Richard Henderson wrote:
> Tested-by: Alex Bennée <alex.bennee@linaro.org>

> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


aarch32 (not thumb), aarch64 (without switching to aarch32):

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>   disas.c          |  3 +++

>   target/arm/cpu.c | 21 ++++++++++++++++++---

>   2 files changed, 21 insertions(+), 3 deletions(-)

> 

> diff --git a/disas.c b/disas.c

> index 1c44514254..23c4742f8d 100644

> --- a/disas.c

> +++ b/disas.c

> @@ -451,6 +451,7 @@ void disas(FILE *out, void *code, unsigned long size)

>       print_insn = print_insn_ppc;

>   #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)

>       print_insn = print_insn_arm_a64;

> +    s.info.cap_arch = CS_ARCH_ARM64;

>   #elif defined(__alpha__)

>       print_insn = print_insn_alpha;

>   #elif defined(__sparc__)

> @@ -458,6 +459,8 @@ void disas(FILE *out, void *code, unsigned long size)

>       s.info.mach = bfd_mach_sparc_v9b;

>   #elif defined(__arm__)

>       print_insn = print_insn_arm;

> +    s.info.cap_arch = CS_ARCH_ARM;

> +    /* TCG only generates code for arm mode.  */

>   #elif defined(__MIPSEB__)

>       print_insn = print_insn_big_mips;

>   #elif defined(__MIPSEL__)

> diff --git a/target/arm/cpu.c b/target/arm/cpu.c

> index 4300de66e2..e5f84066b4 100644

> --- a/target/arm/cpu.c

> +++ b/target/arm/cpu.c

> @@ -33,6 +33,7 @@

>   #include "sysemu/sysemu.h"

>   #include "sysemu/hw_accel.h"

>   #include "kvm_arm.h"

> +#include "disas/capstone.h"

>   

>   static void arm_cpu_set_pc(CPUState *cs, vaddr value)

>   {

> @@ -489,10 +490,24 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)

>   #if defined(CONFIG_ARM_A64_DIS)

>           info->print_insn = print_insn_arm_a64;

>   #endif

> -    } else if (env->thumb) {

> -        info->print_insn = print_insn_thumb1;

> +        info->cap_arch = CS_ARCH_ARM64;

>       } else {

> -        info->print_insn = print_insn_arm;

> +        int cap_mode;

> +        if (env->thumb) {

> +            info->print_insn = print_insn_thumb1;

> +            cap_mode = CS_MODE_THUMB;

> +        } else {

> +            info->print_insn = print_insn_arm;

> +            cap_mode = CS_MODE_ARM;

> +        }

> +        if (arm_feature(env, ARM_FEATURE_V8)) {

> +            cap_mode |= CS_MODE_V8;

> +        }

> +        if (arm_feature(env, ARM_FEATURE_M)) {

> +            cap_mode |= CS_MODE_MCLASS;

> +        }

> +        info->cap_arch = CS_ARCH_ARM;

> +        info->cap_mode = cap_mode;

>       }

>       if (bswap_code(arm_sctlr_b(env))) {

>   #ifdef TARGET_WORDS_BIGENDIAN

>
diff mbox series

Patch

diff --git a/disas.c b/disas.c
index 1c44514254..23c4742f8d 100644
--- a/disas.c
+++ b/disas.c
@@ -451,6 +451,7 @@  void disas(FILE *out, void *code, unsigned long size)
     print_insn = print_insn_ppc;
 #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
     print_insn = print_insn_arm_a64;
+    s.info.cap_arch = CS_ARCH_ARM64;
 #elif defined(__alpha__)
     print_insn = print_insn_alpha;
 #elif defined(__sparc__)
@@ -458,6 +459,8 @@  void disas(FILE *out, void *code, unsigned long size)
     s.info.mach = bfd_mach_sparc_v9b;
 #elif defined(__arm__)
     print_insn = print_insn_arm;
+    s.info.cap_arch = CS_ARCH_ARM;
+    /* TCG only generates code for arm mode.  */
 #elif defined(__MIPSEB__)
     print_insn = print_insn_big_mips;
 #elif defined(__MIPSEL__)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4300de66e2..e5f84066b4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -33,6 +33,7 @@ 
 #include "sysemu/sysemu.h"
 #include "sysemu/hw_accel.h"
 #include "kvm_arm.h"
+#include "disas/capstone.h"
 
 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
 {
@@ -489,10 +490,24 @@  static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 #if defined(CONFIG_ARM_A64_DIS)
         info->print_insn = print_insn_arm_a64;
 #endif
-    } else if (env->thumb) {
-        info->print_insn = print_insn_thumb1;
+        info->cap_arch = CS_ARCH_ARM64;
     } else {
-        info->print_insn = print_insn_arm;
+        int cap_mode;
+        if (env->thumb) {
+            info->print_insn = print_insn_thumb1;
+            cap_mode = CS_MODE_THUMB;
+        } else {
+            info->print_insn = print_insn_arm;
+            cap_mode = CS_MODE_ARM;
+        }
+        if (arm_feature(env, ARM_FEATURE_V8)) {
+            cap_mode |= CS_MODE_V8;
+        }
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            cap_mode |= CS_MODE_MCLASS;
+        }
+        info->cap_arch = CS_ARCH_ARM;
+        info->cap_mode = cap_mode;
     }
     if (bswap_code(arm_sctlr_b(env))) {
 #ifdef TARGET_WORDS_BIGENDIAN