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[209.132.180.67]) by mx.google.com with ESMTP id n1si6914790pge.830.2017.10.18.05.58.57; Wed, 18 Oct 2017 05:58:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSC7llOi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752466AbdJRM6x (ORCPT + 27 others); Wed, 18 Oct 2017 08:58:53 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44529 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752365AbdJRM6m (ORCPT ); Wed, 18 Oct 2017 08:58:42 -0400 Received: by mail-wr0-f193.google.com with SMTP id l24so4935027wre.1 for ; Wed, 18 Oct 2017 05:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kxSAjGL/a34TNgfjLAncz+CWDVEX3RnZVjD4dYHs6uY=; b=CSC7llOi+CSDuvI0eDkuyYgJvqEHxa5VFcAJ16okMfkclPLjJAd3ScfZesQU8/S7/E e1miExDxX90kpNHUrpdJMpZGr7fBfjFYkFLsXws9MwVvcIZTfTXUo5cStz3zJ1lyNsiB Sbr44Ga3s2z6S1+C8wr48SDu3fsEuYtVBZuIA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kxSAjGL/a34TNgfjLAncz+CWDVEX3RnZVjD4dYHs6uY=; b=p5SBc012ej21xJxJp/13ga7BhuKU/q7+fO3E4gzLSEBt9mTtSxC5uTO5IqAmmKbP3z bE4btosO4+mQDMLhCBur7Zf7viCtjH82pMP99HHs4iTVi7kLMdgZPw2BCX+oEH3GE2Er hU/RSV++5cn682Hx+6zYbyJL9UXUdIfrBvwqZe0PYjjBleZdlhalmZ5idO3MjXYxDq/U DbphTj3iZtR+LdBkhUNIPwOi2RTSsaj9nHyfIxs5us4v+G4ljThMP19NWcQOTTzuqkMi 4Ilen0Yc6tz6w7cXATl0rMHGMfEXqECArwpUW9YEw5x/9/zY9wfXygetZzTQj+QLP5TT B81w== X-Gm-Message-State: AMCzsaWSdwxYORZeETIYviNVMnRAphUBbFthhI2Szv16Bavb4wpHJY8h ItquiUq5tdy+uf/EG16iksKP/Q== X-Google-Smtp-Source: ABhQp+RAyW47WVG6h4B6M7+mzJef8uPRDsNJy9U2hXALlcd5WA+HVDx6IQU2449tgnb7JK8d96+qtg== X-Received: by 10.223.195.110 with SMTP id e43mr6342802wrg.219.1508331521655; Wed, 18 Oct 2017 05:58:41 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.70.168]) by smtp.gmail.com with ESMTPSA id m23sm14169908wrm.75.2017.10.18.05.58.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 05:58:41 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v6 3/5] clocksource: stm32: only use 32 bits timers Date: Wed, 18 Oct 2017 14:58:24 +0200 Message-Id: <1508331506-23782-4-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 16 bits hardware are not enough accure to be used. Do no allow them to be probed by tested max counter value. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 67dcf48..c834648 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -81,9 +81,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static int __init stm32_clockevent_init(struct device_node *node) { struct reset_control *rstc; - unsigned long max_delta; - int ret, bits, prescaler = 1; + unsigned long max_arr; struct timer_of *to; + int ret; to = kzalloc(sizeof(*to), GFP_KERNEL); if (!to) @@ -113,29 +113,27 @@ static int __init stm32_clockevent_init(struct device_node *node) /* Detect whether the timer is 16 or 32 bits */ writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR); + if (max_arr != ~0U) { + pr_err("32 bits timer is needed\n"); + ret = -EINVAL; + goto deinit; } + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x60, max_delta); - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - node, bits); + timer_of_period(to), 0x60, ~0U); return 0; +deinit: + timer_of_deinit(to); err: kfree(to); return ret;