| Message ID | CADnVucA9xsr07a9r3QS5k=vytWQ_WY298tFJfy857K17xVYZwQ@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [AArch64,testsuite] gcc.target/aarch64/extend.c: xfails for ilp32 | expand |
On Tue, Oct 24, 2017 at 11:27 AM, Charles Baylis <charles.baylis@linaro.org> wrote: > In ILP32, GCC fails to merge pointer arithmetic into the addressing > mode of a load instruction, as > add w0, w0, w1, lsl 2 > ldr w0, [x0] > is not equivalent to: > ldr w0, [x0, w1, lsl 2] > > Shows the expected FAIL->XFAILs on aarch64-linux-gnu_ilp32, no > regressions on aarch64-linux-gnu. Then this is not a xfail but rather the dg-final should be skipped for ilp32. xfail means the failure can be fixed in the future but in this case, the failure is not fixable. Something like: { target { !ilp32 } } or (what I used in my changes which I was going to submit but had higher priorities than submitting testcase fixes): { target { lp64 } } Thanks, Andrew > > gcc/testsuite: > <date> Charles Baylis <charles.baylis@linaro.org> > > * gcc.target/aarch64/extend.c (ldr_uxtw): Add xfail for ilp32. > (ldr_uxtw0): Likewise. > (ldr_sxtw): Likewise. > (ldr_sxtw0): Likewise.
On 24 October 2017 at 19:40, Andrew Pinski <pinskia@gmail.com> wrote: > On Tue, Oct 24, 2017 at 11:27 AM, Charles Baylis > <charles.baylis@linaro.org> wrote: >> In ILP32, GCC fails to merge pointer arithmetic into the addressing >> mode of a load instruction, as >> add w0, w0, w1, lsl 2 >> ldr w0, [x0] >> is not equivalent to: >> ldr w0, [x0, w1, lsl 2] >> >> Shows the expected FAIL->XFAILs on aarch64-linux-gnu_ilp32, no >> regressions on aarch64-linux-gnu. > > Then this is not a xfail but rather the dg-final should be skipped for ilp32. > xfail means the failure can be fixed in the future but in this case, > the failure is not fixable. > > Something like: > { target { !ilp32 } } > > or (what I used in my changes which I was going to submit but had > higher priorities than submitting testcase fixes): > > { target { lp64 } } Patch updated. gcc/testsuite/ChangeLog: <date> Charles Baylis <charles.baylis@linaro.org> * gcc.target/aarch64/extend.c (ldr_uxtw): Don't scan assembler for ilp32. (ldr_uxtw0): Likewise. (ldr_sxtw): Likewise. (ldr_sxtw0): Likewise. From a6cf8b5e0928fa2c775f4ef1c3d607cc4700305f Mon Sep 17 00:00:00 2001 From: Charles Baylis <charles.baylis@linaro.org> Date: Tue, 24 Oct 2017 14:22:11 +0100 Subject: [PATCH 2/4] [AArch64] gcc.target/aarch64/extend.c: Skip ldr tests for ilp32 gcc/testsuite/ChangeLog: <date> Charles Baylis <charles.baylis@linaro.org> * gcc.target/aarch64/extend.c (ldr_uxtw): Don't scan assembler for ilp32. (ldr_uxtw0): Likewise. (ldr_sxtw): Likewise. (ldr_sxtw0): Likewise. --- gcc/testsuite/gcc.target/aarch64/extend.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/extend.c b/gcc/testsuite/gcc.target/aarch64/extend.c index f399e55..be89cba 100644 --- a/gcc/testsuite/gcc.target/aarch64/extend.c +++ b/gcc/testsuite/gcc.target/aarch64/extend.c @@ -4,28 +4,28 @@ int ldr_uxtw (int *arr, unsigned int i) { - /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw #?2]" } } */ + /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw #?2]" { target { ! ilp32 } } } } */ return arr[i]; } int ldr_uxtw0 (char *arr, unsigned int i) { - /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw]" } } */ + /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw]" { target { ! ilp32 } } } } */ return arr[i]; } int ldr_sxtw (int *arr, int i) { - /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw #?2]" } } */ + /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw #?2]" { target { ! ilp32 } } } } */ return arr[i]; } int ldr_sxtw0 (char *arr, int i) { - /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw]" } } */ + /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw]" { target { ! ilp32 } } } } */ return arr[i]; }
From 70d43eb4f783d434e7996ebdde40b4ffea4a4a20 Mon Sep 17 00:00:00 2001
From: Charles Baylis <charles.baylis@linaro.org>
Date: Tue, 24 Oct 2017 14:22:11 +0100
Subject: [PATCH 2/4] [AArch64] gcc.target/aarch64/extend.c: xfails for ilp32
<date> Charles Baylis <charles.baylis@linaro.org>
* gcc.target/aarch64/extend.c (ldr_uxtw): Add xfail for ilp32.
(ldr_uxtw0): Likewise.
(ldr_sxtw): Likewise.
(ldr_sxtw0): Likewise.
---
gcc/testsuite/gcc.target/aarch64/extend.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/extend.c b/gcc/testsuite/gcc.target/aarch64/extend.c
index f399e55..a9eb852 100644
--- a/gcc/testsuite/gcc.target/aarch64/extend.c
+++ b/gcc/testsuite/gcc.target/aarch64/extend.c
@@ -4,28 +4,28 @@
int
ldr_uxtw (int *arr, unsigned int i)
{
- /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw #?2]" } } */
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw #?2]" { xfail { aarch64*-*-* && ilp32 } } } } */
return arr[i];
}
int
ldr_uxtw0 (char *arr, unsigned int i)
{
- /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw]" } } */
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw]" { xfail { aarch64*-*-* && ilp32 } } } } */
return arr[i];
}
int
ldr_sxtw (int *arr, int i)
{
- /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw #?2]" } } */
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw #?2]" { xfail { aarch64*-*-* && ilp32 } } } } */
return arr[i];
}
int
ldr_sxtw0 (char *arr, int i)
{
- /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw]" } } */
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw]" { xfail { aarch64*-*-* && ilp32 } } } } */
return arr[i];
}
--
2.7.4
In ILP32, GCC fails to merge pointer arithmetic into the addressing mode of a load instruction, as add w0, w0, w1, lsl 2 ldr w0, [x0] is not equivalent to: ldr w0, [x0, w1, lsl 2] Shows the expected FAIL->XFAILs on aarch64-linux-gnu_ilp32, no regressions on aarch64-linux-gnu. gcc/testsuite: <date> Charles Baylis <charles.baylis@linaro.org> * gcc.target/aarch64/extend.c (ldr_uxtw): Add xfail for ilp32. (ldr_uxtw0): Likewise. (ldr_sxtw): Likewise. (ldr_sxtw0): Likewise.