diff mbox series

[edk2,edk2-platforms,v4,21/34] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards

Message ID 20171110142127.12018-22-ard.biesheuvel@linaro.org
State New
Headers show
Series add support for Socionext SynQuacer | expand

Commit Message

Ard Biesheuvel Nov. 10, 2017, 2:21 p.m. UTC 
Implement workaround suggested by Socionext to get legacy endpoints
with 32-bit BARs working. This fixes the issue on Developer Box with
the onboard ASM1061 SATA controller.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

---
 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

-- 
2.11.0

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diff mbox series

Patch

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
index b5bfea8e0e75..1bbef5b6cf98 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
@@ -32,10 +32,13 @@ 
 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO           0x2
 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0         0x4
 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1         0x5
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH                BIT12
 
 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0                   0x908
 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN         BIT31
 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE    BIT28
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT    0xF
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT    0xFF
 
 #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0                   0x90C
 #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0                 0x910
@@ -297,8 +300,9 @@  PciInitController (
     RootBridge->Mem.Base,
     RootBridge->Mem.Base,
     RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
-    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
-    0);
+    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
+    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
+    IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
 
   // Region 1: Type 0 config space
   ConfigureWindow (DbiBase, 1,