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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id a14si5221247pgv.479.2017.11.10.06.24.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:24:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ONK8ReIf; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D767E203555E3; Fri, 10 Nov 2017 06:18:58 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C686C2035522D for ; Fri, 10 Nov 2017 06:18:57 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id 15so8748167wrb.5 for ; Fri, 10 Nov 2017 06:23:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KTsafCwkTqW3gueFe7vbZCrWCLlwBtcQ1VmtcCg0mI4=; b=ONK8ReIf/Zvss27wQc0US+BgVoBYiXE1Dx9DFX3Od6B8ymot0u+MG0jV+q47y9esFJ BI8u+vhSwBBZLCcZdiK11Bu5WlT5E7ALjXA28bR8Pa51PBzoHkbTsaLvG6YF/DEhqxJf ika1OaZCEWlDzV2XTp5ZMWFMH/q+OlLu93r8M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KTsafCwkTqW3gueFe7vbZCrWCLlwBtcQ1VmtcCg0mI4=; b=DZJWpeXHAkJ0aPeHJkrG4ml8MwJexbYEN/VO4m+w+uFkLgRO/BBGnRDAnIQF2H5diL RScLj9DxqG77RTpQ6fjGn8FOO8FFUd9HY54g3u2hjJgVo0V/vGnWwnBdgaHFPKJ8leCV sfcGpbM3eNwrBmhFPxMrLFiPB3yppVLf1miVqSAhz6yhnAz/rroe0fIN6Jssi30FaiCv ujf0C1fBTFjQ91wSiqP61bzp62Jm+q1vLsHQNZJbkrpprLLGf7SRdv/RH2Ng5RAkhUCv zsBWUovlPQIcy6BcYuBgRuQO0XqppRCObUH5EA2oAyCOkj9HLmWZOTzMZVBmeg7qdMng IsQw== X-Gm-Message-State: AJaThX45C7DPItde+pPNFyqZSOuR1lNvBk4pFWIKGzZmJhscsrfPYk4D /E1bOAYIPMS17Bw8MvWe3cQqT0Ed06k= X-Received: by 10.223.156.138 with SMTP id d10mr477708wre.214.1510323779157; Fri, 10 Nov 2017 06:22:59 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.22.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:58 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Fri, 10 Nov 2017 14:21:21 +0000 Message-Id: <20171110142127.12018-29-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110142127.12018-1-ard.biesheuvel@linaro.org> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 28/34] Silicon/SynQuacer: implement PEIM that exposes GPIO PPI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" In order to be able to sample the state of the DIP switches at early boot on the Developer Box platform, implement the GPIO PPI based on the GPIO block that is implemented in the SynQuacer SoC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c | 203 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf | 47 +++++ 2 files changed, 250 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c new file mode 100644 index 000000000000..24d08b4e5899 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c @@ -0,0 +1,203 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include + +#define PDR(x) (SYNQUACER_GPIO_BASE + 4 * (GPIO_PIN (x) >> 3)) +#define DDR(x) (SYNQUACER_GPIO_BASE + 0x10 + 4 * (GPIO_PIN (x) >> 3)) +#define PFR(x) (SYNQUACER_GPIO_BASE + 0x20 + 4 * (GPIO_PIN (x) >> 3)) + +#define GPIO_BIT(x) (1U << (GPIO_PIN (x) % 8)) + +STATIC CONST UINTN mGpioPinCount = 32; + +/** + + Gets the state of a GPIO pin + + @param This Pointer to protocol + @param Gpio Which pin to read + @param Value State of the pin + + @retval EFI_SUCCESS GPIO state returned in Value + @retval EFI_INVALID_PARAMETER Value is NULL + @retval EFI_NOT_FOUND Pin does not exit + +**/ +STATIC +EFI_STATUS +EFIAPI +GpioGet ( + IN EMBEDDED_GPIO_PPI *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT UINTN *Value + ) +{ + if (Value == NULL) { + return EFI_INVALID_PARAMETER; + } + if (GPIO_PORT (Gpio) > 0 || GPIO_PIN (Gpio) >= mGpioPinCount) { + return EFI_NOT_FOUND; + } + + *Value = ((MmioRead32 (PDR (GPIO_PIN (Gpio))) & GPIO_BIT (Gpio)) != 0); + + return EFI_SUCCESS; +} + +/** + + Sets the state of a GPIO pin + + @param This Pointer to protocol + @param Gpio Which pin to modify + @param Mode Mode to set + + @retval EFI_SUCCESS GPIO set as requested + @retval EFI_INVALID_PARAMETER Invalid mode + @retval EFI_NOT_FOUND Pin does not exit + +**/ +STATIC +EFI_STATUS +EFIAPI +GpioSet ( + IN EMBEDDED_GPIO_PPI *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_MODE Mode + ) +{ + if (GPIO_PORT (Gpio) > 0 || GPIO_PIN (Gpio) >= mGpioPinCount) { + return EFI_NOT_FOUND; + } + + switch (Mode) { + case GPIO_MODE_INPUT: + MmioAnd32 (DDR (GPIO_PIN (Gpio)), ~GPIO_BIT (Gpio)); + break; + + case GPIO_MODE_OUTPUT_0: + MmioOr32 (DDR (GPIO_PIN (Gpio)), GPIO_BIT (Gpio)); + MmioAnd32 (PDR (GPIO_PIN (Gpio)), ~GPIO_BIT (Gpio)); + break; + + case GPIO_MODE_OUTPUT_1: + MmioOr32 (DDR (GPIO_PIN (Gpio)), GPIO_BIT (Gpio)); + MmioOr32 (PDR (GPIO_PIN (Gpio)), GPIO_BIT (Gpio)); + break; + + default: + return EFI_INVALID_PARAMETER; + } + return EFI_SUCCESS; +} + + +/** + + Gets the mode (function) of a GPIO pin + + @param This Pointer to protocol + @param Gpio Which pin + @param Mode Pointer to output mode value + + @retval EFI_SUCCESS Mode value retrieved + @retval EFI_INVALID_PARAMETER Mode is NULL + @retval EFI_NOT_FOUND Pin does not exit + +**/ +STATIC +EFI_STATUS +EFIAPI +GpioGetMode ( + IN EMBEDDED_GPIO_PPI *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT EMBEDDED_GPIO_MODE *Mode + ) +{ + if (Mode == NULL) { + return EFI_INVALID_PARAMETER; + } + if (GPIO_PORT (Gpio) > 0 || GPIO_PIN (Gpio) >= mGpioPinCount) { + return EFI_NOT_FOUND; + } + + if (!(MmioRead32 (DDR (GPIO_PIN (Gpio))) & GPIO_BIT (Gpio))) { + *Mode = GPIO_MODE_INPUT; + } else if (!(MmioRead32 (PDR (GPIO_PIN (Gpio))) & GPIO_BIT (Gpio))) { + *Mode = GPIO_MODE_OUTPUT_0; + } else { + *Mode = GPIO_MODE_OUTPUT_1; + } + return EFI_SUCCESS; +} + + +/** + + Sets the pull-up / pull-down resistor of a GPIO pin + + @param This Pointer to PPI + @param Gpio Port/pin index + @param Pull The pullup/pulldown mode to set + + @retval EFI_SUCCESS Mode was set + @retval EFI_NOT_FOUND Pin does not exist + @retval EFI_UNSUPPORTED Action not supported + +**/ +STATIC +EFI_STATUS +EFIAPI +GpioSetPull ( + IN EMBEDDED_GPIO_PPI *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_PULL Pull + ) +{ + if (Pull != GPIO_PULL_NONE) { + return EFI_UNSUPPORTED; + } + if (GPIO_PORT (Gpio) > 0 || GPIO_PIN (Gpio) >= mGpioPinCount) { + return EFI_NOT_FOUND; + } + return EFI_SUCCESS; +} + +STATIC EMBEDDED_GPIO_PPI mGpioPpi = { + GpioGet, + GpioSet, + GpioGetMode, + GpioSetPull, +}; + +STATIC CONST EFI_PEI_PPI_DESCRIPTOR mEmbeddedGpioPpiDescriptor = { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEdkiiEmbeddedGpioPpiGuid, + &mGpioPpi +}; + +EFI_STATUS +EFIAPI +SynQuacerGpioPeiEntryPoint ( + IN EFI_PEI_FILE_HANDLE FfsHeader, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + return PeiServicesInstallPpi (&mEmbeddedGpioPpiDescriptor); +} diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf new file mode 100644 index 000000000000..dbb5e9d4c53a --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf @@ -0,0 +1,47 @@ +#/* @file +# +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SynQuacerGpioPei + FILE_GUID = 55a981a5-f371-4ba3-93a5-37fa0ca95089 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SynQuacerGpioPeiEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# +# + +[Sources] + SynQuacerGpioPei.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + IoLib + PeimEntryPoint + PeiServicesLib + +[Ppis] + gEdkiiEmbeddedGpioPpiGuid ## PRODUCES + +[Depex] + TRUE