From patchwork Tue Nov 14 08:52:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118862 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2785096qgn; Tue, 14 Nov 2017 00:54:21 -0800 (PST) X-Google-Smtp-Source: AGs4zMb3NQN8Yzc2HRI1EDco97BE4HP8iFMPYIxJ75NF8ZgZRXyg4EeMXVPSdDWQbqLHL4efZAQn X-Received: by 10.84.131.68 with SMTP id 62mr9955076pld.185.1510649661436; Tue, 14 Nov 2017 00:54:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510649661; cv=none; d=google.com; s=arc-20160816; b=yfnH1CUkJhSQ/lv3xDFA9TLBjKyuMvPLbQ1PWVyTkcIYEuYAi/TS65+qGkSb06U7jq 6MqE4LPkD+p1EZ46PNPgV7F6RpAcX8EbGKLe08KMom0qBJhMKOJJ5ck5ru8MrqKql9zf V28VEDvvw19mI6xq3UPdyxdvpfN04ebWm/XzzjWXRjVLYFVx+BLTuZBJ1TiISQSgVQeM +Bm/5jHlVeWDPr+9uCEagBbtX7w5n1vXV5s777dP0szblHrLUzjs1hdxu8bNkP86HNpx eDXrukGy3GTZh8BL5yjqNrXqTOJmMsqBBhEAqRGDRgO/VzhNpZqQdE1ivCNcFDAQD7+t hxEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Nfj8++k29HNoLYrhWs1J4XXQ18Xb25URUD1NYtgCZmg=; b=tu4J5lPvI9ZGFKYEwAS/oXDhWB07WbvXgi0kQdiEx/xCxc0O8fl4jR2ITsmXINLbBF aRZuEDlZKvTcG3eJEtOECN3tD7wRb9lC6rH6VqwyFON7kwtqHF6tFsLbACYIP6pMHI54 8XpCYnfneH7p5ZnchcBE2FFRH6YXcN3T1nW/ZD4xrPyu6O8wU2nExd5MibxeBfNAQiZs WbnYCCVwbiX0HojM6V9kVFa3f/o3TNOJYjAG3n1542l9fW2k0JDOv4+MDvqlw3xIv0dF WW1ByQVRNgFPHbTpFkP8sCLSMIuOL9WyhKmr60/V9m/emKph0MWc2v92Jtx2/xU0VAmS 5mQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HUDZ3akv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x8si11130279pgq.460.2017.11.14.00.54.21; Tue, 14 Nov 2017 00:54:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HUDZ3akv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753462AbdKNIyT (ORCPT + 6 others); Tue, 14 Nov 2017 03:54:19 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:46216 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753147AbdKNIxd (ORCPT ); Tue, 14 Nov 2017 03:53:33 -0500 Received: by mail-wr0-f195.google.com with SMTP id y42so16808958wrd.3 for ; Tue, 14 Nov 2017 00:53:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CNfhm8yx6x+a0f51NOrdEx0YCg7fzpeQaqJDNAp1+A4=; b=HUDZ3akv4NPiSYUhlKwryP9JV2Y2LY7NQqildsze5iFJfOvd96cKf2HhchxIgfHUlU lE1S/Fy/lLExG+GblzII2wHizI84oxUWcSyzKQRasnrz8+QfJ5KxAdrv468KADrgNq6Z GWwgPs12xD0DtbKBwWO1lc1nF/1rrj9bGKD4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CNfhm8yx6x+a0f51NOrdEx0YCg7fzpeQaqJDNAp1+A4=; b=eBtgtWFndEsZ08xelf9luoMT95wLTxgrsTIXQZQq8srvbeKuobqO+Ah85zHAyqi0ZS 01+FM6xXlMXTFoDANbgOAVLExsn2ZPUGQelA9nsvLRLsW+Bb+GddqmEBA/ciLba1KANh QsvjaYs0AgJqXahvPWcaZQ5V/av4j5CYmT05p+Y1fG/kPx4DZVbxWkfiP1WtkQPHDwyE 6n1X0wSvSBe18idit2hSrckWN82mcJ7/T2lFTayBxG+A8MA3kPDVFL/zoTI1gc/kCOxq WjPJBpCKfk7DzHHEnoNd5XbJO/hZk4WCeIRXXBe/+hgHl5NZ7l10ZZiK3RwfwKEVeZMi XoYw== X-Gm-Message-State: AJaThX6/JreXUWOwnbUfOe5btxH26apHeZ5J851n8/05OoGrJXvj7heK 5b/PYnc+DL8yfHEQG1Kz7USGJw== X-Received: by 10.223.166.103 with SMTP id k94mr9504691wrc.22.1510649610589; Tue, 14 Nov 2017 00:53:30 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.205.30]) by smtp.gmail.com with ESMTPSA id g28sm22894551wra.31.2017.11.14.00.53.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Nov 2017 00:53:30 -0800 (PST) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com, sudeep.holla@arm.com, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v8 5/6] clocksource: stm32: add clocksource support Date: Tue, 14 Nov 2017 09:52:42 +0100 Message-Id: <1510649563-22975-6-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The stm32 timer hardware is currently only used as a clock event device, but it can be utilized as a clocksource as well. Implement this by enabling the free running counter in the hardware block and converting the clock event part from a count down event timer to a comparator based timer. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 116 +++++++++++++++++++++++++++++--------- 1 file changed, 88 insertions(+), 28 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8173bcf..c0a62cd 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "timer-of.h" @@ -23,16 +25,16 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) @@ -42,28 +44,44 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; + + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long val; + + val = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(val, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } @@ -75,12 +93,57 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; } -static int __init stm32_clockevent_init(struct device_node *node) +static void __init stm32_clockevent_init(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), MIN_DELTA, ~0U); +} + +static void __iomem *stm32_timer_cnt __read_mostly; +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, + timer_of_base(to) + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), 250, 32, + clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { struct reset_control *rstc; unsigned long max_arr; @@ -92,12 +155,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -ENOMEM; to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; to->clkevt.rating = 200; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -122,23 +186,19 @@ static int __init stm32_clockevent_init(struct device_node *node) goto deinit; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); - - writel_relaxed(0, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; - clockevents_config_and_register(&to->clkevt, - timer_of_period(to), MIN_DELTA, ~0U); + stm32_clockevent_init(to); return 0; deinit: - timer_of_exit(to); + timer_of_cleanup(to); err: kfree(to); return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);