From patchwork Fri Dec 8 11:32:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 121151 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp539341qgn; Fri, 8 Dec 2017 03:33:20 -0800 (PST) X-Google-Smtp-Source: AGs4zMbqAXRj3rakJQM2PTZHb/c9Ij7FpyFB+jJajcwKm49Bgc3lLN2usM6Tfz/LaRfirRUBf5Q7 X-Received: by 10.84.251.140 with SMTP id w12mr17907450pll.310.1512732800199; Fri, 08 Dec 2017 03:33:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512732800; cv=none; d=google.com; s=arc-20160816; b=SJhVd7j7fU0AWc0iEN1/9aZdTwXyTis1CsZBoT2PhA60AiEFYzrMGCzfWY0WBEn/mz 8lnDks7e22AqVmuMh/2vfj+M2LSmYwm+Jm/Vt5f57mh3cp0QpKT2SPbQ/ijfjBcbU+Y4 Q8sqHILRIl4eOwW2REcBffhBzx8B8zb0R+JAjsLcCQ4dQ+RkVLOvQWt6tBGo7i13w1vc ar4FRSaLVb4ZfMKG7ScBiXD6aK+hDFLhZCHqyBU79/0HYRFKxc6C8c50SJm4wXJC2eWU eJ5fdHQ9E8OH6HwYgVB37lE1oGO21SfkW/qQ7FIGucir2pniRhc0rhSv2GL/LjnFocR9 LZSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=S70rdJOG7HVN8GjNMXo9TFNVjmSwjzyy8la8zv8cwxo=; b=CGYlH33jZsGFT/i8yuXW6i1nxtvjAtKtmTjNNRtmaAJ7awuuI4I5Kb5qYfoS1nuAa+ iAe5+cmLDyJtVZTfWVVEy2gS6B8nXAZIHNYP5QYQfVCYd0R3zrItpwnWCaHLxQ8VVfJv ZB4bQ4ZegB9znvQK18LVzMDb8NZfi/mpB2iXII8ACeGcCDc5PAaiPRvxeGh/rHjuQdTS jM4Ri90DAk05NvorOTsFCOhA0JUsM7iSvI9sModMMngvSNBYzQlekT+jLS4HcVO63YHB B4j1rilkDY43C3J0IRTmAsm8nLK8g5q+fwbvEXQDQc7sP4c4Kk+2M+NHONPXOiFByY5F VpWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Q6EKbDt7; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v11si5387943plg.3.2017.12.08.03.33.19; Fri, 08 Dec 2017 03:33:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Q6EKbDt7; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753448AbdLHLdS (ORCPT + 6 others); Fri, 8 Dec 2017 06:33:18 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:43338 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753262AbdLHLdJ (ORCPT ); Fri, 8 Dec 2017 06:33:09 -0500 Received: by mail-wm0-f65.google.com with SMTP id n138so2806914wmg.2 for ; Fri, 08 Dec 2017 03:33:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+ofLvKtyAnHtAQQFL19bsjsi2JNpkm6HYTbMdM+2Ntk=; b=Q6EKbDt7OHyEe2YbnwyiBt8V72uZfE5t6XfEafAzqw6dH7MaeKU+/5UW5ZKsc4Njm6 sv0ypmVoR7s/073x3OAUWdomEeQrQ660HozEeLXqZRqEP4SL7d4X6TESoXmirGkCPH6v DY5i3tqTqnafexSpatwMVs8Lw8Zy7Jpe+TPAI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+ofLvKtyAnHtAQQFL19bsjsi2JNpkm6HYTbMdM+2Ntk=; b=KXqYwr3tSTL4VObKUlMcxGJt+iEI8mRWehP1nxFGOrrNgvtOpg1g45DHLn8QFOgtRr cP6nOMdaJqdWwwM/dSN87L3CgogIy9uMevFoCaF5CTVicW2ZcQZpeZdCjtYok6GUDVc1 crEh+OVVr358nlZBP83+9rp+GJz7Q0UfCIycfmnvjZENIzz3tJuhZVUHQbx3OVmdmZPF lXZ50BWkYW9bVT1X757iyfXjQgUugXh+nyS/XvJ24xnN9OXqYeMgldajO+OYCeqgk19Z Og2xNO2w2LXa9iN98rtgy4zCSSJp41AK4advFh39mz17AZlRh6kLyGncBDFb629RgB/T aIzw== X-Gm-Message-State: AKGB3mK9VzF16iMEHehwaXfwHBkYQWJGuPNriU5q0qgFhyU53qYMatr+ qr078cgSn3lYwkDdC4OJLb78Xg== X-Received: by 10.28.91.74 with SMTP id p71mr4046428wmb.61.1512732788012; Fri, 08 Dec 2017 03:33:08 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.33.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:07 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v9 3/6] clocksource: stm32: only use 32 bits timers Date: Fri, 8 Dec 2017 12:32:47 +0100 Message-Id: <20171208113250.359-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Benjamin Gaignard The clock driving counters is at 90MHz so the maximum period for 16 bis counters is around 728us (2^16 / 90.000.000). For 32 bits counters this period is close 47 secondes which is more acceptable. When using 16 bits counters the kernel may not be able to boot because it has a too high overhead compare to the clockevent period. Downgrading the rating of 16bits counter won't change anything to this problem so this patch remove 16 bits counters support and makes sure that they won't be probed anymore. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index a45f1f1cd040..707808d91bf0 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -84,12 +84,16 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static bool stm32_timer_is_32bits(struct timer_of *to) +{ + return readl_relaxed(timer_of_base(to) + TIM_ARR) == ~0UL; +} + static int __init stm32_clockevent_init(struct device_node *node) { struct reset_control *rstc; - unsigned long max_delta; - int ret, bits, prescaler = 1; struct timer_of *to; + int ret; to = kzalloc(sizeof(*to), GFP_KERNEL); if (!to) @@ -118,31 +122,27 @@ static int __init stm32_clockevent_init(struct device_node *node) } /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + if (!stm32_timer_is_32bits(to)) { + pr_warn("Timer %pOF is a 16 bits timer\n", node); + ret = -EINVAL; + goto deinit; } + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, timer_of_period(to), - MIN_DELTA, max_delta); - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - node, bits); + MIN_DELTA, ~0U); return 0; +deinit: + timer_of_cleanup(to); err: kfree(to); return ret;