From patchwork Fri Dec 8 11:32:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 121155 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp540459qgn; Fri, 8 Dec 2017 03:34:36 -0800 (PST) X-Google-Smtp-Source: AGs4zMbgnOaHUxtu3nPMVOS3XlCTAuI6C4mL7gi7Wh0JnvsWasCmRFlhhJzhgeIa8DNddu0KeOKL X-Received: by 10.99.94.71 with SMTP id s68mr29523304pgb.242.1512732876603; Fri, 08 Dec 2017 03:34:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512732876; cv=none; d=google.com; s=arc-20160816; b=h0gpWDQ8f4zCKEF5xNqAm4P01pDq2Maq/qffTTpkYZb73xquDzotDpJMPPH/LIDah9 wPjfmOEgeYf+UK9qrYn3GGlOsA5KmoJNT76hc0Kg692dJzlCZIQC8IJIb6NlcP270WL3 EJiLqlwKqVua1Fi4pbjahRm3pVUoTznzYUZDxUFI8Xc6g8QK14ttKmt3+ufNJEt7rIXD BVMHdwnfzy1Xb9ncpTFWV4Kk8ZHFnXS+w+mHH1gd1n9HiNqIX8ay+mA9h9I4xmqMwsPT 86vfyklyIYqgAGrvpGlptWnvRvQASUBdhhQgvkPYQQSTakugHtVkzfZiOThmTz0f7pAE i5/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=KtaVjK3CJoXbgV1EFwf6ucQlBfpEMhp8d8d2kBoDcKg=; b=FWuMsHP/aMze0bNS8P9nsMKwz8MwAF8D7HbnqH48Qz6yU8AXcq9LmISA23Td3nhTVX 59q6bNVYUlAPrKfcWzSM7IQggN1wRxBuQv50sd+MH4Hpj5uj7NzY0lVN07ovnBoj1V0x Ucv6eIW7jksaeVA0Be02/dwJikM0iGG9d1z2U2g3jtgFwQLq4vIKd7YUKF3Ti2rxEQP6 /2EFgRYs8Zv61h2piF38FZTXCoDYMEI5XcpIhAF7c0eIm8KTUw7ULKMAxAol1lSj5jQw 7Kl6HImekAvhyS9IDY7+eWsGEDjMGg53d70AI0bYcDqUeh2OeopF3sllnVZo8R/FO0GZ foCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZvLMQoqg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n10si4371376plp.158.2017.12.08.03.34.36; Fri, 08 Dec 2017 03:34:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZvLMQoqg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753843AbdLHLee (ORCPT + 11 others); Fri, 8 Dec 2017 06:34:34 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44061 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753141AbdLHLdG (ORCPT ); Fri, 8 Dec 2017 06:33:06 -0500 Received: by mail-wr0-f193.google.com with SMTP id l22so10511119wrc.11 for ; Fri, 08 Dec 2017 03:33:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KtaVjK3CJoXbgV1EFwf6ucQlBfpEMhp8d8d2kBoDcKg=; b=ZvLMQoqgcu2j40a3r5+xcWhqJyPN/jiHLhp9ogxxTjiitnXp2U565bU/j4q86V8nVt H07pRYS3HGtNJaT0ds238a9dR6yj0G7+CB0abT+EbLnfFSaX+lqwrk+r89A1lX4WS5mq HLjJ8UcsTSOcxSPJVz++SwG0KTkyWhln8kGG4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KtaVjK3CJoXbgV1EFwf6ucQlBfpEMhp8d8d2kBoDcKg=; b=gEdywgVmXs98tfwX+uCbBAFrk0bY1VyAE2N9afgG6kJbyMGHk3MPxMOEbrII/3mhJM MzVHUBbUQS038ME5SQEOm0URo44eQ0d7EP9T7UuKJtnuIHILK3wUCyT8H8tTKtnkJv3v Hh5sZ+kLe9uTW7JKbwXsKQ6+MhG76Rlx1JdbZV5KFeKw0xjGUnVxPyKvPryhX86Wh89x 1fOHAWQAYqHZFNe+sZyXKNW9QfeL4ld/0sU+ZD8QM6IwBDHFNwOR5uRC+11IE6IpUPTG 1cW6kEdkHfYoZjsG88lf32JGjFBHUl3hXmBukiL+kvHzCT6//f5935tePL74NSrcDZtM 9G3A== X-Gm-Message-State: AJaThX76/BBuNGQNkI91pV3yhnuhiOThZuYgzFK5yCKRotSmC/QM8Fh7 cun/kCyKAKddeN2nG4piWcX4DQ== X-Received: by 10.223.201.138 with SMTP id f10mr27338458wrh.9.1512732785491; Fri, 08 Dec 2017 03:33:05 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.33.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:04 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v9 2/6] clocksource: stm32: increase min delta value Date: Fri, 8 Dec 2017 12:32:46 +0100 Message-Id: <20171208113250.359-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The CPU is a CortexM4 @ 200MHZ and the clocks driving the timers are at 90MHZ with a min delta at 1 you could have an interrupt each 0.01 ms which is really to much. By increase it to 0x60 it give more time (around 1 ms) to CPU to handle the interrupt. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index fc61fd18a182..a45f1f1cd040 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -36,6 +36,12 @@ #define TIM_EGR_UG BIT(0) +/* + * The clock driving the hardware is at 90MHZ with a MIN_DELTA + * at 0x60 it gives around 1 ms to the CPU to handle the interrupt + */ +#define MIN_DELTA 0x60 + static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); @@ -129,7 +135,8 @@ static int __init stm32_clockevent_init(struct device_node *node) writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x1, max_delta); + timer_of_period(to), + MIN_DELTA, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", node, bits);