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[209.132.180.67]) by mx.google.com with ESMTP id s59si4647273plb.276.2017.12.15.00.53.27; Fri, 15 Dec 2017 00:53:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H6dkACLg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753656AbdLOIxY (ORCPT + 20 others); Fri, 15 Dec 2017 03:53:24 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:46230 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754787AbdLOIxO (ORCPT ); Fri, 15 Dec 2017 03:53:14 -0500 Received: by mail-wm0-f68.google.com with SMTP id r78so16013132wme.5 for ; Fri, 15 Dec 2017 00:53:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x3KScFFwwOM34xGrbmU5fD1gHbJT73ffPl7KKkyHzWs=; b=H6dkACLgYbJazzoSnViwb+tVQbQJ2WldfNs+kbsJWYjqJkwx3FEvqKDb/w/QRzUHU7 Di/IqDg2+3EUoju65+bbBuEF3RnP27uyl8lB511gO4q3fshmeKh/KicxHl062Z0dSrNs rcw6A9tA1TMMg1HKWNpJffrWlwucdiIEg35qo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x3KScFFwwOM34xGrbmU5fD1gHbJT73ffPl7KKkyHzWs=; b=L5yXS4f0qR+QJmH/4fP55tnuQRGtDvTmgtrGyFpeezDUYU6R/NfzeeBbWEpDBJMMCa ta6Z4EAKpMi8FtguLdYsExxFNve9/gZQ0s/PtpcN7qz6zaRtiXOADpqwPqBy0HkzsKR/ F69rtj3BR3uSTjIkIuifNnTMj88RHaUAnn1MP04/tBVKmj8p59QXYX3EACGSWPhQCPjJ rYsyMp5jn3fRAh2Bb8673sKliIhQgzMFOanW/hw+DQWPovAqmCq+c22CMFx5zGD6uV9E 41sHu2SojntY+v0492BLtDL9gp+P20RbICV5DGop7iEYtTpFpEKTLsjutJfDVMVBjiZw yrgA== X-Gm-Message-State: AKGB3mKM++/TbaUplQL+zHPAkrbu/5iosP7o8Zai1o5+W6Qxr2Bewpjy zbnC7KSl4NlPjqua1R5j4ZnkDQ== X-Received: by 10.28.46.67 with SMTP id u64mr4418186wmu.64.1513327992872; Fri, 15 Dec 2017 00:53:12 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.40.214]) by smtp.gmail.com with ESMTPSA id r14sm3211803wra.71.2017.12.15.00.53.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Dec 2017 00:53:12 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH 3/4] clocksource: stm32: add clocksource support Date: Fri, 15 Dec 2017 09:52:46 +0100 Message-Id: <20171215085247.14946-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171215085247.14946-1-benjamin.gaignard@st.com> References: <20171215085247.14946-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The stm32 timer hardware is currently only used as a clock event device, but it can be used as a clocksource as well. Implement this by enabling the free running counter in the hardware block and converting the clock event part from a count down event timer to a comparator based timer. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 114 ++++++++++++++++++++++++++++---------- 1 file changed, 86 insertions(+), 28 deletions(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index de721d318065..38eb59bb7f8a 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "timer-of.h" @@ -24,17 +25,15 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) - -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) - +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) #define MAX_TIM_PSC 0xFFFF @@ -46,29 +45,44 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; + + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long val; + + val = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(val, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } @@ -80,6 +94,11 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; @@ -88,22 +107,46 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static void __init stm32_clockevent_init(struct timer_of *to) { unsigned long max_delta; - unsigned long prescaler; to->clkevt.name = "stm32_clockevent"; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; /* Detect whether the timer is 16 or 32 bits */ + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), 0x1, max_delta); +} + +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + unsigned long max_delta, prescaler; + int bits = 16; + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + + /* Detect whether the timer is 16 or 32 bits */ max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); + to->clkevt.rating = 50; - if (max_delta == ~0U) + if (max_delta == ~0U) { + bits = 32; to->clkevt.rating = 250; + } /* * Get the highest possible prescaler value to be as close @@ -113,18 +156,27 @@ static void __init stm32_clockevent_init(struct timer_of *to) if (prescaler > MAX_TIM_PSC) prescaler = MAX_TIM_PSC; - writel_relaxed(0, timer_of_base(to) + TIM_ARR); writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); - /* adjust rate and period given the prescaler value */ + /* Adjust rate and period given the prescaler value */ to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); - clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, max_delta); + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), + to->clkevt.rating, + bits, + clocksource_mmio_readl_up); } static int __init stm32_timer_init(struct device_node *node) @@ -150,10 +202,16 @@ static int __init stm32_timer_init(struct device_node *node) reset_control_deassert(rstc); } + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; + stm32_clockevent_init(to); return 0; +deinit: + timer_of_cleanup(to); err: kfree(to); return ret;