| Message ID | 20180125122736.5427-8-ard.biesheuvel@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Socionext SynQuacer updates | expand |
On Thu, Jan 25, 2018 at 12:27:35PM +0000, Ard Biesheuvel wrote: > The upstream version of the Linux NETSEC driver expects the PHY DT > node to appear under a MDIO subnode, so fix this in the device tree. > Fix the node name as well, this should be 'ethernet' not 'netsec', > and add a clock-names property describing the single clock reference > as 'phy_ref_clk'. > > Also, move the PHY subnode into the per-platform .dts file so we can > set the unit address in the node name. This is necessary because recent > versions of the DT compiler are more finicky about this. Presumably the only kernels this may break are using non-upstream code? If so: Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 7 +++++ > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 30 +++++++++----------- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 7 +++++ > 3 files changed, 28 insertions(+), 16 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts > index d2cd7ef90e6f..488c51a0f793 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts > @@ -44,3 +44,10 @@ > "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", > "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; > }; > + > +&mdio_netsec { > + phy_netsec: ethernet-phy@7 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <7>; > + }; > +}; > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 7c3518facb98..6ee7a0b7ccb4 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -457,25 +457,23 @@ > #clock-cells = <0>; > }; > > - eth0: netsec@522D0000 { > - compatible = "socionext,synquacer-netsec"; > - reg = <0 0x522d0000 0x0 0x10000>, > - <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; > - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk_netsec>; > - phy-mode = "rgmii"; > - max-speed = <1000>; > - max-frame-size = <9000>; > - phy-handle = <ðphy0>; > - dma-coherent; > + ethernet@522d0000 { > + compatible = "socionext,synquacer-netsec"; > + reg = <0 0x522d0000 0x0 0x10000>, > + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_netsec>; > + clock-names = "phy_ref_clk"; > + phy-mode = "rgmii"; > + max-speed = <1000>; > + max-frame-size = <9000>; > + phy-handle = <&phy_netsec>; > + dma-coherent; > > + mdio_netsec: mdio { > #address-cells = <1>; > #size-cells = <0>; > - > - ethphy0: ethernet-phy { > - compatible = "ethernet-phy-ieee802.3-c22"; > - reg = <FixedPcdGet32 (PcdNetsecPhyAddress)>; > - }; > + }; > }; > > smmu: iommu@582c0000 { > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts > index 132fd370a71b..97fddfedcb46 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts > @@ -34,3 +34,10 @@ > &sdhci { > status = "okay"; > }; > + > +&mdio_netsec { > + phy_netsec: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > +}; > -- > 2.11.0 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 25 January 2018 at 13:00, Leif Lindholm <leif.lindholm@linaro.org> wrote: > On Thu, Jan 25, 2018 at 12:27:35PM +0000, Ard Biesheuvel wrote: >> The upstream version of the Linux NETSEC driver expects the PHY DT >> node to appear under a MDIO subnode, so fix this in the device tree. >> Fix the node name as well, this should be 'ethernet' not 'netsec', >> and add a clock-names property describing the single clock reference >> as 'phy_ref_clk'. >> >> Also, move the PHY subnode into the per-platform .dts file so we can >> set the unit address in the node name. This is necessary because recent >> versions of the DT compiler are more finicky about this. > > Presumably the only kernels this may break are using non-upstream code? Yes. The upstream version is not quite upstream yet - it is now [finally] queued, for inclusion in v4.16 > If so: > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > Thanks >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> --- >> Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 7 +++++ >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 30 +++++++++----------- >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 7 +++++ >> 3 files changed, 28 insertions(+), 16 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts >> index d2cd7ef90e6f..488c51a0f793 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts >> @@ -44,3 +44,10 @@ >> "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", >> "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; >> }; >> + >> +&mdio_netsec { >> + phy_netsec: ethernet-phy@7 { >> + compatible = "ethernet-phy-ieee802.3-c22"; >> + reg = <7>; >> + }; >> +}; >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> index 7c3518facb98..6ee7a0b7ccb4 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> @@ -457,25 +457,23 @@ >> #clock-cells = <0>; >> }; >> >> - eth0: netsec@522D0000 { >> - compatible = "socionext,synquacer-netsec"; >> - reg = <0 0x522d0000 0x0 0x10000>, >> - <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; >> - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&clk_netsec>; >> - phy-mode = "rgmii"; >> - max-speed = <1000>; >> - max-frame-size = <9000>; >> - phy-handle = <ðphy0>; >> - dma-coherent; >> + ethernet@522d0000 { >> + compatible = "socionext,synquacer-netsec"; >> + reg = <0 0x522d0000 0x0 0x10000>, >> + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; >> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clk_netsec>; >> + clock-names = "phy_ref_clk"; >> + phy-mode = "rgmii"; >> + max-speed = <1000>; >> + max-frame-size = <9000>; >> + phy-handle = <&phy_netsec>; >> + dma-coherent; >> >> + mdio_netsec: mdio { >> #address-cells = <1>; >> #size-cells = <0>; >> - >> - ethphy0: ethernet-phy { >> - compatible = "ethernet-phy-ieee802.3-c22"; >> - reg = <FixedPcdGet32 (PcdNetsecPhyAddress)>; >> - }; >> + }; >> }; >> >> smmu: iommu@582c0000 { >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts >> index 132fd370a71b..97fddfedcb46 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts >> @@ -34,3 +34,10 @@ >> &sdhci { >> status = "okay"; >> }; >> + >> +&mdio_netsec { >> + phy_netsec: ethernet-phy@1 { >> + compatible = "ethernet-phy-ieee802.3-c22"; >> + reg = <1>; >> + }; >> +}; >> -- >> 2.11.0 >> _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index d2cd7ef90e6f..488c51a0f793 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -44,3 +44,10 @@ "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; }; + +&mdio_netsec { + phy_netsec: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 7c3518facb98..6ee7a0b7ccb4 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -457,25 +457,23 @@ #clock-cells = <0>; }; - eth0: netsec@522D0000 { - compatible = "socionext,synquacer-netsec"; - reg = <0 0x522d0000 0x0 0x10000>, - <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_netsec>; - phy-mode = "rgmii"; - max-speed = <1000>; - max-frame-size = <9000>; - phy-handle = <ðphy0>; - dma-coherent; + ethernet@522d0000 { + compatible = "socionext,synquacer-netsec"; + reg = <0 0x522d0000 0x0 0x10000>, + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_netsec>; + clock-names = "phy_ref_clk"; + phy-mode = "rgmii"; + max-speed = <1000>; + max-frame-size = <9000>; + phy-handle = <&phy_netsec>; + dma-coherent; + mdio_netsec: mdio { #address-cells = <1>; #size-cells = <0>; - - ethphy0: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <FixedPcdGet32 (PcdNetsecPhyAddress)>; - }; + }; }; smmu: iommu@582c0000 { diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index 132fd370a71b..97fddfedcb46 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -34,3 +34,10 @@ &sdhci { status = "okay"; }; + +&mdio_netsec { + phy_netsec: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +};
The upstream version of the Linux NETSEC driver expects the PHY DT node to appear under a MDIO subnode, so fix this in the device tree. Fix the node name as well, this should be 'ethernet' not 'netsec', and add a clock-names property describing the single clock reference as 'phy_ref_clk'. Also, move the PHY subnode into the per-platform .dts file so we can set the unit address in the node name. This is necessary because recent versions of the DT compiler are more finicky about this. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 7 +++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 30 +++++++++----------- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 7 +++++ 3 files changed, 28 insertions(+), 16 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel