From patchwork Mon Feb 5 13:20:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126868 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967489ljc; Mon, 5 Feb 2018 05:22:51 -0800 (PST) X-Google-Smtp-Source: AH8x224oPKk/KdCNCjiLBryYylKlfzNjM1q9z5zExbwIa+5BSjkN60wGpQSLUzfL/l+7mg2XPArP X-Received: by 10.36.1.70 with SMTP id 67mr13142191itk.104.1517836971856; Mon, 05 Feb 2018 05:22:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517836971; cv=none; d=google.com; s=arc-20160816; b=mbQPVSrw3a79HKUCnXb/41UR6IdEVHrVJVxuHrqhGOnk/yjCJ1kvQEzn24GDUqbKAX xQkBGvUuUZMeUcrIW8QuDR6wjGvqEg8LvyPH2gMWSKjgebmwiBnAioVq+9rdoRB5ZR37 a5xbbHHA5baH0PHvIdvgnCxwBwVKmphWogfRaoWvC4uFdN8x8l57DQRxhIawE0IIiHep chxckdcF4lxJY3cXobFd248lPCwBfKGg3j2QN9mPcqBfItsNHMWeyVRZva+75c3W0Kc+ LmpbFs8rHU4K4RHU1RX1NTusLBc0dyollchCfDVH6GCG5+CtQuO3o2l3oT9e+fBKLof/ 87OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=8KFJi6uNJ+vd+eVFfi0NRwVWHKJrKspH9jwVe9x9HAo=; b=c+PomtHMXJmMFFn+j67JinzKCjsFf6++wG8JdkMhnrBuo4NTKu8AXx5D2AN9s173nE g7GB5EsETEASX9feecY6JIcDtGq6RUKD0Bg9rWMfasQtwlTzR36ue+kKkioHWLMX9V3p iCGc0ZoMCeQ9/+zaBi7d/6/sqLDy5I93zUIkz6hYFpQhDN4kB0e1Gyo79RWgGJ/GdZlA A2aiuxz2JLfUpMU76PVxLX1Hi9O7inFDbvfTs6rdlTIltYbnzyrVPWgRm4ngah2kpdzo ovdsuyBhUvqAIDp9k7m1ou28FjpI/70o0KWzHqbGHQZCGkWV0qDQf9w5cVCYOjwgvfkr 3YZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g64si6176263ite.75.2018.02.05.05.22.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighH-0007Ry-VA; Mon, 05 Feb 2018 13:20:35 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighG-0007ME-A7 for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:34 +0000 X-Inumbo-ID: 6fa56d69-0a77-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 6fa56d69-0a77-11e8-b9b1-635ca7ef6cff; Mon, 05 Feb 2018 13:21:12 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2F7CA1596; Mon, 5 Feb 2018 05:20:27 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 441DB3F24D; Mon, 5 Feb 2018 05:20:26 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:09 +0000 Message-Id: <20180205132011.27996-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 7/7] xen/arm64: Implement a fast path for handling SMCCC_ARCH_WORKAROUND_1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for hardening the branch predictor. So we want the handling to be as fast as possible. As the mitigation is applied on every guest exit, we can check for the call before saving all the context and return very early. For now, only provide a fast path for HVC64 call. Because the code rely on 2 registers, x0 and x1 are saved in advanced. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- guest_sync only handle 64-bit guest, so I have only implemented the 64-bit side for now. We can discuss whether it is useful to implement it for 32-bit guests. We could also consider to implement the fast path for SMC64, althought a guest should always use HVC. --- xen/arch/arm/arm64/entry.S | 56 +++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/processor.h | 2 ++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 6d99e46f0f..67f96d518f 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -1,6 +1,7 @@ #include #include #include +#include #include /* @@ -90,8 +91,12 @@ lr .req x30 /* link register */ .endm /* * Save state on entry to hypervisor, restore on exit + * + * save_x0_x1: Does the macro needs to save x0/x1 (default 1). If 0, + * we rely on the on x0/x1 to have been saved at the correct position on + * the stack before. */ - .macro entry, hyp, compat + .macro entry, hyp, compat, save_x0_x1=1 sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ push x28, x29 push x26, x27 @@ -107,7 +112,16 @@ lr .req x30 /* link register */ push x6, x7 push x4, x5 push x2, x3 + /* + * The caller may already have saved x0/x1 on the stack at the + * correct address and corrupt them with another value. Only + * save them if save_x0_x1 == 1. + */ + .if \save_x0_x1 == 1 push x0, x1 + .else + sub sp, sp, #16 + .endif .if \hyp == 1 /* Hypervisor mode */ @@ -200,7 +214,45 @@ hyp_irq: exit hyp=1 guest_sync: - entry hyp=0, compat=0 + /* + * Save x0, x1 in advance + */ + stp x0, x1, [sp, #-(UREGS_kernel_sizeof - UREGS_X0)] + + /* + * x1 is used because x0 may contain the function identifier. + * This avoids to restore x0 from the stack. + */ + mrs x1, esr_el2 + lsr x1, x1, #HSR_EC_SHIFT /* x1 = ESR_EL2.EC */ + cmp x1, #HSR_EC_HVC64 + b.ne 1f /* Not a HVC skip fastpath. */ + + mrs x1, esr_el2 + and x1, x1, #0xffff /* Check the immediate [0:16] */ + cbnz x1, 1f /* should be 0 for HVC #0 */ + + /* + * Fastest path possible for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the exception + * entry from the guest, so let's quickly get back to the guest. + */ + eor w0, w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + cbnz w0, 1f + + /* + * Clobber both x0 and x1 to prevent leakage. Note that thanks + * the eor, x0 = 0. + */ + mov x1, x0 + eret + +1: + /* + * x0/x1 may have been scratch by the fast path above, so avoid + * to save them. + */ + entry hyp=0, compat=0, save_x0_x1=0 /* * The vSError will be checked while SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT * is not set. If a vSError took place, the initial exception will be diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0f79d0093..222a02dd99 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -306,6 +306,8 @@ #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ +#define HSR_EC_SHIFT 26 + #define HSR_EC_UNKNOWN 0x00 #define HSR_EC_WFI_WFE 0x01 #define HSR_EC_CP15_32 0x03