@@ -360,6 +360,13 @@ virtphys_clash:
1:
PRINT("- Turning on paging -\r\n")
+ /*
+ * The state of the TLBs is unknown before turning on the MMU.
+ * Flush them to avoid stale one.
+ */
+ mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLBs */
+ dsb nsh
+
ldr r1, =paging /* Explicit vaddr, not RIP-relative */
mrc CP32(r0, HSCTLR)
orr r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */
@@ -498,6 +498,13 @@ virtphys_clash:
1:
PRINT("- Turning on paging -\r\n")
+ /*
+ * The state of the TLBs is unknown before turning on the MMU.
+ * Flush them to avoid stale one.
+ */
+ tlbi alle2 /* Flush hypervisor TLBs */
+ dsb nsh
+
ldr x1, =paging /* Explicit vaddr, not RIP-relative */
mrs x0, SCTLR_EL2
orr x0, x0, #SCTLR_M /* Enable MMU */
We don't know what is the state of the TLBs when booting Xen. To avoid stale entries, it is necessary to flush the TLBs before turning on the MMU. Reported-by: Iain Hunter <iain@hunterembedded.co.uk> Signed-off-by: Julien Grall <julien.gralL@arm.com> --- xen/arch/arm/arm32/head.S | 7 +++++++ xen/arch/arm/arm64/head.S | 7 +++++++ 2 files changed, 14 insertions(+)