From patchwork Thu Mar 1 13:58:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 130229 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2828512edc; Thu, 1 Mar 2018 05:58:51 -0800 (PST) X-Google-Smtp-Source: AG47ELsRnsBO9yMMYcPFWiXBxVkrm05nhIUE42JuFhZQ2z/diWsTBdlwSDIwE3hjVZnenl17iWYd X-Received: by 10.99.117.10 with SMTP id q10mr1605715pgc.423.1519912730847; Thu, 01 Mar 2018 05:58:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519912730; cv=none; d=google.com; s=arc-20160816; b=bqqlzBbjCZnQ5hnMxGUUFWQGDdDAdulaJA/3n5WMzg5hFG+5hToQdhoH+sxWWo8GO0 +/P7nkxSOl2oVr4c8MYRZuvcTWqSnu7ikpSqKBPT/zNiz7HqmbVBTVp+VotPNdIfEdWS po9t1jsgzucq4TFNOSyE/DXCLRIKRvFoFhcIQlRdFMvFAfZOTO7OqKDEAv+DK1Q4+T+E R8D4latFeVM1XjU5IIaSlSbfj/xE21QiBVNsHvulE1jjf4H5CTd6NilHWapPV5CM3qb1 qsHs/vcIVvFkqdzszGgRJidw/CTzQqCJsC+lZAq6rPlkqonGnAEDiffsjoWUEPVKw8uz m6Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=TJsBp47ihLuevHNM+JR5gQ3nrfOCnkx2UaaHNCzVIvk=; b=p3kHQI/cXjv+RjPC8G1c5vPxSeRqsXYVgLGAUU67tcV9NjRLPY6Zp1HHn9nSDyQuvE Cdu9Fnk2+K4rnorNYrgi/ioDd8taZLAG6cHumsg8ECCr56vxdEglvZs/fDDBG6Os2VnV 6Kn+AfCx6NVw+wx8VHjAcZ1fHqG4oje+8Gn1OMEkb4/qm+kMqwij/MTi5U7IlqW9FXvE ece5hQZf23TkvGTG3F08fs/AjRup1mdSwtw7M8Go6Cf3M6LcWkBbdn34GgmqO6okbWHE HFacLSzgUroML2jPTY3wnGSZeHlU+6TSB4NZuFaHjtnRi615FgklLU5UDTcGnIY1TsNu MGhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T0Olvte7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p18-v6si3090899plo.388.2018.03.01.05.58.50; Thu, 01 Mar 2018 05:58:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T0Olvte7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031055AbeCAN6q (ORCPT + 28 others); Thu, 1 Mar 2018 08:58:46 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36397 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031004AbeCAN61 (ORCPT ); Thu, 1 Mar 2018 08:58:27 -0500 Received: by mail-wm0-f65.google.com with SMTP id 188so11904313wme.1 for ; Thu, 01 Mar 2018 05:58:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TJsBp47ihLuevHNM+JR5gQ3nrfOCnkx2UaaHNCzVIvk=; b=T0Olvte7VSHZIdxm/rFHZDVV0n4NFkF88QVhZkrLnWroz9tqsy+J9vVVlOVg1If8WQ RvFyYoxxBQ+bvCbEil6Xse1M2vc2J8qWQvs9DyLo6h4Nz3yA0o40KXirPnl0loOYJVtP uaLT7yh0yukk3HAKGO+8shA7DxAMO7P1cgiLA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TJsBp47ihLuevHNM+JR5gQ3nrfOCnkx2UaaHNCzVIvk=; b=ZpL9hdTTiBImHdBxseT21IF91UaphoEoHAT8qNfvCL1islw32rGeztuojVXVYhGKjA H3DtlwC7PGHFtHrQmD/Tk6uAeSIXHBqQlO0jMa2YKUCMI2odjpnGNCKKb9dGaYkonY0c ywxrl8AyuSGTqtHZMh5jyLwq8I6xa+XeglYQZSYo6P+NZi5zMxV81JvzpmEy5rD5IxPZ nElI8/glWncTHLs/rHptnI44LtjTIT3fUG3GjbkdhQ0+DuW/D/M2hdkvi93jCnyRcRkl Y2NoeWxW8ZkeOq7fHFnW3HVEV1WeOPFRvE0pF5v/gL70mRxtEYj7a7PFQlGjkeULyfRl 1h9g== X-Gm-Message-State: AElRT7GBsSnNRSNNtIFWPS9WmcsMMJU2LBSsgQjX8U9v/rx4f4mBfhnO FtouEhepOHFFNm/l1QGck6Sa6A== X-Received: by 10.28.23.143 with SMTP id 137mr1963593wmx.153.1519912706361; Thu, 01 Mar 2018 05:58:26 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.14.109]) by smtp.gmail.com with ESMTPSA id e6sm3826304wra.67.2018.03.01.05.58.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Mar 2018 05:58:25 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, robin.murphy@arm.com, arnd@arndb.de, loic.pallardy@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v2 2/2] ARM: mach-stm32: Add Extended TrustZone Protection driver Date: Thu, 1 Mar 2018 14:58:06 +0100 Message-Id: <20180301135806.19982-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180301135806.19982-1-benjamin.gaignard@st.com> References: <20180301135806.19982-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Extended TrustZone Protection (ETZPC) driver checks that the hardware block is accessible to non-secure world. If not it will disable the device tree node by updated it status property. Split between secure and non-secure hardware blocks is done at early boot stage so the driver only needs to read the status (2 bits) for each of the block. Hardware blocks status bits location in the registers is computed from the index of the device phandle in the list. To avoid to bind a device which will not be accessible ETZPC driver must be probed early, at least before platform driver, so just after core initialisation. Signed-off-by: Benjamin Gaignard --- arch/arm/mach-stm32/Kconfig | 7 +++ arch/arm/mach-stm32/Makefile | 1 + arch/arm/mach-stm32/stm32-etzpc.c | 116 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 arch/arm/mach-stm32/stm32-etzpc.c -- 2.15.0 diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 5bc7f5ab61cd..a3ef308642be 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -44,6 +44,13 @@ config MACH_STM32MP157 bool "STMicroelectronics STM32MP157" default y +config STM32_ETZPC + bool "STM32 Extended TrustZone Protection" + depends on MACH_STM32MP157 + help + Select y to enable STM32 Extended TrustZone Protection + Controller (ETZPC) + endif # ARMv7-A endif diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile index bd0b7b5d6e9d..2e1e729a68c9 100644 --- a/arch/arm/mach-stm32/Makefile +++ b/arch/arm/mach-stm32/Makefile @@ -1 +1,2 @@ obj-y += board-dt.o +obj-$(CONFIG_STM32_ETZPC) += stm32-etzpc.o diff --git a/arch/arm/mach-stm32/stm32-etzpc.c b/arch/arm/mach-stm32/stm32-etzpc.c new file mode 100644 index 000000000000..ea966b7d519a --- /dev/null +++ b/arch/arm/mach-stm32/stm32-etzpc.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Benjamin Gaignard for STMicroelectronics. + */ +#include +#include +#include +#include +#include + +#define ETZPC_DECPROT0 0x10 +#define ETZPC_IP_VER 0x3F4 + +#define IP_VER_MP1 0x00000020 + +#define DECPROT_MASK 0x03 +#define NB_PROT_PER_REG 0x10 +#define DECPROT_NB_BITS 2 + +static void __init stm32_etzpc_update_status(struct device_node *np) +{ + struct property *prop; + + prop = kzalloc(sizeof(*prop), GFP_KERNEL); + if (!prop) + return; + + prop->name = "status"; + prop->value = "disabled"; + prop->length = strlen((char *)prop->value)+1; + + of_update_property(np, prop); + + pr_err("%s status doesn't match ETZPC status\n", of_node_full_name(np)); +} + +static bool __init stm32_etzpc_is_secured(void __iomem *base, int index) +{ + u32 status; + int offset = (index / NB_PROT_PER_REG) * sizeof(u32); + int shift = (index % NB_PROT_PER_REG) * DECPROT_NB_BITS; + + status = readl(base + ETZPC_DECPROT0 + offset); + status &= DECPROT_MASK << shift; + + return (status != DECPROT_MASK << shift); +} + +static const struct of_device_id stm32_etzpc_of_match[] = { + { + .compatible = "st,stm32mp1-etzpc", + }, + { /* end node */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_etzpc_of_match); + +static int __init stm32_etzpc_probe(struct device_node *np, + const struct of_device_id *match) +{ + struct of_phandle_iterator it; + void __iomem *base; + int version, index = 0, ret = 0; + + base = of_iomap(np, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + version = readl(base + ETZPC_IP_VER); + if (version != IP_VER_MP1) { + pr_err("Wrong ETZPC version\n"); + ret = -EINVAL; + goto failed; + } + + of_for_each_phandle(&it, ret, np, "protected-devices", NULL, 0) { + if (of_device_is_available(it.node) && + stm32_etzpc_is_secured(base, index)) + stm32_etzpc_update_status(it.node); + + index++; + } + +failed: + iounmap(base); + return ret; +} + +/* + * stm32_etzpc_init need to be called before starting to probe + * platform drivers to be able check the status of each protected devices + * that's why it is tagged as postcore_initcall + */ +static int __init stm32_etzpc_init(void) +{ + struct device_node *np; + const struct of_device_id *m; + int ret; + + np = of_find_matching_node_and_match(NULL, stm32_etzpc_of_match, &m); + + if (!np) + return -ENODEV; + + if (!of_device_is_available(np)) { + of_node_put(np); + return -ENODEV; + } + + ret = stm32_etzpc_probe(np, m); + + of_node_put(np); + + return ret; +} +postcore_initcall(stm32_etzpc_init);