| Message ID | 1520837611-94728-2-git-send-email-heyi.guo@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ArmPkg/TimerDxe: Add DSB for timer compare value reload | expand |
On 12/03/18 06:53, Heyi Guo wrote: > Resetting timer compare register has a side effect of clearing GIC > pending status, if timer interrupt is level sensitive, so a "DSB SY" > is needed to make sure this change effect is synchronized. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > Signed-off-by: Yi Li <phoenix.liyi@huawei.com> > Cc: Leif Lindholm <leif.lindholm@linaro.org> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Marc Zyngier <marc.zyngier@arm.com> > --- > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > index 33d7c922221f..b732a2ac1b64 100644 > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > // Set next compare value > ArmGenericTimerSetCompareVal (CompareValue); > + ArmDataSynchronizationBarrier (); > ArmGenericTimerEnableTimer (); > } > > Which HW platform is that on? DSB on its own doesn't have any effect on inputs to the GIC, only on the synchronization at the GIC system register level (see the GICv3 architecture specification, 8.1.6). I don't believe this is required. You could stick an ISB instead to ensure that the write to the CNTVCTL_EL0 is executed, but DSB feels pretty odd, unless this is a workaround for a platform erratum. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Thanks, I can try if ISB works. The issue was observed on Hisilicon D05 platform. Regards, Heyi On Mon, Mar 12, 2018 at 09:46:41AM +0000, Marc Zyngier wrote: > On 12/03/18 06:53, Heyi Guo wrote: > > Resetting timer compare register has a side effect of clearing GIC > > pending status, if timer interrupt is level sensitive, so a "DSB SY" > > is needed to make sure this change effect is synchronized. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > > Signed-off-by: Yi Li <phoenix.liyi@huawei.com> > > Cc: Leif Lindholm <leif.lindholm@linaro.org> > > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > Cc: Marc Zyngier <marc.zyngier@arm.com> > > --- > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > index 33d7c922221f..b732a2ac1b64 100644 > > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > > > // Set next compare value > > ArmGenericTimerSetCompareVal (CompareValue); > > + ArmDataSynchronizationBarrier (); > > ArmGenericTimerEnableTimer (); > > } > > > > > > Which HW platform is that on? > > DSB on its own doesn't have any effect on inputs to the GIC, only on the > synchronization at the GIC system register level (see the GICv3 > architecture specification, 8.1.6). > > I don't believe this is required. You could stick an ISB instead to > ensure that the write to the CNTVCTL_EL0 is executed, but DSB feels > pretty odd, unless this is a workaround for a platform erratum. > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Hi Marc, I just tested with an ISB and it also worked for our platform. So is it acceptable to add an ISB after reloading timer compare value? Regards, Heyi On Mon, Mar 12, 2018 at 06:26:43PM +0800, Guo Heyi wrote: > Thanks, I can try if ISB works. The issue was observed on Hisilicon D05 platform. > > Regards, > > Heyi > > On Mon, Mar 12, 2018 at 09:46:41AM +0000, Marc Zyngier wrote: > > On 12/03/18 06:53, Heyi Guo wrote: > > > Resetting timer compare register has a side effect of clearing GIC > > > pending status, if timer interrupt is level sensitive, so a "DSB SY" > > > is needed to make sure this change effect is synchronized. > > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > > > Signed-off-by: Yi Li <phoenix.liyi@huawei.com> > > > Cc: Leif Lindholm <leif.lindholm@linaro.org> > > > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > > Cc: Marc Zyngier <marc.zyngier@arm.com> > > > --- > > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > index 33d7c922221f..b732a2ac1b64 100644 > > > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > > > > > // Set next compare value > > > ArmGenericTimerSetCompareVal (CompareValue); > > > + ArmDataSynchronizationBarrier (); > > > ArmGenericTimerEnableTimer (); > > > } > > > > > > > > > > Which HW platform is that on? > > > > DSB on its own doesn't have any effect on inputs to the GIC, only on the > > synchronization at the GIC system register level (see the GICv3 > > architecture specification, 8.1.6). > > > > I don't believe this is required. You could stick an ISB instead to > > ensure that the write to the CNTVCTL_EL0 is executed, but DSB feels > > pretty odd, unless this is a workaround for a platform erratum. > > > > Thanks, > > > > M. > > -- > > Jazz is not dead. It just smells funny... _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 12 March 2018 at 10:38, Guo Heyi <heyi.guo@linaro.org> wrote: > Hi Marc, > > I just tested with an ISB and it also worked for our platform. > > So is it acceptable to add an ISB after reloading timer compare value? > I am fine with that if Marc is. -- Ard. _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 12/03/18 10:38, Ard Biesheuvel wrote: > On 12 March 2018 at 10:38, Guo Heyi <heyi.guo@linaro.org> wrote: >> Hi Marc, >> >> I just tested with an ISB and it also worked for our platform. >> >> So is it acceptable to add an ISB after reloading timer compare value? >> > > I am fine with that if Marc is. An ISB makes a lot more sense to me. You can put my ack on a modified version of that patch. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On Mon, Mar 12, 2018 at 10:48:59AM +0000, Marc Zyngier wrote: > On 12/03/18 10:38, Ard Biesheuvel wrote: > > On 12 March 2018 at 10:38, Guo Heyi <heyi.guo@linaro.org> wrote: > >> Hi Marc, > >> > >> I just tested with an ISB and it also worked for our platform. > >> > >> So is it acceptable to add an ISB after reloading timer compare value? > >> > > > > I am fine with that if Marc is. > > An ISB makes a lot more sense to me. You can put my ack on a modified > version of that patch. Hi Marc, I've sent v2 patch using ISB. Please help to check the updated commit message to see if my understanding is correct. Thanks, Heyi > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c index 33d7c922221f..b732a2ac1b64 100644 --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -337,6 +337,7 @@ TimerInterruptHandler ( // Set next compare value ArmGenericTimerSetCompareVal (CompareValue); + ArmDataSynchronizationBarrier (); ArmGenericTimerEnableTimer (); }