| Message ID | 20180412111138.40990-16-mark.rutland@arm.com |
|---|---|
| State | New |
| Headers | show
Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1571749ljb; Thu, 12 Apr 2018 04:12:44 -0700 (PDT) X-Google-Smtp-Source: AIpwx49qenzd103sIPjvBgz0v1zr7ZGOhsVamChIhjGfFmy7Q3Z0savcTnWvdYuFofNe//Hqz9AX X-Received: by 2002:a17:902:bd8e:: with SMTP id q14-v6mr535261pls.322.1523531564199; Thu, 12 Apr 2018 04:12:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523531564; cv=none; d=google.com; s=arc-20160816; b=IznVe5TFp+WCBe0RXY4Gg5Hdty7N7RnCMB1rjrfMt75q77UsRIpIFjKpDL3rOoAXsc +6AXAGGC/FDFWy8lFpfEkUg+rKktY4g1+iLXSDl0pL5YcwONDLxR9Hhh6/fIgDOf1s8e m1SdIksuf98K19+vI7tKiHq2klXarw/f1lTNy+IcRUGNzMjl6L852ODpyGXEW2h8QqKe peeAYsFhwt7yFt1j1w+wby049kAw2USrSMsCIEv1/WVbm//Mq2B4BtJObmE1rYbmrNhD V1V0KtOF/rlj7k2txzxsFg4rv6K8vdamfRo5M/KgKg6ApzvlMCOHjgaeDn2tcKDqn/2w lDXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=9wKA446/AlC9DNGfegQN0lnxYiw+aJ4TNGfsK2Wf+yc=; b=ewX9gbn2dEufBiVgZ9w0ykB6e56NlLMehmQeceB9Nkb1ZkkwoDTMS8LWaNVddKpjQn 5KtH5y7J/dqbc5bIx0ATG6eftDDw20RnIKVh5GXfHISi/x9GePsEVRGK+WdavlSQtTXd AbFCOkXJ0gmDN+VBIC5uFP4tUasP/0CF365GLwzoE6R8Ee+8XkFuRKyoN5JMlEt8Fnc4 N1Q2wWtQdFXh+7oOjZRirGpwHlpGzwCyGV+hzsnBeg/NO7KfoVoNwBdX1Ab/XGlw71qb 3WA2NX2xVPnrdpWH8kdWg5440KElOaIU3yWUqIiTTZoV+DocpF75UJTpl9MQETavI589 Jv0Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: <stable-owner@vger.kernel.org> Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bg3-v6si3001807plb.118.2018.04.12.04.12.43; Thu, 12 Apr 2018 04:12:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752894AbeDLLMn (ORCPT <rfc822;semen.protsenko@linaro.org> + 11 others); Thu, 12 Apr 2018 07:12:43 -0400 Received: from foss.arm.com ([217.140.101.70]:59434 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752882AbeDLLMn (ORCPT <rfc822;stable@vger.kernel.org>); Thu, 12 Apr 2018 07:12:43 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C71B380D; Thu, 12 Apr 2018 04:12:42 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 251C03F24A; Thu, 12 Apr 2018 04:12:41 -0700 (PDT) From: Mark Rutland <mark.rutland@arm.com> To: stable@vger.kernel.org Cc: mark.brown@linaro.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, will.deacon@arm.com, catalin.marinas@arm.com, ghackmann@google.com, shankerd@codeaurora.org Subject: [PATCH v4.9.y 15/42] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Date: Thu, 12 Apr 2018 12:11:11 +0100 Message-Id: <20180412111138.40990-16-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180412111138.40990-1-mark.rutland@arm.com> References: <20180412111138.40990-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: <stable.vger.kernel.org> X-Mailing-List: stable@vger.kernel.org |
| Series |
arm64 spectre patches
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expand
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diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 540c24f74837..c9bd4ad4db82 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -434,4 +434,18 @@ alternative_endif .macro pte_to_phys, phys, pte and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) .endm + +/* + * Errata workaround post TTBR0_EL1 update. + */ + .macro post_ttbr0_update_workaround +#ifdef CONFIG_CAVIUM_ERRATUM_27456 +alternative_if ARM64_WORKAROUND_CAVIUM_27456 + ic iallu + dsb nsh + isb +alternative_else_nop_endif +#endif + .endm + #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c07d9cc057e6..135a698ce946 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,11 +139,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb -alternative_if ARM64_WORKAROUND_CAVIUM_27456 - ic iallu - dsb nsh - isb -alternative_else_nop_endif + post_ttbr0_update_workaround ret ENDPROC(cpu_do_switch_mm)