From patchwork Fri May 4 17:39:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 135014 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp323481lji; Fri, 4 May 2018 10:40:08 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrQk0RjE3336e/tXFwwZJGhAI+pN83s76zVDOsPxPMxgpHr+qeXq19u0IiJXxdlZpBHXNgh X-Received: by 10.98.11.3 with SMTP id t3mr27869862pfi.32.1525455607915; Fri, 04 May 2018 10:40:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525455607; cv=none; d=google.com; s=arc-20160816; b=s4ioX6pD39Sbu2SJ9kYW4twrYzwt8GnpEEgBEptxjWerAs6EAncMVHwC6CVwlPcsNF IP0JKQzwYERc4W+D75yNm0+2C7uYQXydjMDMhgyRYsSMgrSmjzFEhi/yUdWVL/y1qo8l 6uukBI8NMkfvZSW/MjAxsYKah2Suys5WSRfaSL9Bs1iUMzo0GdVef2ECWZ7bWzlw2qwj zgeyWwVhyw8aIuyXm8IwlfaQlFaH3MlJiNmTPCdufcVRw5eMUfJvK3K7+gVYMEl9fOsK FP9ugnMymA2l7CudAUjKwLppkg4Ziir93joAcCMKRQLRsTvotv+7KH1KG2mzIuPDVXE4 CF9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=vtCCki6tA0bRQFNaK1Hh8IoMrMdnWV/whfFTcJfgNaU=; b=rwXW4g67YzEq4i6UEg5BB2LLEKSP30soyhjdXbVQPmvMCwSZOBRwgzZE/3tQSdZR5g nIq3xvEPrUZP84FyvS8CfMzHlSm+HgRsjyZcpLURvlwx3SjkGbriKiEmbwIiDXwIRwHX /QcoyGzrQkNTsN+7ZRbOHHLcMR1e22pdDEUHmirXhDgYfNjZsmlV44KXs/Qa9rHVHA6v JEZezi25lj/0n6NU1KPxJ0SZvr23LtceRWxVNWsRTsF2j4m81JI0kL1kxXoZ8ExBnelH k+Qvmy0xx8dhvK6c89a0QY0Muf1q6wf6Sb32j6EtoCIKyUlAk7SsZEzEl/HCDsj/2EZ2 zLSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k2-v6si10988592plt.374.2018.05.04.10.40.07; Fri, 04 May 2018 10:40:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752033AbeEDRkF (ORCPT + 29 others); Fri, 4 May 2018 13:40:05 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:57404 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751484AbeEDRkB (ORCPT ); Fri, 4 May 2018 13:40:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 673E4168F; Fri, 4 May 2018 10:40:01 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9D7613F487; Fri, 4 May 2018 10:39:59 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, aryabinin@virtuozzo.com, boqun.feng@gmail.com, catalin.marinas@arm.com, dvyukov@google.com, mark.rutland@arm.com, mingo@kernel.org, peterz@infradead.org, will.deacon@arm.com Subject: [PATCH 4/6] arm64: fix assembly constraints for cmpxchg Date: Fri, 4 May 2018 18:39:35 +0100 Message-Id: <20180504173937.25300-5-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180504173937.25300-1-mark.rutland@arm.com> References: <20180504173937.25300-1-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Our LL/SC cmpxchg assembly uses "Lr" as the constraint for old, which allows either an integer constant suitable for a 64-bit logical oepration, or a register. However, this assembly is also used for 32-bit cases (where we explicitly add a 'w' prefix to the output format), where the set of valid immediates differ, and we should use a 'Kr' constraint. In some cases, this can result in build failures, when GCC selects an immediate which is valid for a 64-bit logical operation, but we try to assemble a 32-bit logical operation: [mark@lakrids:~/src/linux]% uselinaro 17.05 make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- net/sunrpc/auth_gss/svcauth_gss.o CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK include/generated/bounds.h CHK include/generated/timeconst.h CHK include/generated/asm-offsets.h CALL scripts/checksyscalls.sh CHK scripts/mod/devicetable-offsets.h CC net/sunrpc/auth_gss/svcauth_gss.o /tmp/ccj04KVh.s: Assembler messages: /tmp/ccj04KVh.s:325: Error: immediate out of range at operand 3 -- `eor w2,w1,4294967295' scripts/Makefile.build:324: recipe for target 'net/sunrpc/auth_gss/svcauth_gss.o' failed make[1]: *** [net/sunrpc/auth_gss/svcauth_gss.o] Error 1 Makefile:1704: recipe for target 'net/sunrpc/auth_gss/svcauth_gss.o' failed make: *** [net/sunrpc/auth_gss/svcauth_gss.o] Error 2 Note that today we largely avoid the specific failure above because GCC happens to already have the value in a register, and in most cases uses that rather than generating the immediate. The following code added to an arbitrary file will cause the same failure: unsigned int test_cmpxchg(unsigned int *l) { return cmpxchg(l, -1, 0); } While it would seem that we could conditionally use the 'K' constraint, this seems to be handled erroneously by GCC (at least versions 6.3 and 7.1), with the same immediates being used, despite not being permitted for 32-bit logical operations. Thus we must avoid the use of an immediate in order to prevent failures as above. Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/atomic_ll_sc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.11.0 diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h index f5a2d09afb38..3175f4982682 100644 --- a/arch/arm64/include/asm/atomic_ll_sc.h +++ b/arch/arm64/include/asm/atomic_ll_sc.h @@ -267,7 +267,7 @@ __LL_SC_PREFIX(__cmpxchg_case_##name(volatile void *ptr, \ "2:" \ : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \ [v] "+Q" (*(unsigned long *)ptr) \ - : [old] "Lr" (old), [new] "r" (new) \ + : [old] "r" (old), [new] "r" (new) \ : cl); \ \ return oldval; \