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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id p76-v6sm6913861lfp.44.2018.05.28.10.51.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 May 2018 10:51:33 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli Cc: netdev@vger.kernel.org, openwrt-devel@lists.openwrt.org, LEDE Development List , Linus Walleij , =?utf-8?b?QW50dGkgU2VwcMOkbMOk?= , Roman Yeryomin , Colin Leitner , Gabor Juhos Subject: [PATCH 1/4 RFCv2] net: phy: realtek: Support RTL8366RB variant Date: Mon, 28 May 2018 19:47:49 +0200 Message-Id: <20180528174752.6806-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180528174752.6806-1-linus.walleij@linaro.org> References: <20180528174752.6806-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The RTL8366RB is an ASIC with five internal PHYs for LAN0..LAN3 and WAN. The PHYs are spawn off the main device so they can be handled in a distributed manner by the Realtek PHY driver. All that is really needed is the power save feature enablement and letting the PHY driver core pick up the IRQ from the switch chip. Cc: Antti Seppälä Cc: Roman Yeryomin Cc: Colin Leitner Cc: Gabor Juhos Cc: Florian Fainelli Signed-off-by: Linus Walleij --- ChangeLog RFCv1->RFCv2: - No real changes. --- drivers/net/phy/realtek.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.17.0 diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 9f48ecf9c627..21624d1c9d38 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -37,6 +37,9 @@ #define RTL8201F_ISR 0x1e #define RTL8201F_IER 0x13 +#define RTL8366RB_POWER_SAVE 0x21 +#define RTL8366RB_POWER_SAVE_ON 0x1000 + MODULE_DESCRIPTION("Realtek PHY driver"); MODULE_AUTHOR("Johnson Leung"); MODULE_LICENSE("GPL"); @@ -145,6 +148,22 @@ static int rtl8211f_config_init(struct phy_device *phydev) return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val); } +static int rtl8366rb_config_init(struct phy_device *phydev) +{ + int ret; + u16 reg; + + ret = genphy_config_init(phydev); + if (ret < 0) + return ret; + + reg = phy_read(phydev, RTL8366RB_POWER_SAVE); + reg |= RTL8366RB_POWER_SAVE_ON; + phy_write(phydev, RTL8366RB_POWER_SAVE, reg); + + return 0; +} + static struct phy_driver realtek_drvs[] = { { .phy_id = 0x00008201, @@ -207,6 +226,18 @@ static struct phy_driver realtek_drvs[] = { .resume = genphy_resume, .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, + }, { + /* The main part of this DSA is in drivers/net/dsa */ + .phy_id = 0x001cc961, + .name = "RTL8366RB Gigabit Ethernet", + .phy_id_mask = 0x001fffff, + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_INTERRUPT, + .config_aneg = &genphy_config_aneg, + .config_init = &rtl8366rb_config_init, + .read_status = &genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, }, }; @@ -218,6 +249,7 @@ static struct mdio_device_id __maybe_unused realtek_tbl[] = { { 0x001cc914, 0x001fffff }, { 0x001cc915, 0x001fffff }, { 0x001cc916, 0x001fffff }, + { 0x001cc961, 0x001fffff }, { } };