From patchwork Fri Jun 22 15:33:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todor Tomov X-Patchwork-Id: 139697 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1020214lji; Fri, 22 Jun 2018 08:38:13 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIHyJTfRUsoKgToFl5fMsQ3Y3jYFDOniCDlMdpr1U9yF7gCZS5Atd8Ttzs4rvX/c+CAg9g3 X-Received: by 2002:a17:902:925:: with SMTP id 34-v6mr2239275plm.103.1529681892928; Fri, 22 Jun 2018 08:38:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529681892; cv=none; d=google.com; s=arc-20160816; b=H6TI2zTuy/tp+QojApFRirSbx9h7IllgITkv++/5JFCHth4Pdv/LTt7J3pXNGrV768 hDzExIEaXZAjL8hxSLaaN2EMKQuuH4EHl+aabYVqBTvVqySCoAXHfwRD53/+3vvf5VxV A739Bv+4C0m/xaGpiy/2bGnU9Q1bzH5dNyL9rYYeeeggS7wHgyFbTx/txygYONiVQZDe UDLE2PXYrr+58oQia2blUyEECCAPQ7RHOekMjhVc5rKtpBM3hCkhcmzmyZV81JZ8hcKd OuxX2sq+ulNSBQlTfBoHDG5AT2PeXT5PRc+LICsLaxQKkNMm7jKH+3eEu/dKpOfoePk7 1N+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=kazahbVygXMg/tODLJv7oA2yjE6cv4IlWWhcVrRFOJM=; b=jF3O1H+NSUhdiORWK1MMgBNXsjqrGKOa9iWL4z1TN9KQBTa6oJW0I/OCGYdx/4IdYA LCXlrmvNDQx5wmDDOONV8JJ9pCVGg09IuVRroEWo7NCHIL8cMdU59quIa56G5ecu2hBA NHn3ZpbPujEgHM26kUFLhCCt6ayvC9DmzkaiWgZV7p1xERuDDD/tUXlZ0gMDfAivHC9I iEyM6mupoS+F/TiAHVv70YgZZppDAiQyCXLM4PU9BGJN7+/OdjjckwfYvKfKDXifh5dz CQe1kgeRgiZ1awwwcjnN1sTqTW38uCkqQtOorwfFhcSDEYdfMULRWD6FCvxJREG4eeYP QFMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r59-v6si7458711plb.314.2018.06.22.08.38.12; Fri, 22 Jun 2018 08:38:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934154AbeFVPiL (ORCPT + 31 others); Fri, 22 Jun 2018 11:38:11 -0400 Received: from ns.mm-sol.com ([37.157.136.199]:46550 "EHLO extserv.mm-sol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933989AbeFVPeI (ORCPT ); Fri, 22 Jun 2018 11:34:08 -0400 Received: from mms-0439.qualcomm.mm-sol.com (unknown [37.157.136.206]) by extserv.mm-sol.com (Postfix) with ESMTPSA id 9F0674F88D; Fri, 22 Jun 2018 18:33:59 +0300 (EEST) From: Todor Tomov To: mchehab@kernel.org, sakari.ailus@linux.intel.com, hans.verkuil@cisco.com, laurent.pinchart+renesas@ideasonboard.com, linux-media@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Todor Tomov Subject: [PATCH 21/32] media: camss: csid: Add support for 8x96 Date: Fri, 22 Jun 2018 18:33:30 +0300 Message-Id: <1529681621-9682-22-git-send-email-todor.tomov@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529681621-9682-1-git-send-email-todor.tomov@linaro.org> References: <1529681621-9682-1-git-send-email-todor.tomov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org CSID hardware modules on 8x16 and 8x96 are similar. There is no need to duplicate the code by adding separate versions. Just update the register macros to return the correct register addresses. Signed-off-by: Todor Tomov --- drivers/media/platform/qcom/camss/camss-csid.c | 60 ++++++++++++++++---------- 1 file changed, 37 insertions(+), 23 deletions(-) -- 2.7.4 diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index ea2b0ba..ff0e0d5 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -27,21 +27,26 @@ #define CAMSS_CSID_HW_VERSION 0x0 #define CAMSS_CSID_CORE_CTRL_0 0x004 #define CAMSS_CSID_CORE_CTRL_1 0x008 -#define CAMSS_CSID_RST_CMD 0x00c -#define CAMSS_CSID_CID_LUT_VC_n(n) (0x010 + 0x4 * (n)) -#define CAMSS_CSID_CID_n_CFG(n) (0x020 + 0x4 * (n)) -#define CAMSS_CSID_IRQ_CLEAR_CMD 0x060 -#define CAMSS_CSID_IRQ_MASK 0x064 -#define CAMSS_CSID_IRQ_STATUS 0x068 -#define CAMSS_CSID_TG_CTRL 0x0a0 +#define CAMSS_CSID_RST_CMD(v) ((v) == CAMSS_8x16 ? 0x00c : 0x010) +#define CAMSS_CSID_CID_LUT_VC_n(v, n) \ + (((v) == CAMSS_8x16 ? 0x010 : 0x014) + 0x4 * (n)) +#define CAMSS_CSID_CID_n_CFG(v, n) \ + (((v) == CAMSS_8x16 ? 0x020 : 0x024) + 0x4 * (n)) +#define CAMSS_CSID_IRQ_CLEAR_CMD(v) ((v) == CAMSS_8x16 ? 0x060 : 0x064) +#define CAMSS_CSID_IRQ_MASK(v) ((v) == CAMSS_8x16 ? 0x064 : 0x068) +#define CAMSS_CSID_IRQ_STATUS(v) ((v) == CAMSS_8x16 ? 0x068 : 0x06c) +#define CAMSS_CSID_TG_CTRL(v) ((v) == CAMSS_8x16 ? 0x0a0 : 0x0a8) #define CAMSS_CSID_TG_CTRL_DISABLE 0xa06436 #define CAMSS_CSID_TG_CTRL_ENABLE 0xa06437 -#define CAMSS_CSID_TG_VC_CFG 0x0a4 +#define CAMSS_CSID_TG_VC_CFG(v) ((v) == CAMSS_8x16 ? 0x0a4 : 0x0ac) #define CAMSS_CSID_TG_VC_CFG_H_BLANKING 0x3ff #define CAMSS_CSID_TG_VC_CFG_V_BLANKING 0x7f -#define CAMSS_CSID_TG_DT_n_CGG_0(n) (0x0ac + 0xc * (n)) -#define CAMSS_CSID_TG_DT_n_CGG_1(n) (0x0b0 + 0xc * (n)) -#define CAMSS_CSID_TG_DT_n_CGG_2(n) (0x0b4 + 0xc * (n)) +#define CAMSS_CSID_TG_DT_n_CGG_0(v, n) \ + (((v) == CAMSS_8x16 ? 0x0ac : 0x0b4) + 0xc * (n)) +#define CAMSS_CSID_TG_DT_n_CGG_1(v, n) \ + (((v) == CAMSS_8x16 ? 0x0b0 : 0x0b8) + 0xc * (n)) +#define CAMSS_CSID_TG_DT_n_CGG_2(v, n) \ + (((v) == CAMSS_8x16 ? 0x0b4 : 0x0bc) + 0xc * (n)) #define DATA_TYPE_EMBEDDED_DATA_8BIT 0x12 #define DATA_TYPE_YUV422_8BIT 0x1e @@ -203,10 +208,11 @@ static const struct csid_fmts *csid_get_fmt_entry(u32 code) static irqreturn_t csid_isr(int irq, void *dev) { struct csid_device *csid = dev; + enum camss_version ver = csid->camss->version; u32 value; - value = readl_relaxed(csid->base + CAMSS_CSID_IRQ_STATUS); - writel_relaxed(value, csid->base + CAMSS_CSID_IRQ_CLEAR_CMD); + value = readl_relaxed(csid->base + CAMSS_CSID_IRQ_STATUS(ver)); + writel_relaxed(value, csid->base + CAMSS_CSID_IRQ_CLEAR_CMD(ver)); if ((value >> 11) & 0x1) complete(&csid->reset_complete); @@ -289,7 +295,8 @@ static int csid_reset(struct csid_device *csid) reinit_completion(&csid->reset_complete); - writel_relaxed(0x7fff, csid->base + CAMSS_CSID_RST_CMD); + writel_relaxed(0x7fff, csid->base + + CAMSS_CSID_RST_CMD(csid->camss->version)); time = wait_for_completion_timeout(&csid->reset_complete, msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); @@ -370,6 +377,7 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable) { struct csid_device *csid = v4l2_get_subdevdata(sd); struct csid_testgen_config *tg = &csid->testgen; + enum camss_version ver = csid->camss->version; u32 val; if (enable) { @@ -402,13 +410,14 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable) /* 1:0 VC */ val = ((CAMSS_CSID_TG_VC_CFG_V_BLANKING & 0xff) << 24) | ((CAMSS_CSID_TG_VC_CFG_H_BLANKING & 0x7ff) << 13); - writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); + writel_relaxed(val, csid->base + + CAMSS_CSID_TG_VC_CFG(ver)); /* 28:16 bytes per lines, 12:0 num of lines */ val = ((num_bytes_per_line & 0x1fff) << 16) | (num_lines & 0x1fff); writel_relaxed(val, csid->base + - CAMSS_CSID_TG_DT_n_CGG_0(0)); + CAMSS_CSID_TG_DT_n_CGG_0(ver, 0)); dt = csid_get_fmt_entry( csid->fmt[MSM_CSID_PAD_SRC].code)->data_type; @@ -416,12 +425,12 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable) /* 5:0 data type */ val = dt; writel_relaxed(val, csid->base + - CAMSS_CSID_TG_DT_n_CGG_1(0)); + CAMSS_CSID_TG_DT_n_CGG_1(ver, 0)); /* 2:0 output test pattern */ val = tg->payload_mode; writel_relaxed(val, csid->base + - CAMSS_CSID_TG_DT_n_CGG_2(0)); + CAMSS_CSID_TG_DT_n_CGG_2(ver, 0)); df = csid_get_fmt_entry( csid->fmt[MSM_CSID_PAD_SRC].code)->decode_format; @@ -450,22 +459,27 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable) dt_shift = (cid % 4) * 8; - val = readl_relaxed(csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); + val = readl_relaxed(csid->base + + CAMSS_CSID_CID_LUT_VC_n(ver, vc)); val &= ~(0xff << dt_shift); val |= dt << dt_shift; - writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); + writel_relaxed(val, csid->base + + CAMSS_CSID_CID_LUT_VC_n(ver, vc)); val = (df << 4) | 0x3; - writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid)); + writel_relaxed(val, csid->base + + CAMSS_CSID_CID_n_CFG(ver, cid)); if (tg->enabled) { val = CAMSS_CSID_TG_CTRL_ENABLE; - writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); + writel_relaxed(val, csid->base + + CAMSS_CSID_TG_CTRL(ver)); } } else { if (tg->enabled) { val = CAMSS_CSID_TG_CTRL_DISABLE; - writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); + writel_relaxed(val, csid->base + + CAMSS_CSID_TG_CTRL(ver)); } }