diff mbox series

[edk2,edk2-platforms,v3,2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address

Message ID 20180713081540.8414-3-ming.huang@linaro.org
State New
Headers show
Series Improve D0x platforms and bug fix | expand

Commit Message

Ming Huang July 13, 2018, 8:15 a.m. UTC 
From: Jason Zhang <zhangjinsong2@huawei.com>


1. During test PCIe mcs9922 UART card, the card can't
   work because the IO ATU config is overlap by Cfg0/Cfg1
   ATU address.
2. After adjust the ATU windows, Cfg0/Cfg1 config as below:
     Cfg0 is equal to "ECAM + (BusBase, 0, 0)"
     Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)"

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>

Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Signed-off-by: Ming Huang <ming.huang@linaro.org>

---
 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

-- 
2.17.0

_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
diff mbox series

Patch

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 55b80aa4e4..e5f66eaa4a 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -640,11 +640,12 @@  void SetAtuConfig0RW (
 {
     UINTN RbPciBase = Private->RbPciBar;
     UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+    UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0);
 
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32));
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
@@ -666,12 +667,12 @@  void SetAtuConfig1RW (
 {
     UINTN RbPciBase = Private->RbPciBar;
     UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
-
+    UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32));
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);