| Message ID | 1532063694-3466-1-git-send-email-sumit.garg@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | synquacer: Enable optional OP-TEE support | expand |
On Fri, Jul 20, 2018 at 10:44:54AM +0530, Sumit Garg wrote: > OP-TEE loading is optional on Developerbox controlled via SCP > firmware. To check if OP-TEE is loaded or not, we use DRAM1 region > info passed by SCP firmware. > > Signed-off-by: Sumit Garg <sumit.garg@linaro.org> This approach looks OK. > --- > plat/socionext/synquacer/platform.mk | 4 ++++ > plat/socionext/synquacer/sq_bl31_setup.c | 35 ++++++++++++++++++++++---------- > 2 files changed, 28 insertions(+), 11 deletions(-) > > diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk > index 546f84a..96427a1 100644 > --- a/plat/socionext/synquacer/platform.mk > +++ b/plat/socionext/synquacer/platform.mk > @@ -18,6 +18,10 @@ ERRATA_A53_855873 := 1 > # Libraries > include lib/xlat_tables_v2/xlat_tables.mk > > +ifeq (${SPD},opteed) > +TF_CFLAGS_aarch64 += -DBL32_BASE=0xfc000000 > +endif > + > PLAT_PATH := plat/socionext/synquacer > PLAT_INCLUDES := -I$(PLAT_PATH)/include \ > -I$(PLAT_PATH)/drivers/scpi \ > diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c > index 461c8de..9e5fa6f 100644 > --- a/plat/socionext/synquacer/sq_bl31_setup.c > +++ b/plat/socionext/synquacer/sq_bl31_setup.c > @@ -58,6 +58,8 @@ uint32_t sq_get_spsr_for_bl33_entry(void) > void bl31_early_platform_setup(bl31_params_t *from_bl2, > void *plat_params_from_bl2) > { > + struct draminfo di = {0}; > + > /* Initialize the console to provide early debug support */ > (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, > PLAT_SQ_BOOT_UART_CLK_IN_HZ, > @@ -70,15 +72,29 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, > assert(from_bl2 == NULL); > assert(plat_params_from_bl2 == NULL); > > + /* Initialize power controller before setting up topology */ > + plat_sq_pwrc_setup(); > + > #ifdef BL32_BASE > - /* Populate entry point information for BL32 */ > - SET_PARAM_HEAD(&bl32_image_ep_info, > - PARAM_EP, > - VERSION_1, > - 0); > - SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); > - bl32_image_ep_info.pc = BL32_BASE; > - bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); > + scpi_get_draminfo(&di); > + > + /* > + * Check if OP-TEE has been loaded in Secure RAM allocated > + * from DRAM1 region > + */ > + if ((di.base1 + di.size1) <= BL32_BASE) { > + NOTICE("OP-TEE has been loaded by SCP firmware\n"); > + /* Populate entry point information for BL32 */ > + SET_PARAM_HEAD(&bl32_image_ep_info, > + PARAM_EP, > + VERSION_1, > + 0); > + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); > + bl32_image_ep_info.pc = BL32_BASE; > + bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); > + } else { > + NOTICE("OP-TEE has not been loaded by SCP firmware\n"); > + } > #endif /* BL32_BASE */ > > /* Populate entry point information for BL33 */ > @@ -125,9 +141,6 @@ void bl31_platform_setup(void) > > /* Allow access to the System counter timer module */ > sq_configure_sys_timer(); > - > - /* Initialize power controller before setting up topology */ > - plat_sq_pwrc_setup(); > } > > void bl31_plat_runtime_setup(void) > -- > 2.7.4 >
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk index 546f84a..96427a1 100644 --- a/plat/socionext/synquacer/platform.mk +++ b/plat/socionext/synquacer/platform.mk @@ -18,6 +18,10 @@ ERRATA_A53_855873 := 1 # Libraries include lib/xlat_tables_v2/xlat_tables.mk +ifeq (${SPD},opteed) +TF_CFLAGS_aarch64 += -DBL32_BASE=0xfc000000 +endif + PLAT_PATH := plat/socionext/synquacer PLAT_INCLUDES := -I$(PLAT_PATH)/include \ -I$(PLAT_PATH)/drivers/scpi \ diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index 461c8de..9e5fa6f 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -58,6 +58,8 @@ uint32_t sq_get_spsr_for_bl33_entry(void) void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { + struct draminfo di = {0}; + /* Initialize the console to provide early debug support */ (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, PLAT_SQ_BOOT_UART_CLK_IN_HZ, @@ -70,15 +72,29 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, assert(from_bl2 == NULL); assert(plat_params_from_bl2 == NULL); + /* Initialize power controller before setting up topology */ + plat_sq_pwrc_setup(); + #ifdef BL32_BASE - /* Populate entry point information for BL32 */ - SET_PARAM_HEAD(&bl32_image_ep_info, - PARAM_EP, - VERSION_1, - 0); - SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); - bl32_image_ep_info.pc = BL32_BASE; - bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + scpi_get_draminfo(&di); + + /* + * Check if OP-TEE has been loaded in Secure RAM allocated + * from DRAM1 region + */ + if ((di.base1 + di.size1) <= BL32_BASE) { + NOTICE("OP-TEE has been loaded by SCP firmware\n"); + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + } else { + NOTICE("OP-TEE has not been loaded by SCP firmware\n"); + } #endif /* BL32_BASE */ /* Populate entry point information for BL33 */ @@ -125,9 +141,6 @@ void bl31_platform_setup(void) /* Allow access to the System counter timer module */ sq_configure_sys_timer(); - - /* Initialize power controller before setting up topology */ - plat_sq_pwrc_setup(); } void bl31_plat_runtime_setup(void)
OP-TEE loading is optional on Developerbox controlled via SCP firmware. To check if OP-TEE is loaded or not, we use DRAM1 region info passed by SCP firmware. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> --- plat/socionext/synquacer/platform.mk | 4 ++++ plat/socionext/synquacer/sq_bl31_setup.c | 35 ++++++++++++++++++++++---------- 2 files changed, 28 insertions(+), 11 deletions(-) -- 2.7.4