diff mbox series

[edk2,edk2-platforms,v2,12/12] Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE

Message ID 20180724063220.61679-13-ming.huang@linaro.org
State New
Headers show
Series Switching to generic PciHostBridge driver | expand

Commit Message

Ming Huang July 24, 2018, 6:32 a.m. UTC 
From: Heyi Guo <heyi.guo@linaro.org>


In structure PCI_ROOT_BRIDGE_RESOURCE_APPETURE, MemBase is redundant
with CpuMemRegionBase, and MemLimit can be calculated by
CpuMemRegionBase + PciRegionLimit - PciRegionBase so it is also
redundant.

Remove these two fields to make things simple and clear.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Signed-off-by: Yi Li <phoenix.liyi@huawei.com>

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
 Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 16 ----------
 Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 32 --------------------
 Silicon/Hisilicon/Include/Library/PlatformPciLib.h             |  2 --
 3 files changed, 50 deletions(-)

-- 
2.17.0

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diff mbox series

Patch

diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
index 3a770d17bb..59c468ac4b 100644
--- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
+++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
@@ -32,8 +32,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB0_ECAM_BASE, //ecam
       0,  //BusBase
       31, //BusLimit
-      PCI_HB0RB0_PCIREGION_BASE, //Membase
-      PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
       PCI_HB0RB0_IO_BASE,  //IoBase
       (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
       PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -49,8 +47,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB1_ECAM_BASE,//ecam
       224,  //BusBase
       254, //BusLimit
-      PCI_HB0RB1_PCIREGION_BASE, //Membase
-      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB1_IO_BASE),  //IoBase
       (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
       PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -65,8 +61,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB2_ECAM_BASE,
       128,  //BusBase
       159, //BusLimit
-      PCI_HB0RB2_PCIREGION_BASE ,//MemBase
-      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB2_IO_BASE),  //IOBase
       (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
       PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -82,8 +76,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB3_ECAM_BASE,
       96,  //BusBase
       127, //BusLimit
-      (PCI_HB0RB3_ECAM_BASE),  //MemBase
-      (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
       (0), //IoBase
       (0),  //IoLimit
       0,
@@ -100,8 +92,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB0_ECAM_BASE,
       128,  //BusBase
       159, //BusLimit
-      (PCI_HB1RB0_ECAM_BASE),  //MemBase
-      (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
       (0), //IoBase
       (0),  //IoLimit
       0,
@@ -116,8 +106,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB1_ECAM_BASE,
       160,  //BusBase
       191, //BusLimit
-      (PCI_HB1RB1_ECAM_BASE),  //MemBase
-      (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
       (0), //IoBase
       (0),  //IoLimit
       0,
@@ -132,8 +120,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB2_ECAM_BASE,
       192,  //BusBase
       223, //BusLimit
-      (PCI_HB1RB2_ECAM_BASE),  //MemBase
-      (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
       (0), //IoBase
       (0),  //IoLimit
       0,
@@ -149,8 +135,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB3_ECAM_BASE,
       224,  //BusBase
       255, //BusLimit
-      (PCI_HB1RB3_ECAM_BASE),  //MemBase
-      (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
       (0), //IoBase
       (0),  //IoLimit
       0,
diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
index 42bbdd8c98..0dc988a1d3 100644
--- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
+++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
@@ -33,8 +33,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB0_ECAM_BASE, //ecam
       0x80,  //BusBase
       0x87, //BusLimit
-      PCI_HB0RB0_PCIREGION_BASE, //Membase
-      PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
       PCI_HB0RB0_IO_BASE,  //IoBase
       (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
       PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -49,8 +47,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB1_ECAM_BASE,//ecam
       0x90,  //BusBase
       0x97, //BusLimit
-      PCI_HB0RB1_PCIREGION_BASE, //Membase
-      PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB1_IO_BASE),  //IoBase
       (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
       PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -65,8 +61,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB2_ECAM_BASE,
       0xF8,  //BusBase
       0xFF, //BusLimit
-      PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
-      PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB2_IO_BASE),  //IOBase
       (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
       PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -82,8 +76,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB3_ECAM_BASE,
       0xb0,  //BusBase
       0xb7, //BusLimit
-      (PCI_HB0RB3_ECAM_BASE),  //MemBase
-      (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit
       (PCI_HB0RB3_IO_BASE), //IoBase
       (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1),  //IoLimit
       PCI_HB0RB3_CPUMEMREGIONBASE,
@@ -98,8 +90,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB4_ECAM_BASE, //ecam
       0x88,  //BusBase
       0x8f, //BusLimit
-      PCI_HB0RB4_CPUMEMREGIONBASE, //Membase
-      PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit
       PCI_HB0RB4_IO_BASE,  //IoBase
       (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
       PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -114,8 +104,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB5_ECAM_BASE,//ecam
       0x78,  //BusBase
       0x7F, //BusLimit
-      PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
-      PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB5_IO_BASE),  //IoBase
       (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
       PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -130,8 +118,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB6_ECAM_BASE,
       0xC0,  //BusBase
       0xC7, //BusLimit
-      PCI_HB0RB6_PCIREGION_BASE ,//MemBase
-      PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB6_IO_BASE),  //IOBase
       (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
       PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -147,8 +133,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB0RB7_ECAM_BASE,
       0x90,  //BusBase
       0x97, //BusLimit
-      PCI_HB0RB7_CPUMEMREGIONBASE,  //MemBase
-      PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB7_IO_BASE), //IoBase
       (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1),  //IoLimit
       PCI_HB0RB7_CPUMEMREGIONBASE,
@@ -165,8 +149,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB0_ECAM_BASE,
       0x80,  //BusBase
       0x87, //BusLimit
-      (PCI_HB1RB0_ECAM_BASE),  //MemBase
-      (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit
       PCI_HB1RB0_IO_BASE, //IoBase
       (PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit
       PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -181,8 +163,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB1_ECAM_BASE,
       0x90,  //BusBase
       0x97, //BusLimit
-      (PCI_HB1RB1_ECAM_BASE),  //MemBase
-      (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit
       PCI_HB1RB1_IO_BASE, //IoBase
       (PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit
       PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -197,8 +177,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB2_ECAM_BASE,
       0x10,  //BusBase
       0x1f, //BusLimit
-      PCI_HB1RB2_CPUMEMREGIONBASE,  //MemBase
-      PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit
       PCI_HB1RB2_IO_BASE, //IoBase
       (PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit
       PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -214,8 +192,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB3_ECAM_BASE,
       0xb0,  //BusBase
       0xb7, //BusLimit
-      (PCI_HB1RB3_ECAM_BASE),  //MemBase
-      (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit
       PCI_HB1RB3_IO_BASE, //IoBase
       (PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit
       PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -230,8 +206,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB4_ECAM_BASE,
       0x20,  //BusBase
       0x2f, //BusLimit
-      PCI_HB1RB4_CPUMEMREGIONBASE,  //MemBase
-      PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit
       PCI_HB1RB4_IO_BASE, //IoBase
       (PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit
       PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -246,8 +220,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB5_ECAM_BASE,
       0x30,  //BusBase
       0x3f, //BusLimit
-      PCI_HB1RB5_CPUMEMREGIONBASE,  //MemBase
-      PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit
       PCI_HB1RB5_IO_BASE, //IoBase
       (PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit
       PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -262,8 +234,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB6_ECAM_BASE,
       0xa8,  //BusBase
       0xaf, //BusLimit
-      (PCI_HB1RB6_ECAM_BASE),  //MemBase
-      PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit
       PCI_HB1RB6_IO_BASE, //IoBase
       (PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit
       PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
@@ -279,8 +249,6 @@  PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
       PCI_HB1RB7_ECAM_BASE,
       0xb8,  //BusBase
       0xbf, //BusLimit
-      (PCI_HB1RB7_ECAM_BASE),  //MemBase
-      PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit
       PCI_HB1RB7_IO_BASE, //IoBase
       (PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit
       PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
index 6725a547d5..5fdc3d3e0a 100644
--- a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
+++ b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
@@ -194,8 +194,6 @@  typedef struct {
   UINT64          Ecam;
   UINT64          BusBase;
   UINT64          BusLimit;
-  UINT64          MemBase;
-  UINT64          MemLimit;
   UINT64          IoBase;
   UINT64          IoLimit;
   UINT64          CpuMemRegionBase;