diff mbox series

[5/7] aspeed_sdmc: Handle ECC training

Message ID 20180807075757.7242-6-joel@jms.id.au
State Superseded
Headers show
Series arm: aspeed: Extend SDRAM controller | expand

Commit Message

Joel Stanley Aug. 7, 2018, 7:57 a.m. UTC 
This is required to ensure u-boot SDRAM training completes.

Signed-off-by: Joel Stanley <joel@jms.id.au>

---
 hw/misc/aspeed_sdmc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

-- 
2.17.1

Comments

Cédric Le Goater Aug. 7, 2018, 10:29 a.m. UTC | #1 
On 08/07/2018 09:57 AM, Joel Stanley wrote:
> This is required to ensure u-boot SDRAM training completes.

> 

> Signed-off-by: Joel Stanley <joel@jms.id.au>




Reviewed-by: Cédric Le Goater <clg@kaod.org>


Thanks,

C.

> ---

>  hw/misc/aspeed_sdmc.c | 9 +++++++++

>  1 file changed, 9 insertions(+)

> 

> diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c

> index 522e01ef8c0d..89de3138aff0 100644

> --- a/hw/misc/aspeed_sdmc.c

> +++ b/hw/misc/aspeed_sdmc.c

> @@ -27,6 +27,10 @@

>  #define R_STATUS1         (0x60 / 4)

>  #define   PHY_BUSY_STATE      BIT(0)

>  

> +#define R_ECC_TEST_CTRL   (0x70 / 4)

> +#define   ECC_TEST_FINISHED   BIT(12)

> +#define   ECC_TEST_FAIL       BIT(13)

> +

>  /*

>   * Configuration register Ox4 (for Aspeed AST2400 SOC)

>   *

> @@ -148,6 +152,11 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,

>              /* Will never return 'busy' */

>              data &= ~PHY_BUSY_STATE;

>              break;

> +        case R_ECC_TEST_CTRL:

> +            /* Always done, always happy */

> +            data |= ECC_TEST_FINISHED;

> +            data &= ~ECC_TEST_FAIL;

> +            break;

>          default:

>              break;

>          }

>
diff mbox series

Patch

diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 522e01ef8c0d..89de3138aff0 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -27,6 +27,10 @@ 
 #define R_STATUS1         (0x60 / 4)
 #define   PHY_BUSY_STATE      BIT(0)
 
+#define R_ECC_TEST_CTRL   (0x70 / 4)
+#define   ECC_TEST_FINISHED   BIT(12)
+#define   ECC_TEST_FAIL       BIT(13)
+
 /*
  * Configuration register Ox4 (for Aspeed AST2400 SOC)
  *
@@ -148,6 +152,11 @@  static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
             /* Will never return 'busy' */
             data &= ~PHY_BUSY_STATE;
             break;
+        case R_ECC_TEST_CTRL:
+            /* Always done, always happy */
+            data |= ECC_TEST_FINISHED;
+            data &= ~ECC_TEST_FAIL;
+            break;
         default:
             break;
         }