From patchwork Fri Aug 10 14:52:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 143946 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp49878ljj; Fri, 10 Aug 2018 07:52:58 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzLoYzux+dnqR/kGpv4ROnzswdIWa2Eh76Z/3nbkwlx1PTpTiSXgE6qtgj0bUC72NDkpN7q X-Received: by 2002:a63:460d:: with SMTP id t13-v6mr4220878pga.201.1533912778356; Fri, 10 Aug 2018 07:52:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533912778; cv=none; d=google.com; s=arc-20160816; b=sTdyLFxd8HyaqOKeyQxp64aC+7njhAMMWORfS1nCMgu8v617Nx9xksIoWych/eUuda V/MV2OtOXwzu7EMa/XXuF5qAhLCYpAnP9bKtiE3sXcQ7dY0eA9Podr41Y2WYJFjI5g4G IFdpkqM8tBMpF2dTGCfqPANPiWn+yGsFaMgXjiWpnZf25SlPrxblxzb7rnQfl+Vtu6vq e0vcEaf7lHQy2yoH91r9FlzsUZO8nzQSqbH+0YcIVkRqQzyrSKzbaPZM5QDCU7WOVtsP ohwzittvSJ6DRCNgPpVjzJBRFWLxL/yL1k3VV365NqbgVzLbNrS7RjWB+Ul7rmAQeHxt R3QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=9oUIEusk495SIX9kXu/WUGAbH7L0f6JAltllXHNc7ks=; b=c0dn4Dw7HfzB4l0S5Z826eCx/5BgXPH6qpJrcPV3rqmMvyiwgfXC94Y4ljLQd/rLFf 0QlZjKugJ7uZBcEmVxXhxfZulv8BkzA/UFtiJkAOuIpsbjfhzX75Dd/BqDNYlgV/Clsk rJztpb9tbz1mEoD0Xm+gQvAYv2LaywdzJLMBaMc8NXhfHWTg0mxcE4m+uw2UQFQB6f6c STGizosR89HReYu4eCEBqSW+2n5ZHQeZwMYHHX58qH1dZlpx5EbYey2/rYzmVYRd2eaI 2ApMcvZPt2sgg5OmHVp/yd1iCR8n+9KGUDRLI7k7WYlfg4781bt3zZYFWfo/ODlM5Hap 4P1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fDe9hhyt; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a3-v6si8642378pln.298.2018.08.10.07.52.58; Fri, 10 Aug 2018 07:52:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fDe9hhyt; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728635AbeHJRXJ (ORCPT + 5 others); Fri, 10 Aug 2018 13:23:09 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:44566 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728596AbeHJRXJ (ORCPT ); Fri, 10 Aug 2018 13:23:09 -0400 Received: by mail-wr1-f65.google.com with SMTP id r16-v6so8526703wrt.11 for ; Fri, 10 Aug 2018 07:52:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9oUIEusk495SIX9kXu/WUGAbH7L0f6JAltllXHNc7ks=; b=fDe9hhytJG0RF8rhbn+47nA7nVGZgSi5GoxHmDWZ/FDIp3LmfvcWtFr3eeYpffMVsx txJ91+MXpGjCAjUDBTJcZDikUD9hUWJbUzVFMe2UpXWFNt+TQ+fZPtTPKy8VQ1u7xhYZ SDGvN868w6X6yEhGEWaiHRIhLWtVffvPCYGH4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9oUIEusk495SIX9kXu/WUGAbH7L0f6JAltllXHNc7ks=; b=sY06J9s4nlk9sj2l8YHu4zwoBXESuw7b/g/DDqHAgM/Gj3CWhZfampIwTksfYFemO0 BTD9e4fgh5tIFEkMfOHjTu6r7a/jYfkv4cvSFY1aYpTlQpTmsLJmY/bIFiZdB4g2feF9 tN/rJroB5TK6WXageIeUZGbKsqiF9pUmrbgxHuQmMrxXfP7p//rkqv202chaK9Qn/wVa 0iKBO2wef5ug2Bn2wkXufjGYMnaKPw/Osa4RBqN+pAYFme6d6EiJCsmtGdykCiw+3vlW 3gz2WBtYo/B73y48GlmaKrVdPkIeGiYK2pcTsI0il5kdZD/BC7r63JJbychrmswEzNNw eXlQ== X-Gm-Message-State: AOUpUlFo6eYTDUDQ7fh1Tg1Ca94BeLFh+tlC9q5uIx9U/P3aNqQLwtd5 aH0h1R1SDd+LEzSeL0vRMYxayg== X-Received: by 2002:adf:820a:: with SMTP id 10-v6mr4395879wrb.144.1533912774010; Fri, 10 Aug 2018 07:52:54 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 9-v6sm19842700wrb.48.2018.08.10.07.52.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Aug 2018 07:52:53 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, abailon@baylibre.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v8 6/8] dt-bindings: interconnect: Document qcom, msm8916 NoC bindings Date: Fri, 10 Aug 2018 17:52:31 +0300 Message-Id: <20180810145233.16466-7-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180810145233.16466-1-georgi.djakov@linaro.org> References: <20180810145233.16466-1-georgi.djakov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device-tree bindings of the Network-On-Chip interconnect hardware found on Qualcomm msm8916 platforms. Signed-off-by: Georgi Djakov Reviewed-by: Evan Green --- .../bindings/interconnect/qcom-msm8916.txt | 41 ++++++++ include/dt-bindings/interconnect/qcom.h | 98 +++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt create mode 100644 include/dt-bindings/interconnect/qcom.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt b/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt new file mode 100644 index 000000000000..744df51df4ed --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt @@ -0,0 +1,41 @@ +Qualcomm MSM8916 Network-On-Chip interconnect driver binding +---------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,msm8916-bimc" + "qcom,msm8916-pnoc" + "qcom,msm8916-snoc" +- #interconnect-cells : should contain 1 +- reg : shall contain base register location and length + +Optional properties : +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus_clk" and "bus_a_clk" + +Examples: + + snoc: snoc@580000 { + compatible = "qcom,msm8916-snoc"; + #interconnect-cells = <1>; + reg = <0x580000 0x14000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + bimc: bimc@400000 { + compatible = "qcom,msm8916-bimc"; + #interconnect-cells = <1>; + reg = <0x400000 0x62000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + pnoc: pnoc@500000 { + compatible = "qcom,msm8916-pnoc"; + #interconnect-cells = <1>; + reg = <0x500000 0x11000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; diff --git a/include/dt-bindings/interconnect/qcom.h b/include/dt-bindings/interconnect/qcom.h new file mode 100644 index 000000000000..f4d154f0afbf --- /dev/null +++ b/include/dt-bindings/interconnect/qcom.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_H + +#define BIMC_SNOC_MAS 0 +#define BIMC_SNOC_SLV 1 +#define MASTER_AMPSS_M0 2 +#define MASTER_BLSP_1 3 +#define MASTER_CRYPTO_CORE0 4 +#define MASTER_DEHR 5 +#define MASTER_GRAPHICS_3D 6 +#define MASTER_JPEG 7 +#define MASTER_LPASS 8 +#define MASTER_MDP_PORT0 9 +#define MASTER_QDSS_BAM 10 +#define MASTER_QDSS_ETR 11 +#define MASTER_SDCC_1 12 +#define MASTER_SDCC_2 13 +#define MASTER_SNOC_CFG 14 +#define MASTER_SPDM 15 +#define MASTER_TCU_0 16 +#define MASTER_TCU_1 17 +#define MASTER_USB_HS 18 +#define MASTER_VFE 19 +#define MASTER_VIDEO_P0 20 +#define PNOC_INT_0 21 +#define PNOC_INT_1 22 +#define PNOC_M_0 23 +#define PNOC_M_1 24 +#define PNOC_SLV_0 25 +#define PNOC_SLV_1 26 +#define PNOC_SLV_2 27 +#define PNOC_SLV_3 28 +#define PNOC_SLV_4 29 +#define PNOC_SLV_8 30 +#define PNOC_SLV_9 31 +#define PNOC_SNOC_MAS 32 +#define PNOC_SNOC_SLV 33 +#define SLAVE_AMPSS_L2 34 +#define SLAVE_BIMC_CFG 35 +#define SLAVE_BLSP_1 36 +#define SLAVE_BOOT_ROM 37 +#define SLAVE_CAMERA_CFG 38 +#define SLAVE_CATS_128 39 +#define SLAVE_CLK_CTL 40 +#define SLAVE_CRYPTO_0_CFG 41 +#define SLAVE_DEHR_CFG 42 +#define SLAVE_DISPLAY_CFG 43 +#define SLAVE_EBI_CH0 44 +#define SLAVE_GRAPHICS_3D_CFG 45 +#define SLAVE_IMEM_CFG 46 +#define SLAVE_LPASS 47 +#define SLAVE_MPM 48 +#define SLAVE_MSM_PDM 49 +#define SLAVE_MSM_TCSR 50 +#define SLAVE_MSS 51 +#define SLAVE_OCMEM_64 52 +#define SLAVE_PMIC_ARB 53 +#define SLAVE_PNOC_CFG 54 +#define SLAVE_PRNG 55 +#define SLAVE_QDSS_CFG 56 +#define SLAVE_QDSS_STM 57 +#define SLAVE_RBCPR_CFG 58 +#define SLAVE_RPM_MSG_RAM 59 +#define SLAVE_SDCC_1 60 +#define SLAVE_SDCC_4 61 +#define SLAVE_SECURITY 62 +#define SLAVE_SERVICE_SNOC 63 +#define SLAVE_SNOC_CFG 64 +#define SLAVE_SPDM 65 +#define SLAVE_SYSTEM_IMEM 66 +#define SLAVE_TLMM 67 +#define SLAVE_USB_HS 68 +#define SLAVE_VENUS_CFG 69 +#define SNOC_BIMC_0_MAS 70 +#define SNOC_BIMC_0_SLV 71 +#define SNOC_BIMC_1_MAS 72 +#define SNOC_BIMC_1_SLV 73 +#define SNOC_INT_0 74 +#define SNOC_INT_1 75 +#define SNOC_INT_BIMC 76 +#define SNOC_MM_INT_0 77 +#define SNOC_MM_INT_1 78 +#define SNOC_MM_INT_2 79 +#define SNOC_MM_INT_BIMC 80 +#define SNOC_PNOC_MAS 81 +#define SNOC_PNOC_SLV 82 +#define SNOC_QDSS_INT 83 +#define SYSTEM_SLAVE_FAB_APPS 84 + +#endif