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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:30 -0700 Message-Id: <20180915161738.25257-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PATCH 05/13] target/arm: Derive id_isar3 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? The assertion does fire for the old cpus; they may be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 379d6a08a4..2b199845fc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -855,6 +855,38 @@ static uint32_t resolve_id_isar2(CPUARMState *env, uint32_t orig) return ret; } +static uint32_t resolve_id_isar3(CPUARMState *env) +{ + uint32_t ret = 0; + + if (arm_feature(env, ARM_FEATURE_V5)) { + ret = deposit32(ret, 0, 4, 1); /* Saturate */ + } + if (arm_feature(env, ARM_FEATURE_V6)) { + ret = deposit32(ret, 4, 4, 3); /* SIMD */ + } + ret = deposit32(ret, 8, 4, 1); /* SVC -- no pre-armv4t */ + /* SynchPrim */ + if (arm_feature(env, ARM_FEATURE_V6K)) { + ret = deposit32(ret, 12, 4, 2); /* ldrex, ldrexb, ldrexd */ + } else if (arm_feature(env, ARM_FEATURE_V6)) { + ret = deposit32(ret, 12, 4, 1); /* ldrex only */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2)) { + ret = deposit32(ret, 16, 4, 1); /* TabBranch */ + ret = deposit32(ret, 20, 4, 1); /* T32Copy */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2) || + arm_feature(env, ARM_FEATURE_V6K)) { + ret = deposit32(ret, 24, 4, 1); /* TrueNOP */ + } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + ret = deposit32(ret, 28, 4, 1); /* T32EE */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -871,6 +903,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_isar2; cpu->id_isar2 = resolve_id_isar2(env, orig); g_assert_cmphex(cpu->id_isar2, ==, orig); + + orig = cpu->id_isar3; + cpu->id_isar3 = resolve_id_isar3(env); + g_assert_cmphex(cpu->id_isar3, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)