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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:36 -0700 Message-Id: <20180915161738.25257-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52f Subject: [Qemu-devel] [PATCH 11/13] target/arm: Derive id_aa64isar1 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1c51b9f631..a9724f3bb1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1062,6 +1062,24 @@ static uint64_t resolve_id_aa64isar0(CPUARMState *env) return ret; } +static uint64_t resolve_id_aa64isar1(CPUARMState *env) +{ + uint64_t ret = 0; + + /* DPB -- not implemented yet */ + /* APA -- not implemented yet */ + /* API -- not implemented yet */ + /* JSCVT -- not implemented yet */ + if (arm_feature(env, ARM_FEATURE_V8_FCMA)) { + ret = deposit64(ret, 16, 4, 1); + } + /* LRCPC -- not implemented yet */ + /* GPA -- not implemented yet */ + /* GPI -- not implemented yet */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1102,6 +1120,8 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_aa64isar0; cpu->id_aa64isar0 = resolve_id_aa64isar0(env); g_assert_cmphex(cpu->id_aa64isar0, ==, orig); + + cpu->id_aa64isar1 = resolve_id_aa64isar1(env); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)