diff mbox series

[v2,8/9] target/arm: Convert sve from feature bit to pfr0 test

Message ID 20180927211322.16118-9-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Rely on id regs instead of features | expand

Commit Message

Richard Henderson Sept. 27, 2018, 9:13 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.h            | 16 +++++++++++++++-
 target/arm/translate-a64.h  |  1 +
 linux-user/aarch64/signal.c |  4 ++--
 linux-user/elfload.c        |  2 +-
 linux-user/syscall.c        | 10 ++++++----
 target/arm/cpu64.c          |  3 ++-
 target/arm/helper.c         |  7 ++++---
 target/arm/machine.c        |  3 +--
 target/arm/translate-a64.c  |  4 ++--
 9 files changed, 34 insertions(+), 16 deletions(-)

-- 
2.17.1

Comments

Philippe Mathieu-Daudé Sept. 28, 2018, 4:09 p.m. UTC | #1 
On 27/09/2018 23:13, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>


> ---

>  target/arm/cpu.h            | 16 +++++++++++++++-

>  target/arm/translate-a64.h  |  1 +

>  linux-user/aarch64/signal.c |  4 ++--

>  linux-user/elfload.c        |  2 +-

>  linux-user/syscall.c        | 10 ++++++----

>  target/arm/cpu64.c          |  3 ++-

>  target/arm/helper.c         |  7 ++++---

>  target/arm/machine.c        |  3 +--

>  target/arm/translate-a64.c  |  4 ++--

>  9 files changed, 34 insertions(+), 16 deletions(-)

> 

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index da841f8538..152a558a94 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -1508,6 +1508,16 @@ FIELD(ID_AA64ISAR1, LRCPC, 20, 4)

>  FIELD(ID_AA64ISAR1, GPA, 24, 4)

>  FIELD(ID_AA64ISAR1, GPI, 28, 4)

>  

> +FIELD(ID_AA64PFR0, EL0, 0, 4)

> +FIELD(ID_AA64PFR0, EL1, 4, 4)

> +FIELD(ID_AA64PFR0, EL2, 8, 4)

> +FIELD(ID_AA64PFR0, EL3, 12, 4)

> +FIELD(ID_AA64PFR0, FP, 16, 4)

> +FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)

> +FIELD(ID_AA64PFR0, GIC, 24, 4)

> +FIELD(ID_AA64PFR0, RAS, 28, 4)

> +FIELD(ID_AA64PFR0, SVE, 32, 4)

> +

>  QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);

>  

>  /* If adding a feature bit which corresponds to a Linux ELF

> @@ -1556,7 +1566,6 @@ enum arm_features {

>      ARM_FEATURE_PMU, /* has PMU support */

>      ARM_FEATURE_VBAR, /* has cp15 VBAR */

>      ARM_FEATURE_M_SECURITY, /* M profile Security Extension */

> -    ARM_FEATURE_SVE, /* has Scalable Vector Extension */

>      ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */

>      ARM_FEATURE_M_MAIN, /* M profile Main Extension */

>  };

> @@ -3235,4 +3244,9 @@ static inline bool aa64_feature_fcma(ARMCPU *cpu)

>      return FIELD_EX64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;

>  }

>  

> +static inline bool aa64_feature_sve(ARMCPU *cpu)

> +{

> +    return FIELD_EX64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;

> +}

> +

>  #endif

> diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h

> index b4ef9eb024..636f3fded3 100644

> --- a/target/arm/translate-a64.h

> +++ b/target/arm/translate-a64.h

> @@ -140,6 +140,7 @@ FORWARD_FEATURE(sm3)

>  FORWARD_FEATURE(sm4)

>  FORWARD_FEATURE(dp)

>  FORWARD_FEATURE(fcma)

> +FORWARD_FEATURE(sve)

>  

>  #undef FORWARD_FEATURE

>  

> diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c

> index 07fedfc33c..65272fb7a9 100644

> --- a/linux-user/aarch64/signal.c

> +++ b/linux-user/aarch64/signal.c

> @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env,

>              break;

>  

>          case TARGET_SVE_MAGIC:

> -            if (arm_feature(env, ARM_FEATURE_SVE)) {

> +            if (aa64_feature_sve(arm_env_get_cpu(env))) {

>                  vq = (env->vfp.zcr_el[1] & 0xf) + 1;

>                  sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);

>                  if (!sve && size == sve_size) {

> @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,

>                                        &layout);

>  

>      /* SVE state needs saving only if it exists.  */

> -    if (arm_feature(env, ARM_FEATURE_SVE)) {

> +    if (aa64_feature_sve(arm_env_get_cpu(env))) {

>          vq = (env->vfp.zcr_el[1] & 0xf) + 1;

>          sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);

>          sve_ofs = alloc_sigframe_space(sve_size, &layout);

> diff --git a/linux-user/elfload.c b/linux-user/elfload.c

> index 01707ebb91..c4969f163e 100644

> --- a/linux-user/elfload.c

> +++ b/linux-user/elfload.c

> @@ -593,7 +593,7 @@ static uint32_t get_elf_hwcap(void)

>      GET_FEATURE_ID(rdm, ARM_HWCAP_A64_ASIMDRDM);

>      GET_FEATURE_ID(dp, ARM_HWCAP_A64_ASIMDDP);

>      GET_FEATURE_ID(fcma, ARM_HWCAP_A64_FCMA);

> -    GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE);

> +    GET_FEATURE_ID(sve, ARM_HWCAP_A64_SVE);

>  

>  #undef GET_FEATURE

>  #undef GET_FEATURE_ID

> diff --git a/linux-user/syscall.c b/linux-user/syscall.c

> index 850b72a0c7..f927f51fb4 100644

> --- a/linux-user/syscall.c

> +++ b/linux-user/syscall.c

> @@ -10735,7 +10735,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,

>               * even though the current architectural maximum is VQ=16.

>               */

>              ret = -TARGET_EINVAL;

> -            if (arm_feature(cpu_env, ARM_FEATURE_SVE)

> +            if (aa64_feature_sve(arm_env_get_cpu(cpu_env))

>                  && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {

>                  CPUARMState *env = cpu_env;

>                  ARMCPU *cpu = arm_env_get_cpu(env);

> @@ -10754,9 +10754,11 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,

>              return ret;

>          case TARGET_PR_SVE_GET_VL:

>              ret = -TARGET_EINVAL;

> -            if (arm_feature(cpu_env, ARM_FEATURE_SVE)) {

> -                CPUARMState *env = cpu_env;

> -                ret = ((env->vfp.zcr_el[1] & 0xf) + 1) * 16;

> +            {

> +                ARMCPU *cpu = arm_env_get_cpu(cpu_env);

> +                if (aa64_feature_sve(cpu)) {

> +                    ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;

> +                }

>              }

>              return ret;

>  #endif /* AARCH64 */

> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

> index f9830b67f3..8f95de677a 100644

> --- a/target/arm/cpu64.c

> +++ b/target/arm/cpu64.c

> @@ -258,6 +258,8 @@ static void aarch64_max_initfn(Object *obj)

>  

>          FIELD_DP64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA, 1);

>  

> +        FIELD_DP64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE, 1);

> +

>          /* Replicate the same data to the 32-bit id registers.  */

>          FIELD_DP32(cpu->id_isar5, ID_ISAR5, AES, 2); /* AES + PMULL */

>          FIELD_DP32(cpu->id_isar5, ID_ISAR5, SHA1, 1);

> @@ -275,7 +277,6 @@ static void aarch64_max_initfn(Object *obj)

>           * present in either.

>           */

>          set_feature(&cpu->env, ARM_FEATURE_V8_FP16);

> -        set_feature(&cpu->env, ARM_FEATURE_SVE);

>          /* For usermode -cpu max we can use a larger and more efficient DCZ

>           * blocksize since we don't have to follow what the hardware does.

>           */

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index 5af89f6d9d..dd3a2c0b8b 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -5587,7 +5587,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)

>          define_one_arm_cp_reg(cpu, &sctlr);

>      }

>  

> -    if (arm_feature(env, ARM_FEATURE_SVE)) {

> +    if (aa64_feature_sve(cpu)) {

>          define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);

>          if (arm_feature(env, ARM_FEATURE_EL2)) {

>              define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);

> @@ -12587,13 +12587,15 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>      uint32_t flags;

>  

>      if (is_a64(env)) {

> +        ARMCPU *cpu = arm_env_get_cpu(env);

> +

>          *pc = env->pc;

>          flags = ARM_TBFLAG_AARCH64_STATE_MASK;

>          /* Get control bits for tagged addresses */

>          flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);

>          flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);

>  

> -        if (arm_feature(env, ARM_FEATURE_SVE)) {

> +        if (aa64_feature_sve(cpu)) {

>              int sve_el = sve_exception_el(env);

>              uint32_t zcr_len;

>  

> @@ -12604,7 +12606,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>                  zcr_len = 0;

>              } else {

>                  int current_el = arm_current_el(env);

> -                ARMCPU *cpu = arm_env_get_cpu(env);

>  

>                  zcr_len = cpu->sve_max_vq - 1;

>                  if (current_el <= 1) {

> diff --git a/target/arm/machine.c b/target/arm/machine.c

> index d44e891533..8b3ba96889 100644

> --- a/target/arm/machine.c

> +++ b/target/arm/machine.c

> @@ -131,9 +131,8 @@ static const VMStateDescription vmstate_iwmmxt = {

>  static bool sve_needed(void *opaque)

>  {

>      ARMCPU *cpu = opaque;

> -    CPUARMState *env = &cpu->env;

>  

> -    return arm_feature(env, ARM_FEATURE_SVE);

> +    return aa64_feature_sve(cpu);

>  }

>  

>  /* The first two words of each Zreg is stored in VFP state.  */

> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

> index 40575485aa..5527ffb203 100644

> --- a/target/arm/translate-a64.c

> +++ b/target/arm/translate-a64.c

> @@ -169,7 +169,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,

>      cpu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",

>                  vfp_get_fpcr(env), vfp_get_fpsr(env));

>  

> -    if (arm_feature(env, ARM_FEATURE_SVE)) {

> +    if (aa64_feature_sve(cpu)) {

>          int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */

>  

>          for (i = 0; i <= FFR_PRED_NUM; i++) {

> @@ -13786,7 +13786,7 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)

>          unallocated_encoding(s);

>          break;

>      case 0x2:

> -        if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) {

> +        if (!aa64_dc_feature_sve(s) || !disas_sve(s, insn)) {

>              unallocated_encoding(s);

>          }

>          break;

>
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index da841f8538..152a558a94 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1508,6 +1508,16 @@  FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
 FIELD(ID_AA64ISAR1, GPA, 24, 4)
 FIELD(ID_AA64ISAR1, GPI, 28, 4)
 
+FIELD(ID_AA64PFR0, EL0, 0, 4)
+FIELD(ID_AA64PFR0, EL1, 4, 4)
+FIELD(ID_AA64PFR0, EL2, 8, 4)
+FIELD(ID_AA64PFR0, EL3, 12, 4)
+FIELD(ID_AA64PFR0, FP, 16, 4)
+FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
+FIELD(ID_AA64PFR0, GIC, 24, 4)
+FIELD(ID_AA64PFR0, RAS, 28, 4)
+FIELD(ID_AA64PFR0, SVE, 32, 4)
+
 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
 
 /* If adding a feature bit which corresponds to a Linux ELF
@@ -1556,7 +1566,6 @@  enum arm_features {
     ARM_FEATURE_PMU, /* has PMU support */
     ARM_FEATURE_VBAR, /* has cp15 VBAR */
     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
-    ARM_FEATURE_SVE, /* has Scalable Vector Extension */
     ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
 };
@@ -3235,4 +3244,9 @@  static inline bool aa64_feature_fcma(ARMCPU *cpu)
     return FIELD_EX64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
 }
 
+static inline bool aa64_feature_sve(ARMCPU *cpu)
+{
+    return FIELD_EX64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
+}
+
 #endif
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index b4ef9eb024..636f3fded3 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -140,6 +140,7 @@  FORWARD_FEATURE(sm3)
 FORWARD_FEATURE(sm4)
 FORWARD_FEATURE(dp)
 FORWARD_FEATURE(fcma)
+FORWARD_FEATURE(sve)
 
 #undef FORWARD_FEATURE
 
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 07fedfc33c..65272fb7a9 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -314,7 +314,7 @@  static int target_restore_sigframe(CPUARMState *env,
             break;
 
         case TARGET_SVE_MAGIC:
-            if (arm_feature(env, ARM_FEATURE_SVE)) {
+            if (aa64_feature_sve(arm_env_get_cpu(env))) {
                 vq = (env->vfp.zcr_el[1] & 0xf) + 1;
                 sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
                 if (!sve && size == sve_size) {
@@ -433,7 +433,7 @@  static void target_setup_frame(int usig, struct target_sigaction *ka,
                                       &layout);
 
     /* SVE state needs saving only if it exists.  */
-    if (arm_feature(env, ARM_FEATURE_SVE)) {
+    if (aa64_feature_sve(arm_env_get_cpu(env))) {
         vq = (env->vfp.zcr_el[1] & 0xf) + 1;
         sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
         sve_ofs = alloc_sigframe_space(sve_size, &layout);
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 01707ebb91..c4969f163e 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -593,7 +593,7 @@  static uint32_t get_elf_hwcap(void)
     GET_FEATURE_ID(rdm, ARM_HWCAP_A64_ASIMDRDM);
     GET_FEATURE_ID(dp, ARM_HWCAP_A64_ASIMDDP);
     GET_FEATURE_ID(fcma, ARM_HWCAP_A64_FCMA);
-    GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE);
+    GET_FEATURE_ID(sve, ARM_HWCAP_A64_SVE);
 
 #undef GET_FEATURE
 #undef GET_FEATURE_ID
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 850b72a0c7..f927f51fb4 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -10735,7 +10735,7 @@  static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
              * even though the current architectural maximum is VQ=16.
              */
             ret = -TARGET_EINVAL;
-            if (arm_feature(cpu_env, ARM_FEATURE_SVE)
+            if (aa64_feature_sve(arm_env_get_cpu(cpu_env))
                 && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
                 CPUARMState *env = cpu_env;
                 ARMCPU *cpu = arm_env_get_cpu(env);
@@ -10754,9 +10754,11 @@  static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
             return ret;
         case TARGET_PR_SVE_GET_VL:
             ret = -TARGET_EINVAL;
-            if (arm_feature(cpu_env, ARM_FEATURE_SVE)) {
-                CPUARMState *env = cpu_env;
-                ret = ((env->vfp.zcr_el[1] & 0xf) + 1) * 16;
+            {
+                ARMCPU *cpu = arm_env_get_cpu(cpu_env);
+                if (aa64_feature_sve(cpu)) {
+                    ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
+                }
             }
             return ret;
 #endif /* AARCH64 */
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f9830b67f3..8f95de677a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -258,6 +258,8 @@  static void aarch64_max_initfn(Object *obj)
 
         FIELD_DP64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA, 1);
 
+        FIELD_DP64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE, 1);
+
         /* Replicate the same data to the 32-bit id registers.  */
         FIELD_DP32(cpu->id_isar5, ID_ISAR5, AES, 2); /* AES + PMULL */
         FIELD_DP32(cpu->id_isar5, ID_ISAR5, SHA1, 1);
@@ -275,7 +277,6 @@  static void aarch64_max_initfn(Object *obj)
          * present in either.
          */
         set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
-        set_feature(&cpu->env, ARM_FEATURE_SVE);
         /* For usermode -cpu max we can use a larger and more efficient DCZ
          * blocksize since we don't have to follow what the hardware does.
          */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5af89f6d9d..dd3a2c0b8b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5587,7 +5587,7 @@  void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &sctlr);
     }
 
-    if (arm_feature(env, ARM_FEATURE_SVE)) {
+    if (aa64_feature_sve(cpu)) {
         define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
         if (arm_feature(env, ARM_FEATURE_EL2)) {
             define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
@@ -12587,13 +12587,15 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
     uint32_t flags;
 
     if (is_a64(env)) {
+        ARMCPU *cpu = arm_env_get_cpu(env);
+
         *pc = env->pc;
         flags = ARM_TBFLAG_AARCH64_STATE_MASK;
         /* Get control bits for tagged addresses */
         flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
         flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
 
-        if (arm_feature(env, ARM_FEATURE_SVE)) {
+        if (aa64_feature_sve(cpu)) {
             int sve_el = sve_exception_el(env);
             uint32_t zcr_len;
 
@@ -12604,7 +12606,6 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                 zcr_len = 0;
             } else {
                 int current_el = arm_current_el(env);
-                ARMCPU *cpu = arm_env_get_cpu(env);
 
                 zcr_len = cpu->sve_max_vq - 1;
                 if (current_el <= 1) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index d44e891533..8b3ba96889 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -131,9 +131,8 @@  static const VMStateDescription vmstate_iwmmxt = {
 static bool sve_needed(void *opaque)
 {
     ARMCPU *cpu = opaque;
-    CPUARMState *env = &cpu->env;
 
-    return arm_feature(env, ARM_FEATURE_SVE);
+    return aa64_feature_sve(cpu);
 }
 
 /* The first two words of each Zreg is stored in VFP state.  */
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 40575485aa..5527ffb203 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -169,7 +169,7 @@  void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
     cpu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",
                 vfp_get_fpcr(env), vfp_get_fpsr(env));
 
-    if (arm_feature(env, ARM_FEATURE_SVE)) {
+    if (aa64_feature_sve(cpu)) {
         int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */
 
         for (i = 0; i <= FFR_PRED_NUM; i++) {
@@ -13786,7 +13786,7 @@  static void disas_a64_insn(CPUARMState *env, DisasContext *s)
         unallocated_encoding(s);
         break;
     case 0x2:
-        if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) {
+        if (!aa64_dc_feature_sve(s) || !disas_sve(s, insn)) {
             unallocated_encoding(s);
         }
         break;