| Message ID | 20181019015617.22583-3-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Reduce tlb_flush overhead | expand |
On 19/10/2018 03:56, Richard Henderson wrote: > Since QEMU does not implement ASIDs, changes to the ASID must flush the > tlb. However, if the ASID does not change there is no reason to flush. > > In testing a boot of the Ubuntu installer to the first menu, this reduces > the number of flushes by 30%, or nearly 600k instances. > > Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > target/arm/helper.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 24bbde4f76..ed70ac645e 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2709,12 +2709,10 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, > static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - /* 64 bit accesses to the TTBRs can change the ASID and so we > - * must flush the TLB. > - */ > - if (cpreg_field_is_64bit(ri)) { > + /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ > + if (cpreg_field_is_64bit(ri) && > + extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { > ARMCPU *cpu = arm_env_get_cpu(env); > - > tlb_flush(CPU(cpu)); > } > raw_write(env, ri, value); >
On 19 October 2018 at 02:56, Richard Henderson <richard.henderson@linaro.org> wrote: > Since QEMU does not implement ASIDs, changes to the ASID must flush the > tlb. However, if the ASID does not change there is no reason to flush. > > In testing a boot of the Ubuntu installer to the first menu, this reduces > the number of flushes by 30%, or nearly 600k instances. > > Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/helper.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 24bbde4f76..ed70ac645e 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2709,12 +2709,10 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, > static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - /* 64 bit accesses to the TTBRs can change the ASID and so we > - * must flush the TLB. > - */ > - if (cpreg_field_is_64bit(ri)) { > + /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ > + if (cpreg_field_is_64bit(ri) && > + extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { > ARMCPU *cpu = arm_env_get_cpu(env); > - > tlb_flush(CPU(cpu)); > } > raw_write(env, ri, value); > -- > 2.17.2 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index 24bbde4f76..ed70ac645e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2709,12 +2709,10 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* 64 bit accesses to the TTBRs can change the ASID and so we - * must flush the TLB. - */ - if (cpreg_field_is_64bit(ri)) { + /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ + if (cpreg_field_is_64bit(ri) && + extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { ARMCPU *cpu = arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); } raw_write(env, ri, value);