@@ -17,7 +17,7 @@
[Defines]
INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformLibPv660
+ BASE_NAME = ArmPlatformLib
FILE_GUID = 6887500D-32AD-41cd-855E-F8A5D5B0D4D2
MODULE_TYPE = BASE
VERSION_STRING = 1.0
@@ -17,7 +17,7 @@
[Defines]
INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformLibPv660Sec
+ BASE_NAME = ArmPlatformLibSec
FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56
MODULE_TYPE = BASE
VERSION_STRING = 1.0
deleted file mode 100644
@@ -1,58 +0,0 @@
-#/** @file
-#
-# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015, Linaro Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = IoInitDxe
- FILE_GUID = e99c606a-5626-11e5-b09e-bb93f4e4c400
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = IoInitDxeEntry
-
-[Sources.common]
- IoInitDxe.c
- Smmu.c
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
- Silicon/Hisilicon/HisiPkg.dec
-
-[LibraryClasses]
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- DebugLib
- BaseLib
- PcdLib
- CacheMaintenanceLib
- SerdesLib
- PlatformSysCtrlLib
- MemoryAllocationLib
-
-[Guids]
-
-[Protocols]
-
-[Pcd]
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
-
-[Depex]
- TRUE
-
deleted file mode 100644
@@ -1,56 +0,0 @@
-#/** @file
-#
-# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2016, Linaro Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PcieInitDxe
- FILE_GUID = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = PcieInitEntry
-
-[Sources]
- PcieInit.c
- PcieInitLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
- Silicon/Hisilicon/HisiPkg.dec
-
-[LibraryClasses]
- UefiDriverEntryPoint
- UefiBootServicesTableLib
- UefiLib
- BaseLib
- DebugLib
- ArmLib
- TimerLib
- PcdLib
- IoLib
-
-[Protocols]
-
-
-[Pcd]
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
-
-[depex]
- TRUE
-
-
-
deleted file mode 100644
@@ -1,48 +0,0 @@
-/** @file
-*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SasV1InitDxe
- FILE_GUID = 6e673d64-4801-4cbd-a7c0-20a26a9d5919
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = SasV1InitEntry
-
-[Sources.common]
- SasV1Init.c
-
-[Packages]
- MdePkg/MdePkg.dec
- Silicon/Hisilicon/HisiPkg.dec
-
-[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- IoLib
- TimerLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- UefiLib
-
-[Pcd]
-
-[Protocols]
- gPlatformSasProtocolGuid
-
-[Depex]
- TRUE
deleted file mode 100644
@@ -1,57 +0,0 @@
-#/** @file
-#
-# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015, Linaro Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = UnInstallSsdt
- FILE_GUID = E39977F0-20A4-4551-B0ED-BCE246592E78
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = UnInstallSsdtTable
-
-[Sources.common]
- UnInstallAcpiTable.c
-
-[Packages]
- ArmPlatformPkg/ArmPlatformPkg.dec
- MdePkg/MdePkg.dec
- ArmPkg/ArmPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- Silicon/Hisilicon/HisiPkg.dec
-
-[LibraryClasses]
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- DebugLib
- BaseLib
- DxeServicesTableLib
-
-[Guids]
- gEfiAcpiTableGuid
- gEfiAcpi20TableGuid
-
-[Protocols]
- gEfiAcpiTableProtocolGuid
- gEfiAcpiSdtProtocolGuid
- gSataEnableFlagProtocolGuid
-
-[Pcd]
-
-
-[Depex]
- gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiVariableArchProtocolGuid
-
-
deleted file mode 100644
@@ -1,60 +0,0 @@
-## @file
-#
-# ACPI table data and ASL sources required to boot the platform.
-#
-# Copyright (c) 2014, ARM Ltd. All rights reserved.
-# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015, Linaro Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = Pv660AcpiTables
- FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-
-[Sources]
- Dsdt/Dsdt.asl
- Facs.aslc
- Fadt.aslc
- Gtdt.aslc
- Madt.aslc
- Mcfg.aslc
- Iort.asl
- Spcr.aslc
- Dbg2.aslc
- SASSSDT.ASL
- SATASSDT.ASL
-
-[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
-
- Silicon/Hisilicon/HisiPkg.dec
-
-[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
-
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
-
deleted file mode 100644
@@ -1,36 +0,0 @@
-/** @file
-*
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef _SMMU_H_
-#define _SMMU_H_
-
-typedef struct {
- UINTN Base;
- UINTN S2Cbt;
-} SMMU_DEVICE;
-
-EFI_STATUS
-SmmuConfigSwitch (
- SMMU_DEVICE *Smmu
- );
-
-EFI_STATUS
-SmmuEnableTable (
- SMMU_DEVICE *Smmu
- );
-
-
-#endif
-
deleted file mode 100644
@@ -1,93 +0,0 @@
-/** @file
-*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __PCIE_INIT_H__
-#define __PCIE_INIT_H__
-
-#include "PcieInitLib.h"
-#include <Library/DebugLib.h>
-#include <Library/BaseLib.h>
-#include <Library/UefiLib.h>
-
-extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
-
-#define PCIE_LOG_ID 1
-
-#define PCIE_CONFIG_SPACE_SIZE 0x1000 //4k
-#define PCIE_MEMORY_SPACE_SIZE 0x800000 //8M
-#define PCIE_IO_SPACE_SIZE 0x800000 //8M
-#define PCIE_TYPE1_MEM_SIZE (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE)
-
-#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000
-#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0
-#define CONFIG_SPACE_ADDR_LIMIT (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1)
-
-#define PCIE_MEM_BASE_ADDR_LOW (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE)
-#define PCIE_MEM_BASE_ADDR_HIGH 0x0
-#define PCIE_MEM_ADDR_LIMIT (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1)
-
-#define PCIE_IO_BASE_ADDR_LOW (PCIE_MEM_ADDR_LIMIT - 1)
-#define PCIE_IO_BASE_ADDR_HIGH 0x0
-#define PCIE_IO_ADDR_LIMIT (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1)
-
-#define PCIE_INBOUND_BASE 0xD0000000
-
-
-#define PCIE_ALL_DMA_BASE (0x100000000)
-#define PCIE0_ALL_DMA_BASE (PCIE_ALL_DMA_BASE)
-#define PCIE0_ALL_DMA_SIZE (0x8000000)
-#define PCIE0_ALL_BAR01_BASE (0x10000000)
-#define PCIE0_ALL_BAR23_BASE (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE)
-#define PCIE0_ALL_TRANSLATE01_BASE 0x2c0000000 //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR)
-#define PCIE0_ALL_TRANSLATE01_SIZE (PCIE_MAX_AXI_SIZE)
-#define PCIE0_ALL_TRANSLATE23_BASE (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE)
-#define PCIE0_ALL_TRANSLATE23_SIZE (PCIE0_ALL_DMA_SIZE)
-
-
-#define PCIE0_REG_BASE (0xb0070000)
-#define PCIE1_REG_BASE (0xb0080000)
-#define PCIE2_REG_BASE (0xb0090000)
-#define PCIE3_REG_BASE (0xb00a0000)
-
-#define PCIE_BASE_BAR (0xf0000000)
-#define PCIE_BAR_SIZE (0x1000000)
-
-
-#define PCIE_AXI_SIZE (0x1000000)
-#define PCIE0_AXI_BASE (0xb3000000)
-#define PCIE1_AXI_BASE (PCIE0_AXI_BASE + PCIE_AXI_SIZE)
-#define PCIE2_AXI_BASE (PCIE1_AXI_BASE + PCIE_AXI_SIZE)
-#define PCIE3_AXI_BASE (PCIE2_AXI_BASE + PCIE_AXI_SIZE)
-
-//#define PCIE_CONFIG_SPACE_SIZE (0x1000)
-#define PCIE0_CONFIG_BASE (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
-#define PCIE1_CONFIG_BASE (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
-#define PCIE2_CONFIG_BASE (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
-#define PCIE3_CONFIG_BASE (PCIE3_AXI_BASE + PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE)
-
-
-#define PCIE0_TRANSLATE_BASE (0x30000000)
-#define PCIE1_TRANSLATE_BASE (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
-#define PCIE2_TRANSLATE_BASE (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
-#define PCIE3_TRANSLATE_BASE (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
-
-#define PCIE0_BAR_BASE (PCIE0_AXI_BASE)
-#define PCIE1_BAR_BASE (PCIE1_AXI_BASE)
-#define PCIE2_BAR_BASE (PCIE2_AXI_BASE)
-#define PCIE3_BAR_BASE (PCIE3_AXI_BASE)
-
-
-#endif
-
deleted file mode 100644
@@ -1,239 +0,0 @@
-/** @file
-*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __PCIE_INIT_LIB_H__
-#define __PCIE_INIT_LIB_H__
-
-#include <Uefi.h>
-#include <Regs/HisiPcieV1RegOffset.h>
-#include "PcieKernelApi.h"
-
-#define PCIE_AXI_SLAVE_BASE (0xb3000000)
-#define PCIE_MAX_AXI_SIZE (0x1000000)
-#define PCIE_AXI_BASE(port) (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
-#define PCIE_SMMU_BASE (0xb0040000)
-
-
-#define PCIE_DMA_CHANNEL_NUM (2)
-#define PCIE_DMA_RESOURCE_MODE_SIZE (0x40000)
-#define PCIE_DMA_BURST_SIZE (0x80000000)
-
-#define PCIE_ADDR_BASE_OFFSET 0x46C00000
-#define PCIE_ADDR_BASE_HOST_ADDR (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
-#define NP_DDR_BASE_ADDR_HOST 0x236E00000ULL
-
-
-
-#define PCIE_GIC_MSI_ITS_BASE (0xb7010040)
-#define PCIE_INT_BASE (13824)
-#define PCIE_INT_LIMIT (PCIE_INT_BASE + 64)
-
-#define PCIE_NTB_MEM_SIZE (0x1000000)
-#define PCIE_NTB_BAR01_SIZE (0x10000) // 64K
-#define PCIE_NTB_BAR23_SIZE (0x800000) // 8M
-#define PCIE_NTB_BAR45_SIZE (0x800000)
-
-#define PCIE_IATU_END {PCIE_IATU_OUTBOUND,0,0,0}
-#define PCIE_IATU_INBOUND_MASK (0x80000000)
-#define PCIE_IATU_INDEX_MASK (0x7f)
-#define PCIE_IATU_TYPE_MASK (0x1f)
-#define PCIE_IATU_EN (0x1 << 0)
-#define PCIE_IATU_SHIFT_MODE (0x1 << 1)
-#define PCIE_IATU_BAR_MODE (0x1 << 2)
-#define PCIE_IATU_FUNC_MODE (0x1 << 3)
-#define PCIE_IATU_AT_MODE (0x1 << 4)
-#define PCIE_IATU_ATTR_MODE (0x1 << 5)
-#define PCIE_IATU_TD_MODE (0x1 << 6) //TD
-#define PCIE_IATU_TC_MODE (0x1 << 7) // TC
-#define PCIE_IATU_PREFETCH_MODE (0x1 << 8)
-#define PCIE_IATU_DMA_BY_PASS_MODE (0x1 << 9) //DMA bypass untranslate
-
-#define PCIE_BAR_MASK_SIZE (0x800000)
-#define PCIE_BAR_TYPE_32 (0)
-#define PCIE_BAR_TYPE_64 (2)
-#define PCIE_BAR_PREFETCH_MODE (1)
-
-#define RegWrite(addr,data) (*(volatile UINT32*)(UINTN)(addr) = (data))
-#define RegRead(addr,data) ((data) = *(volatile UINT32*)(UINTN)(addr))
-
-
-typedef struct tagPcieDebugInfo
-{
- UINT32 pcie_rdma_start_cnt;
- UINT32 pcie_wdma_start_cnt;
- UINT64 pcie_wdma_transfer_len;
- UINT64 pcie_rdma_transfer_len;
- UINT32 pcie_rdma_fail_cnt;
- UINT32 pcie_wdma_fail_cnt;
-}pcie_debug_info_s;
-
-
-#define bdf_2_b(bdf) ((bdf >> 8) & 0xFF)
-#define bdf_2_d(bdf) ((bdf >> 3) & 0x1F)
-#define bdf_2_f(bdf) ((bdf >> 0) & 0x7)
-#define b_d_f_2_bdf(b,d,f) (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
-
-
-
-typedef UINT32 (*pcie_dma_func_int)(UINT32 ulErrno, UINT32 ulReserved);
-
-
-typedef struct {
- UINT32 ViewPort; //iATU Viewport Register
- UINT32 RegionCtrl1; //Region Control 1 Register
- UINT32 RegionCtrl2; //Region Control 2 Register
- UINT32 BaseLow; //Lower Base Address Register
- UINT32 BaseHigh; //Upper Base Address Register
- UINT32 Limit; //Limit Address Register
- UINT32 TargetLow; //Lower Target Address Register
- UINT32 TargetHigh; //Upper Target Address Register
-} PCIE_IATU_VA;
-
-typedef enum {
- PCIE_IATU_OUTBOUND = 0x0,
- PCIE_IATU_INBOUND = 0x1,
-} PCIE_IATU_DIR;
-
-typedef struct {
- PCIE_IATU_DIR IatuType;
- UINT64 IatuBase;
- UINT64 IatuSize;
- UINT64 IatuTarget;
-} PCIE_IATU;
-
-typedef struct {
- UINT32 IatuType;
- UINT64 IatuBase;
- UINT32 IatuLimit;
- UINT64 IatuTarget;
- UINT32 Valid;
-} PCIE_IATU_HW;
-
-typedef struct {
- UINT32 PortIndex;
- PCIE_PORT_INFO PortInfo;
- PCIE_IATU_HW OutBound[PCIE_MAX_OUTBOUND];
- PCIE_IATU_HW InBound[PCIE_MAX_INBOUND];
-} PCIE_DRIVER_CFG;
-
-typedef enum {
- PCIE_CONFIG_REG = 0x0,
- PCIE_SYS_CONTROL = 0x1,
- PCIE_SLV_CONTENT_MODE = 0x2,
-} PCIE_RW_MODE;
-
-typedef union {
- PCIE_DRIVER_CFG PcieDevice;
- PCIE_NTB_CFG NtbDevice;
-} DRIVER_CFG_U;
-
-typedef struct {
- VOID *MappedOutbound[PCIE_MAX_OUTBOUND];
- UINT32 OutboundType[PCIE_MAX_OUTBOUND];
- UINT32 OutboundEn[PCIE_MAX_OUTBOUND];
-} PCIE_MAPPED_IATU_ADDR;
-
-typedef struct {
- BOOLEAN PortIsInitilized[PCIE_MAX_PORT_NUM];
- DRIVER_CFG_U Dev[PCIE_MAX_PORT_NUM];
- VOID *DmaResource[PCIE_MAX_PORT_NUM];
- UINT32 DmaChannel[PCIE_MAX_PORT_NUM][2];
- VOID *RegResource[PCIE_MAX_PORT_NUM];
- VOID *CfgResource[PCIE_MAX_PORT_NUM];
-} PCIE_INIT_CFG;
-
-typedef enum {
- PCIE_MMIO_IEP_CFG = 0x1000,
- PCIE_MMIO_IEP_CTRL = 0x0,
- PCIE_MMIO_EEP_CFG = 0x9000,
- PCIE_MMIO_EEP_CTRL = 0x8000,
-} NTB_MMIO_MODE;
-
-typedef struct tagPcieDmaDes
-{
- UINT32 uwChanCtrl;
- UINT32 uwLen;
- UINT32 uwLocalLow;
- UINT32 uwLocalHigh;
- UINT32 uwTagetLow;
- UINT32 uwTagetHigh;
-}pcie_dma_des_s,*pcie_dma_des_ps;
-
-typedef enum {
- PCIE_IATU_MEM,
- PCIE_IATU_CFG = 0x4,
- PCIE_IATU_IO
-} PCIE_IATU_OUT_TYPE;
-
-typedef enum {
- PCIE_PAYLOAD_128B = 0,
- PCIE_PAYLOAD_256B,
- PCIE_PAYLOAD_512B,
- PCIE_PAYLOAD_1024B,
- PCIE_PAYLOAD_2048B,
- PCIE_PAYLOAD_4096B,
- PCIE_RESERVED_PAYLOAD
-} PCIE_PAYLOAD_SIZE;
-
-typedef struct tagPcieDfxInfo
-{
- PCIE_EP_AER_CAP0_U aer_cap0;
- PCIE_EP_AER_CAP1_U aer_cap1;
- PCIE_EP_AER_CAP2_U aer_cap2;
- PCIE_EP_AER_CAP3_U aer_cap3;
- PCIE_EP_AER_CAP4_U aer_cap4;
- PCIE_EP_AER_CAP5_U aer_cap5;
- PCIE_EP_AER_CAP6_U aer_cap6;
- UINT32 hdr_log0;
- UINT32 hdr_log1;
- UINT32 hdr_log2;
- UINT32 hdr_log3;
- PCIE_EP_AER_CAP11_U aer_cap11;
- PCIE_EP_AER_CAP12_U aer_cap12;
- PCIE_EP_AER_CAP13_U aer_cap13;
-
- PCIE_EP_PORTLOGIC62_U port_logic62;
- PCIE_EP_PORTLOGIC64_U port_logic64;
- PCIE_EP_PORTLOGIC66_U port_logic66;
- PCIE_EP_PORTLOGIC67_U port_logic67;
- PCIE_EP_PORTLOGIC69_U port_logic69;
- PCIE_EP_PORTLOGIC75_U port_logic75;
- PCIE_EP_PORTLOGIC76_U port_logic76;
- PCIE_EP_PORTLOGIC77_U port_logic77;
- PCIE_EP_PORTLOGIC79_U port_logic79;
- PCIE_EP_PORTLOGIC80_U port_logic80;
- PCIE_EP_PORTLOGIC81_U port_logic81;
- PCIE_EP_PORTLOGIC87_U port_logic87;
-
- PCIE_CTRL_10_U pcie_ctrl10;
- UINT32 slve_rerr_addr_low;
- UINT32 slve_rerr_addr_up;
- UINT32 slve_werr_addr_low;
- UINT32 slve_werr_addr_up;
- UINT32 pcie_state4;
- UINT32 pcie_state5;
-}PCIE_DFX_INFO_S;
-
-VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
-
-UINT32 PcieIsLinkDown(UINT32 Port);
-
-BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port);
-
-EFI_STATUS PcieWaitLinkUp(UINT32 Port);
-
-EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
-
-#endif
deleted file mode 100644
@@ -1,346 +0,0 @@
-/** @file
-*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __PCIE_KERNEL_API_H__
-#define __PCIE_KERNEL_API_H__
-
-#define PCIE_HOST_BRIDGE_NUM (1)
-#define PCIE_MAX_PORT_NUM (4)
-#define PCIE_MAX_OUTBOUND (6)
-#define PCIE_MAX_INBOUND (4)
-#define PCIE3_MAX_OUTBOUND (16)
-#define PCIE3_MAX_INBOUND (16)
-
-#define PCIE_LINK_LOOP_CNT (0x1000)
-#define PCIE_IATU_ADDR_MASK (0xFFFFF000)
-#define PCIE_1M_ALIGN_SHIRFT (20)
-#define PCIE_BDF_MASK (0xF0000FFF)
-#define PCIE_BUS_SHIRFT (20)
-#define PCIE_DEV_SHIRFT (15)
-#define PCIE_FUNC_SHIRFT (12)
-
-#define PCIE_DBI_CS2_ENABLE (0x1)
-#define PCIE_DBI_CS2_DISABLE (0x0)
-
-#define PCIE_DMA_CHANLE_READ (0x1)
-#define PCIE_DMA_CHANLE_WRITE (0x0)
-
-
-#define PCIE_ERR_IATU_TABLE_NULL EFIERR (1)
-#define PCIE_ERR_LINK_OVER_TIME EFIERR (2)
-#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3)
-#define PCIE_ERR_ALREADY_INIT EFIERR (4)
-#define PCIE_ERR_PARAM_INVALID EFIERR (5)
-#define PCIE_ERR_MEM_OPT_OVER EFIERR (6)
-#define PCIE_ERR_NOT_INIT EFIERR (7)
-#define PCIE_ERR_CFG_OPT_OVER EFIERR (8)
-#define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9)
-#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10)
-#define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11)
-#define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12)
-#define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13)
-#define PCIE_ERR_NO_IATU_WINDOW EFIERR (14)
-#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15)
-#define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16)
-#define PCIE_ERR_DMA_ABORT EFIERR (17)
-#define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18)
-
-typedef enum {
- PCIE_ROOT_COMPLEX,
- PCIE_END_POINT,
- PCIE_NTB_TO_NTB,
- PCIE_NTB_TO_RP,
-} PCIE_PORT_TYPE;
-
-typedef enum {
- PCIE_GEN1_0 = 1, //PCIE 1.0
- PCIE_GEN2_0 = 2, //PCIE 2.0
- PCIE_GEN3_0 = 4 //PCIE 3.0
-} PCIE_PORT_GEN;
-
-typedef enum {
- PCIE_WITDH_X1 = 0x1,
- PCIE_WITDH_X2 = 0x3,
- PCIE_WITDH_X4 = 0x7,
- PCIE_WITDH_X8 = 0xf,
- PCIE_WITDH_INVALID
-} PCIE_PORT_WIDTH;
-
-
-typedef struct {
- PCIE_PORT_TYPE PortType;
- PCIE_PORT_WIDTH PortWidth;
- PCIE_PORT_GEN PortGen;
- UINT8 PcieLinkUp;
-} PCIE_PORT_INFO;
-
-typedef struct tagPciecfg_params
-{
- UINT32 preemphasis;
- UINT32 deemphasis;
- UINT32 swing;
- UINT32 balance;
-}pcie_cfg_params_s;
-
-typedef enum {
- PCIE_CORRECTABLE_ERROR = 0,
- PCIE_NON_FATAL_ERROR,
- PCIE_FATAL_ERROR,
- PCIE_UNSUPPORTED_REQUEST_ERROR,
- PCIE_ALL_ERROR
-} PCIE_ERROR_TYPE;
-
-typedef union tagPcieDeviceStatus
-{
- struct
- {
- UINT16 correctable_error : 1;
- UINT16 non_fatal_error : 1;
- UINT16 fatal_error : 1;
- UINT16 unsupported_error : 1;
- UINT16 aux_power : 1;
- UINT16 transaction_pending : 1;
- UINT16 reserved_6_15 : 10;
- }Bits;
-
- UINT16 Value;
-}pcie_device_status_u;
-
-
-typedef union tagPcieUcAerStatus
-{
- struct
- {
- UINT32 undefined : 1 ; /* [0] undefined */
- UINT32 reserved_1_3 : 3 ; /* reserved */
- UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */
- UINT32 reserved_5_11 : 7 ; /* reserved */
- UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */
- UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */
- UINT32 completion_time_out : 1 ; /* Completion Timeout Status */
- UINT32 compler_abort_status : 1 ; /* Completer Abort Status */
- UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */
- UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */
- UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/
- UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */
- UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */
- UINT32 reserved_21 : 1 ; /* reserved */
- UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */
- UINT32 reserved_23 : 1 ; /* reserved*/
- UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */
- UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */
- UINT32 reserved_26_31 : 1 ; /* reserved */
- }Bits;
-
- UINT32 Value;
-}pcie_uc_aer_status_u;
-
-typedef union tagPcieCoAerStatus
-{
- struct
- {
- UINT32 receiver_error_status : 1 ; /* Receiver Error Status */
- UINT32 reserved_1_5 : 5 ; /* Reserved */
- UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */
- UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */
- UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/
- UINT32 reserved_9_11 : 3 ; /* Reserved */
- UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */
- UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/
- UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/
- UINT32 reserved_15_31 : 1 ; /* Reserved */
- }Bits;
- UINT32 Value;
-}pcie_co_aer_status_u;
-
-typedef struct tagPcieAerStatus
-{
- pcie_uc_aer_status_u uc_aer_status;
- pcie_co_aer_status_u co_aer_status;
-}pcie_aer_status_s;
-
-
-
-typedef struct tagPcieLoopTestResult
-{
- UINT32 tx_pkts_cnt;
- UINT32 rx_pkts_cnt;
- UINT32 error_pkts_cnt;
- UINT32 droped_pkts_cnt;
- UINT32 push_cnt;
- pcie_device_status_u device_status;
- pcie_aer_status_s pcie_aer_status;
-} pcie_loop_test_result_s;
-
-typedef struct tagPcieDmaChannelAttrs {
- UINT32 dma_chan_en;
- UINT32 dma_mode;
- UINT32 channel_status;
-}pcie_dma_channel_attrs_s;
-
-typedef enum tagPcieDmaChannelStatus
-{
- PCIE_DMA_CS_RESERVED = 0,
- PCIE_DMA_CS_RUNNING = 1,
- PCIE_DMA_CS_HALTED = 2,
- PCIE_DMA_CS_STOPPED = 3
-}pcie_dma_channel_status_e;
-
-typedef enum tagPcieDmaIntType{
- PCIE_DMA_INT_TYPE_DONE=0,
- PCIE_DMA_INT_TYPE_ABORT,
- PCIE_DMA_INT_ALL,
- PCIE_DMA_INT_NONE
-}pcie_dma_int_type_e;
-
-typedef enum tagPcieMulWinSize
-{
- WIN_SIZE_4K = 0xc,
- WIN_SIZE_8K,
- WIN_SIZE_16K,
- WIN_SIZE_32K,
- WIN_SIZE_64K,
- WIN_SIZE_128K,
- WIN_SIZE_256K,
- WIN_SIZE_512K,
- WIN_SIZE_1M,
- WIN_SIZE_2M,
- WIN_SIZE_4M,
- WIN_SIZE_8M,
- WIN_SIZE_16M,
- WIN_SIZE_32M,
- WIN_SIZE_64M,
- WIN_SIZE_128M,
- WIN_SIZE_256M,
- WIN_SIZE_512M,
- WIN_SIZE_1G,
- WIN_SIZE_2G,
- WIN_SIZE_4G,
- WIN_SIZE_8G,
- WIN_SIZE_16G,
- WIN_SIZE_32G,
- WIN_SIZE_64G,
- WIN_SIZE_128G,
- WIN_SIZE_256G,
- WIN_SIZE_512G = 0x27,
-}pcie_mul_win_size_e;
-
-typedef struct tagPcieMultiCastCfg
-{
- UINT64 multicast_base_addr;
- pcie_mul_win_size_e base_addr_size;
- UINT64 base_translate_addr;
-}pcie_multicast_cfg_s;
-
-typedef enum tagPcieMode
-{
- PCIE_EP_DEVICE = 0x0,
- LEGACY_PCIE_EP_DEVICE = 0x1,
- RP_OF_PCIE_RC = 0x4,
- PCIE_INVALID = 0x100
-}pcie_mode_e;
-
-typedef struct{
- UINT32 PortIndex;
- PCIE_PORT_INFO PortInfo;
- UINT64 iep_bar01; /*iep bar 01*/
- UINT64 iep_bar23;
- UINT64 iep_bar45;
- UINT64 iep_bar01_xlat;
- UINT64 iep_bar23_xlat;
- UINT64 iep_bar45_xlat;
- UINT64 iep_bar_lmt23;
- UINT64 iep_bar_lmt45; /*bar limit*/
- UINT64 eep_bar01;
- UINT64 eep_bar23;
- UINT64 eep_bar45;
- UINT64 eep_bar23_xlat;
- UINT64 eep_bar45_xlat;
- UINT64 eep_bar_lmt23; /*bar limit*/
- UINT64 eep_bar_lmt45; /*bar limit*/
-} PCIE_NTB_CFG;
-
-extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
-
-extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
-
-extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
-
-extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
-
-extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
-
-
-extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
-
-extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
-
-extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
-
-extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
-
-extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
-
-extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
-
-
-extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
-
-extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
-
-
-extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
-
-extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
-
-extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
-
-extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
-
-extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
-
-extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
-
-extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
-
-extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
-extern int pcie_port_reset(UINT32 Port);
-
-extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
-
-extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
-
-extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
-pcie_device_status_u *pcie_stat);
-extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
-
-extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
-extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
-
-extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
-
-
-extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
-
-
-extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
-
-extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
-
-extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
-
-extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
-
-#endif
deleted file mode 100644
@@ -1,30 +0,0 @@
-/*
-# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015, Linaro Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-#ifndef _EFI_UNINSTALL_ACPI_H_
-#define _EFI_UNINSTALL_ACPI_H_
-
-#define EFI_SATA_CONTROL_GUID \
- { \
- 0x287e41a8, 0x5108, 0x4faf, { 0xbe, 0x3d, 0xd4, 0xdd, 0xff, 0xcd, 0x4e, 0x9f } \
- }
-
-#define SATA_ENABLE_FLAG (L"SataEnableFlag")
-#define EFI_SAS_SIGNATURE SIGNATURE_32 ('S', 'A', 'S', '0')
-#define EFI_SATA_SIGNATURE SIGNATURE_32 ('S', 'A', 'T', 'A')
-#define SATAENABLE 1
-#define SATADISABLE 0
-
-
-#endif
deleted file mode 100644
@@ -1,120 +0,0 @@
-/** @file
-*
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-
-#ifndef _SERDES_LIB_H_
-#define _SERDES_LIB_H_
-
-
-typedef enum {
- EmHilink0Pcie1X8 = 0,
- EmHilink0Pcie1X4Pcie2X4 = 1,
-} HILINK0_MODE_TYPE;
-
-typedef enum {
- EmHilink1Pcie0X8 = 0,
- EmHilink1HccsX8 = 1,
-} HILINK1_MODE_TYPE;
-
-typedef enum {
- EmHilink2Pcie2X8 = 0,
- EmHilink2Sas0X8 = 1,
-} HILINK2_MODE_TYPE;
-
-typedef enum {
- EmHilink3GeX4 = 0,
- EmHilink3GeX2XgeX2 = 1, //lane0,lane1-ge,lane2,lane3 xge
-} HILINK3_MODE_TYPE;
-
-
-typedef enum {
- EmHilink4GeX4 = 0,
- EmHilink4XgeX4 = 1,
-} HILINK4_MODE_TYPE;
-
-typedef enum {
- EmHilink5Sas1X4 = 0,
- EmHilink5Pcie3X4 = 1,
-} HILINK5_MODE_TYPE;
-
-
-typedef struct {
- HILINK0_MODE_TYPE Hilink0Mode;
- HILINK1_MODE_TYPE Hilink1Mode;
- HILINK2_MODE_TYPE Hilink2Mode;
- HILINK3_MODE_TYPE Hilink3Mode;
- HILINK4_MODE_TYPE Hilink4Mode;
- HILINK5_MODE_TYPE Hilink5Mode;
-} SERDES_PARAM;
-
-
-#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF
-#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF
-
-typedef struct {
- UINT32 MacroId;
- UINT32 DsNum;
-} SERDES_POLARITY_INVERT;
-
-
-EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
-extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
-extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
-UINT32 GetEthType(UINT8 EthChannel);
-
-EFI_STATUS
-EfiSerdesInitWrap (VOID);
-
-void serdes_state_show(UINT32 macro1);
-//uniBIOS__l00228991_start DTS2015042210118 2015-4-22 20:06:34
-
-void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg);
-//uniBIOS__l00228991_end DTS2015042210118 2015-4-22 20:06:34
-
-//uniBIOS_l00306713_000_start 2015-3-19 17:37:06
-
-//EYE test
-UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData);
-
-UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum);
-
-//PRBS test
-int serdes_prbs_test(UINT8 ulMacroId , UINT8 ulDsNum,UINT8 PrbsType);
-
-int serdes_prbs_test_cancle(UINT8 ulMacroId,UINT8 ulDsNum);
-
-//CTLE/DFE
-void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane);
-
-void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane);
-
-void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane);
-
-void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane);
-
-void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane);
-//uniBIOS_l00306713_000_end 2015-3-19 17:37:06
-
-
-//uniBIOS_l00306713_000_start 2015-7-15 9:13:55
-
-int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val);
-
-int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
-
-int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
-//uniBIOS_l00306713_000_end 2015-7-15 9:13:55
-
-#endif
deleted file mode 100644
@@ -1,48 +0,0 @@
-/** @file
-*
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-
-#ifndef _PV660_PLATFORM_H_
-#define _PV660_PLATFORM_H_
-
-//
-// ACPI table information used to initialize tables.
-//
-#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long
-#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','5',' ',' ',' ') // OEM table id 8 bytes long
-#define EFI_ACPI_ARM_OEM_REVISION 0x00000000
-#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L')
-#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
-
-// A macro to initialise the common header part of EFI ACPI tables as defined by
-// EFI_ACPI_DESCRIPTION_HEADER structure.
-#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
- Signature, /* UINT32 Signature */ \
- sizeof (Type), /* UINT32 Length */ \
- Revision, /* UINT8 Revision */ \
- 0, /* UINT8 Checksum */ \
- { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
- EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
- EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
- EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
- EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
- }
-
-#define PV660_WATCHDOG_COUNT 2
-
-#endif
deleted file mode 100644
@@ -1,94 +0,0 @@
-/** @file
-*
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Library/PlatformSysCtrlLib.h>
-#include <Library/SerdesLib.h>
-
-#include "Smmu.h"
-
-SMMU_DEVICE mSpecialSmmu[] = {
- {FixedPcdGet64 (PcdM3SmmuBaseAddress), 0},
- {FixedPcdGet64 (PcdPcieSmmuBaseAddress), 0},
-};
-
-VOID
-SpecialSmmuConfig (VOID)
-{
- UINTN Index;
-
- for (Index = 0; Index < sizeof (mSpecialSmmu) / sizeof (mSpecialSmmu[0]); Index++) {
- (VOID) SmmuConfigSwitch (&mSpecialSmmu[Index]);
- }
-}
-
-VOID
-SpecialSmmuEnable (VOID)
-{
- UINTN Index;
-
- for (Index = 0; Index < sizeof (mSpecialSmmu) / sizeof (mSpecialSmmu[0]); Index++) {
- (VOID) SmmuEnableTable (&mSpecialSmmu[Index]);
- }
-}
-
-VOID
-EFIAPI
-ExitBootServicesEventSmmu (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- SmmuConfigForOS ();
- SpecialSmmuEnable ();
- DEBUG((EFI_D_ERROR,"SMMU ExitBootServicesEvent\n"));
-}
-
-
-EFI_STATUS
-EFIAPI
-IoInitDxeEntry (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable)
-{
- EFI_STATUS Status;
- EFI_EVENT Event = NULL;
-
- (VOID) EfiSerdesInitWrap ();
-
- SmmuConfigForBios ();
-
- SpecialSmmuConfig ();
-
- Status = gBS->CreateEvent (
- EVT_SIGNAL_EXIT_BOOT_SERVICES,
- TPL_CALLBACK,
- ExitBootServicesEventSmmu,
- NULL,
- &Event
- );
-
- if (EFI_ERROR(Status))
- {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - CreateEvent failed: %r\n", __FUNCTION__,
- __LINE__, Status));
- }
-
- return Status;
-}
-
deleted file mode 100644
@@ -1,442 +0,0 @@
-/** @file
-*
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/TimerLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/ArmLib.h>
-
-#include "Smmu.h"
-
-/* Maximum number of context banks per SMMU */
-#define SMMU_MAX_CBS 256
-
-#ifdef CONFIG_MM_OUTER_SHAREABLE
-#define SH_DOMAIN 2 /* outer shareable */
-#else
-#define SH_DOMAIN 3 /* inner shareable */
-#endif
-
-#define SMMU_OS_VMID 0
-#define SMMU_CB_NUMIRPT 8
-#define SMMU_S1CBT_SIZE 0x10000
-#define SMMU_S2CBT_SIZE 0x2000
-#define SMMU_S1CBT_SHIFT 16
-#define SMMU_S2CBT_SHIFT 12
-
-
-#define SMMU_CTRL_CR0 0x0
-#define SMMU_CTRL_ACR 0x8
-#define SMMU_CFG_S2CTBAR 0xc
-#define SMMU_IDR0 0x10
-#define SMMU_IDR1 0x14
-#define SMMU_IDR2 0x18
-#define SMMU_HIS_GFAR_LOW 0x20
-#define SMMU_HIS_GFAR_HIGH 0x24
-#define SMMU_RINT_GFSR 0x28
-#define SMMU_RINT_GFSYNR 0x2c
-#define SMMU_CFG_GFIM 0x30
-#define SMMU_CFG_CBF 0x34
-#define SMMU_TLBIALL 0x40
-#define SMMU_TLBIVMID 0x44
-#define SMMU_TLBISID 0x48
-#define SMMU_TLBIVA_LOW 0x4c
-#define SMMU_TLBIVA_HIGH 0x50
-#define SMMU_TLBGSYNC 0x54
-#define SMMU_TLBGSTATUS 0x58
-#define SMMU_CXTIALL 0x60
-#define SMMU_CXTIVMID 0x64
-#define SMMU_CXTISID 0x68
-#define SMMU_CXTGSYNC 0x6c
-#define SMMU_CXTGSTATUS 0x70
-#define SMMU_RINT_CB_FSR(n) (0x100 + ((n) << 2))
-#define SMMU_RINT_CB_FSYNR(n) (0x120 + ((n) << 2))
-#define SMMU_HIS_CB_FAR_LOW(n) (0x140 + ((n) << 3))
-#define SMMU_HIS_CB_FAR_HIGH(n) (0x144 + ((n) << 3))
-#define SMMU_CTRL_CB_RESUME(n) (0x180 + ((n) << 2))
-#define SMMU_RINT_CB_FSYNR_MSTID 0x1a0
-
-#define SMMU_CB_S2CR(n) (0x0 + ((n) << 5))
-#define SMMU_CB_CBAR(n) (0x4 + ((n) << 5))
-#define SMMU_CB_S1CTBAR(n) (0x18 + ((n) << 5))
-
-#define SMMU_S1_MAIR0 0x0
-#define SMMU_S1_MAIR1 0x4
-#define SMMU_S1_TTBR0_L 0x8
-#define SMMU_S1_TTBR0_H 0xc
-#define SMMU_S1_TTBR1_L 0x10
-#define SMMU_S1_TTBR1_H 0x14
-#define SMMU_S1_TTBCR 0x18
-#define SMMU_S1_SCTLR 0x1c
-
-#define CFG_CBF_S1_ORGN_WA (1 << 12)
-#define CFG_CBF_S1_IRGN_WA (1 << 10)
-#define CFG_CBF_S1_SHCFG (SH_DOMAIN << 8)
-#define CFG_CBF_S2_ORGN_WA (1 << 4)
-#define CFG_CBF_S2_IRGN_WA (1 << 2)
-#define CFG_CBF_S2_SHCFG (SH_DOMAIN << 0)
-
-/* Configuration registers */
-#define sCR0_CLIENTPD (1 << 0)
-#define sCR0_GFRE (1 << 1)
-#define sCR0_GFIE (1 << 2)
-#define sCR0_GCFGFRE (1 << 4)
-#define sCR0_GCFGFIE (1 << 5)
-
-#define sACR_WC_EN (7 << 0)
-
-#define ID0_S1TS (1 << 30)
-#define ID0_S2TS (1 << 29)
-#define ID0_NTS (1 << 28)
-#define ID0_PTFS_SHIFT 24
-#define ID0_PTFS_MASK 0x2
-#define ID0_PTFS_V8_ONLY 0x2
-#define ID0_CTTW (1 << 14)
-
-#define ID2_OAS_SHIFT 8
-#define ID2_OAS_MASK 0xff
-#define ID2_IAS_SHIFT 0
-#define ID2_IAS_MASK 0xff
-
-#define S2CR_TYPE_SHIFT 16
-#define S2CR_TYPE_MASK 0x3
-#define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
-#define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
-#define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
-#define S2CR_SHCFG_NS (3 << 8)
-#define S2CR_MTCFG (1 << 11)
-#define S2CR_MEMATTR_OIWB (0xf << 12)
-#define S2CR_MTSH_WEAKEST (S2CR_SHCFG_NS | \
- S2CR_MTCFG | S2CR_MEMATTR_OIWB)
-
-/* Context bank attribute registers */
-#define CBAR_VMID_SHIFT 0
-#define CBAR_VMID_MASK 0xff
-#define CBAR_S1_BPSHCFG_SHIFT 8
-#define CBAR_S1_BPSHCFG_MASK 3
-#define CBAR_S1_BPSHCFG_NSH 3
-#define CBAR_S1_MEMATTR_SHIFT 12
-#define CBAR_S1_MEMATTR_MASK 0xf
-#define CBAR_S1_MEMATTR_WB 0xf
-#define CBAR_TYPE_SHIFT 16
-#define CBAR_TYPE_MASK 0x3
-#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
-#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
-#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
-#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
-#define CBAR_IRPTNDX_SHIFT 24
-#define CBAR_IRPTNDX_MASK 0xff
-
-#define SMMU_CB_BASE(smmu) ((smmu)->s1cbt)
-#define SMMU_CB(n) ((n) << 5)
-
-#define sTLBGSTATUS_GSACTIVE (1 << 0)
-#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
-
-#define SCTLR_WACFG_WA (2 << 26)
-#define SCTLR_RACFG_RA (2 << 24)
-#ifdef CONFIG_P660_2P
-#define SCTLR_SHCFG (1 << 22)
-#else
-#define SCTLR_SHCFG (2 << 22)
-#endif
-#define SCTLR_MTCFG (1 << 20)
-#define SCTLR_MEMATTR_WB (0xf << 16)
-#define SCTLR_MEMATTR_NC (0x5 << 16)
-#define SCTLR_MEMATTR_NGNRE (0x1 << 16)
-#define SCTLR_CACHE_WBRAWA (SCTLR_WACFG_WA | SCTLR_RACFG_RA | \
- SCTLR_SHCFG | SCTLR_MTCFG | SCTLR_MEMATTR_WB)
-#define SCTLR_CACHE_NC (SCTLR_SHCFG | \
- SCTLR_MTCFG | SCTLR_MEMATTR_NC)
-#define SCTLR_CACHE_NGNRE (SCTLR_SHCFG | \
- SCTLR_MTCFG | SCTLR_MEMATTR_NGNRE)
-
-#define SCTLR_CFCFG (1 << 7)
-#define SCTLR_CFIE (1 << 6)
-#define SCTLR_CFRE (1 << 5)
-#define SCTLR_E (1 << 4)
-#define SCTLR_AFED (1 << 3)
-#define SCTLR_M (1 << 0)
-#define SCTLR_EAE_SBOP (SCTLR_AFED)
-
-#define RESUME_RETRY (0 << 0)
-#define RESUME_TERMINATE (1 << 0)
-
-#define TTBCR_TG0_4K (0 << 14)
-#define TTBCR_TG0_64K (3 << 14)
-
-#define TTBCR_SH0_SHIFT 12
-#define TTBCR_SH0_MASK 0x3
-#define TTBCR_SH_NS 0
-#define TTBCR_SH_OS 2
-#define TTBCR_SH_IS 3
-#define TTBCR_ORGN0_SHIFT 10
-#define TTBCR_IRGN0_SHIFT 8
-#define TTBCR_RGN_MASK 0x3
-#define TTBCR_RGN_NC 0
-#define TTBCR_RGN_WBWA 1
-#define TTBCR_RGN_WT 2
-#define TTBCR_RGN_WB 3
-#define TTBCR_T1SZ_SHIFT 16
-#define TTBCR_T0SZ_SHIFT 0
-#define TTBCR_SZ_MASK 0xf
-
-#define MAIR_ATTR_SHIFT(n) ((n) << 3)
-#define MAIR_ATTR_MASK 0xff
-#define MAIR_ATTR_DEVICE 0x04
-#define MAIR_ATTR_NC 0x44
-#define MAIR_ATTR_WBRWA 0xff
-#define MAIR_ATTR_IDX_NC 0
-#define MAIR_ATTR_IDX_CACHE 1
-#define MAIR_ATTR_IDX_DEV 2
-
-#define FSR_MULTI (1 << 31)
-#define FSR_EF (1 << 4)
-#define FSR_PF (1 << 3)
-#define FSR_AFF (1 << 2)
-#define FSR_TF (1 << 1)
-#define FSR_IGN (FSR_AFF)
-#define FSR_FAULT (FSR_MULTI | FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
-
-#define FSYNR0_ASID(n) (0xff & ((n) >> 24))
-#define FSYNR0_VMID(n) (0xff & ((n) >> 16))
-#define FSYNR0_WNR (1 << 4)
-#define FSYNR0_SS (1 << 2)
-#define FSYNR0_CF (1 << 0)
-
-#define SMMU_FEAT_COHERENT_WALK (1 << 0)
-#define SMMU_FEAT_STREAM_MATCH (1 << 1)
-#define SMMU_FEAT_TRANS_S1 (1 << 2)
-#define SMMU_FEAT_TRANS_S2 (1 << 3)
-#define SMMU_FEAT_TRANS_NESTED (1 << 4)
-
-static UINT32 hisi_bypass_vmid = 0xff;
-
-VOID writel_relaxed (UINT32 Value, UINTN Base)
-{
- MmioWrite32 (Base, Value);
-}
-
-UINT32 readl_relaxed (UINTN Base)
-{
- return MmioRead32 (Base);
-}
-
-/* Wait for any pending TLB invalidations to complete */
-static void hisi_smmu_tlb_sync(SMMU_DEVICE *smmu)
-{
- int count = 0;
- UINTN gr0_base = smmu->Base;
-
- writel_relaxed(0, gr0_base + SMMU_TLBGSYNC);
- while (readl_relaxed(gr0_base + SMMU_TLBGSTATUS)
- & sTLBGSTATUS_GSACTIVE) {
- if (++count == TLB_LOOP_TIMEOUT) {
- DEBUG ((EFI_D_ERROR, "TLB sync timed out -- SMMU (0x%p) may be deadlocked\n", gr0_base));
- return;
- }
- MicroSecondDelay (1);
- }
-}
-
-
-VOID *
-SmmuAllocateTable (
- UINTN Size,
- UINTN Alignment
- )
-{
- return AllocateAlignedReservedPages (EFI_SIZE_TO_PAGES (Size), Alignment);
-}
-
-
-EFI_STATUS
-SmmuInit (
- SMMU_DEVICE *Smmu
- )
-{
- UINT32 Value;
- UINTN Base = Smmu->Base;
- UINTN Index;
-
- /* Clear Global FSR */
- Value = MmioRead32 (Base + SMMU_RINT_GFSR);
- MmioWrite32 (Base + SMMU_RINT_GFSR, Value);
-
- /* mask all global interrupt */
- MmioWrite32 (Base + SMMU_CFG_GFIM, 0xFFFFFFFF);
-
- Value = CFG_CBF_S1_ORGN_WA | CFG_CBF_S1_IRGN_WA | CFG_CBF_S1_SHCFG;
- Value |= CFG_CBF_S2_ORGN_WA | CFG_CBF_S2_IRGN_WA | CFG_CBF_S2_SHCFG;
- MmioWrite32 (Base + SMMU_CFG_CBF, Value);
-
- /* Clear CB_FSR */
- for (Index = 0; Index < SMMU_CB_NUMIRPT; Index++) {
- MmioWrite32 (Base + SMMU_RINT_CB_FSR(Index), FSR_FAULT);
- }
-
- return EFI_SUCCESS;
-}
-
-VOID *
-SmmuCreateS2Cbt (VOID)
-{
- VOID *Table;
- UINTN Index;
-
- Table = SmmuAllocateTable (SMMU_S2CBT_SIZE, LShiftU64 (1, SMMU_S2CBT_SHIFT));
- if (Table == NULL) {
- DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Allocate table failed!\n", __FUNCTION__, __LINE__));
- return NULL;
- }
- ZeroMem (Table, SMMU_S2CBT_SIZE);
-
- for (Index = 0; Index < SMMU_MAX_CBS; Index++) {
- MmioWrite32 ((UINTN)Table + SMMU_CB_S1CTBAR(Index), 0);
- MmioWrite32 ((UINTN)Table + SMMU_CB_S2CR(Index), S2CR_TYPE_BYPASS);
- }
- return Table;
-}
-
-VOID *
-SmmuCreateS1Cbt (VOID)
-{
- VOID *Table;
-
- Table = SmmuAllocateTable (SMMU_S1CBT_SIZE, LShiftU64 (1, SMMU_S1CBT_SHIFT));
- if (Table == NULL) {
- DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Allocate table failed!\n", __FUNCTION__, __LINE__));
- return NULL;
- }
- ZeroMem (Table, SMMU_S1CBT_SIZE);
-
- return Table;
-}
-
-EFI_STATUS
-SmmuConfigSwitch (
- SMMU_DEVICE *Smmu
- )
-{
- VOID* S2;
- VOID* S1;
- UINT32 reg;
-
- S2 = SmmuCreateS2Cbt ();
- if (S2 == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
- Smmu->S2Cbt = (UINTN) S2;
-
- S1 = SmmuCreateS1Cbt ();
- if (S1 == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID), (UINT32) RShiftU64 ((UINT64)S1, SMMU_S1CBT_SHIFT));
-
- // Force device for VMID 0 ASID 0
- MmioWrite32 ((UINTN)S1 + SMMU_CB(0) + SMMU_S1_SCTLR, SCTLR_CACHE_WBRAWA);
- // Force device for VMID 0 ASID 1
- MmioWrite32 ((UINTN)S1 + SMMU_CB(1) + SMMU_S1_SCTLR, SCTLR_CACHE_NGNRE);
-
- /*
- * Use the weakest attribute, so no impact stage 1 output attribute.
- */
- reg = CBAR_TYPE_S1_TRANS_S2_BYPASS |
- (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
- (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
- MmioWrite32 (Smmu->S2Cbt + SMMU_CB_CBAR(SMMU_OS_VMID), reg);
-
- /* Mark S2CR as translation */
- reg = S2CR_TYPE_TRANS | S2CR_MTSH_WEAKEST;
- MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S2CR(SMMU_OS_VMID), reg);
-
- /* Bypass need use another S2CR */
- reg = S2CR_TYPE_BYPASS;
- MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S2CR(hisi_bypass_vmid), reg);
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-SmmuFlushCbt (
- SMMU_DEVICE *Smmu
- )
-{
- UINTN Index;
-
- if (Smmu->S2Cbt == 0) {
- DEBUG ((EFI_D_ERROR, "[%a]:[%dL] S2Cbt is null!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
-
- WriteBackInvalidateDataCacheRange ((VOID *)Smmu->S2Cbt, SMMU_S2CBT_SIZE);
- for (Index = 0; Index < SMMU_MAX_CBS; Index++) {
- UINTN S1Ctb = MmioRead32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID));
- if (S1Ctb) {
- // TODO: shall we really need to flush 64KB? Or 8KB is enough?
- WriteBackInvalidateDataCacheRange ((VOID *)LShiftU64 (S1Ctb, SMMU_S1CBT_SHIFT), SMMU_S1CBT_SIZE);
- }
- }
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-SmmuEnableTable (
- SMMU_DEVICE *Smmu
- )
-{
- UINT32 reg;
- UINTN gr0_base = Smmu->Base;
-
- (VOID) SmmuFlushCbt (Smmu);
-
- /* Clear Global FSR */
- reg = readl_relaxed(gr0_base + SMMU_RINT_GFSR);
- writel_relaxed(reg, gr0_base + SMMU_RINT_GFSR);
-
- /* unmask all global interrupt */
- writel_relaxed(0, gr0_base + SMMU_CFG_GFIM);
-
- reg = CFG_CBF_S1_ORGN_WA | CFG_CBF_S1_IRGN_WA | CFG_CBF_S1_SHCFG;
- reg |= CFG_CBF_S2_ORGN_WA | CFG_CBF_S2_IRGN_WA | CFG_CBF_S2_SHCFG;
- writel_relaxed(reg, gr0_base + SMMU_CFG_CBF);
-
- reg = (UINT32) RShiftU64 (Smmu->S2Cbt, SMMU_S2CBT_SHIFT);
- writel_relaxed(reg, gr0_base + SMMU_CFG_S2CTBAR);
-
- /* Invalidate all TLB, just in case */
- writel_relaxed(0, gr0_base + SMMU_TLBIALL);
- hisi_smmu_tlb_sync(Smmu);
-
- writel_relaxed(sACR_WC_EN, gr0_base + SMMU_CTRL_ACR);
-
- /* Enable fault reporting */
- reg = (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
- reg &= ~sCR0_CLIENTPD;
-
- writel_relaxed(reg, gr0_base + SMMU_CTRL_CR0);
- ArmDataSynchronizationBarrier ();
-
- return EFI_SUCCESS;
-};
-
deleted file mode 100644
@@ -1,103 +0,0 @@
-/** @file
-*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-
-#include "PcieInit.h"
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/PcdLib.h>
-
-extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
-extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
-extern EFI_STATUS PciePortInit (UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
-
-PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] =
-{
- //Port 0
- {
- 0x0, //Portindex
-
- {
- PCIE_ROOT_COMPLEX, //PortType
- PCIE_WITDH_X8, //PortWidth
- PCIE_GEN3_0, //PortGen
- }, //PortInfo
-
- },
-
- //Port 1
- {
- 0x1, //Portindex
- {
- PCIE_ROOT_COMPLEX, //PortType
- PCIE_WITDH_X8, //PortWidth
- PCIE_GEN3_0, //PortGen
- },
-
- },
-
- //Port 2
- {
- 0x2, //Portindex
- {
- PCIE_ROOT_COMPLEX, //PortType
- PCIE_WITDH_X8, //PortWidth
- PCIE_GEN3_0, //PortGen
- },
-
- },
-
- //Port 3
- {
- 0x3, //Portindex
- {
- PCIE_ROOT_COMPLEX, //PortType
- PCIE_WITDH_X8, //PortWidth
- PCIE_GEN3_0, //PortGen
- },
-
- },
-};
-
-EFI_STATUS
-PcieInitEntry (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-
-{
- UINT32 Port;
- EFI_STATUS Status = EFI_SUCCESS;
- UINT32 HostBridgeNum = 0;
-
- for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++)
- {
- for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++)
- {
- if (!((((PcdGet32(PcdPcieRootBridgeMask) >> (4 * HostBridgeNum))) >> Port) & 0x1))
- {
- continue;
- }
-
- Status = PciePortInit(HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
- if(EFI_ERROR(Status))
- {
- DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
- }
-
- }
- }
-
- return EFI_SUCCESS;
-}
deleted file mode 100644
@@ -1,1048 +0,0 @@
-/** @file
-*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include "PcieInitLib.h"
-#include <Library/DebugLib.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/IoLib.h>
-#include <Library/TimerLib.h>
-
-static PCIE_INIT_CFG mPcieIntCfg;
-UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
-UINT64 pcie_serders_base[2][4] = {{0xB2080000,0xB2000000,0xB2100000,0xB2200000},{BASE_4TB + 0xB2080000,BASE_4TB + 0xB2000000,BASE_4TB + 0xB2100000,BASE_4TB + 0xB2200000}};
-UINT64 io_sub0_base = 0xa0000000;
-UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
-#define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
-UINT32 loop_test_flag[4] = {0,0,0,0};
-UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
-#define PCIE_GEN1 0 /* PCIE 1.0 */
-#define PCIE_GEN2 1 /* PCIE 2.0 */
-#define PCIE_GEN3 2 /* PCIE 3.0 */
-#define DS_API(lane) ((0x1FF6c + 8*(15-lane))*2)
-
-extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
-extern PCIE_IATU gastr_pcie_iatu_cfg;
-extern PCIE_IATU_VA mPcieIatuTable;
-
-VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
-{
- RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
-
-}
-
-UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
-{
- UINT32 Value = 0;
-
- RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
- return Value;
-}
-
-VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
-{
- RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
-}
-
-UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
-{
- UINT32 Value = 0;
- RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
- return Value;
-}
-
-VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
-{
- u_sc_pcie0_clkreq pcie0;
- u_sc_pcie1_clkreq pcie1;
- u_sc_pcie2_clkreq pcie2;
- u_sc_pcie3_clkreq pcie3;
-
- switch(Port)
- {
- case 0:
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
- pcie0.Bits.pcie0_apb_cfg_sel = Mode;
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
- break;
- case 1:
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
- pcie1.Bits.pcie1_apb_cfg_sel = Mode;
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
- break;
- case 2:
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
- pcie2.Bits.pcie2_apb_cfg_sel = Mode;
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
- break;
- case 3:
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
- pcie3.Bits.pcie3_apb_cfg_sel = Mode;
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
- break;
- default:
- break;
- }
-}
-
-
-
-EFI_STATUS PcieEnableItssm(UINT32 HostBridgeNum, UINT32 Port)
-{
- PCIE_CTRL_7_U pcie_ctrl7;
-
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- if(mPcieIntCfg.PortIsInitilized[Port])
- {
- return PCIE_ERR_ALREADY_INIT;
- }
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
-
- pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
- pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
- PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS PcieDisableItssm(UINT32 HostBridgeNum, UINT32 Port)
-{
- PCIE_CTRL_7_U pcie_ctrl7;
-
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return PCIE_ERR_PARAM_INVALID;
- }
-
-
- if(mPcieIntCfg.PortIsInitilized[Port])
- {
- return PCIE_ERR_ALREADY_INIT;
- }
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
-
- pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
- pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
- PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
-
- return EFI_SUCCESS;
-}
-
-
-EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
-{
- PCIE_EP_PCIE_CAP12_U pcie_cap12;
-
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
- pcie_cap12.Bits.targetlinkspeed = Speed;
- PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
-
- if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
- mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
- {
- pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
- pcie_cap12.Bits.targetlinkspeed = Speed;
- PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
- }
- return EFI_SUCCESS;
-}
-
-EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
-{
- PCIE_EP_PORT_LOGIC4_U pcie_logic4;
- PCIE_EP_PORT_LOGIC22_U logic22;
-
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return PCIE_ERR_PARAM_INVALID;
- }
-
- pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
- pcie_logic4.Bits.linkmodeenable = Width;
- pcie_logic4.Bits.crosslinkenable = 0;
- pcie_logic4.Bits.fastlinkmode = 1;
- PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
-
- logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
- logic22.Bits.n_fts = 0xff;
- if(Width == PCIE_WITDH_X1)
- {
- logic22.Bits.pre_determ_num_of_lane = 1;
- }
- else if(Width == PCIE_WITDH_X2)
- {
- logic22.Bits.pre_determ_num_of_lane = 2;
- }
- else
- {
- logic22.Bits.pre_determ_num_of_lane = 3;
- }
- PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
-
- if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
- mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
- {
- pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
- pcie_logic4.Bits.linkmodeenable = Width;
- pcie_logic4.Bits.crosslinkenable = 0;
- pcie_logic4.Bits.fastlinkmode = 1;
- PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
-
- logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
- logic22.Bits.n_fts = 0xff;
- if(Width == PCIE_WITDH_X1)
- {
- logic22.Bits.pre_determ_num_of_lane = 1;
- }
- else if(Width == PCIE_WITDH_X2)
- {
- logic22.Bits.pre_determ_num_of_lane = 2;
- }
- else
- {
- logic22.Bits.pre_determ_num_of_lane = 3;
- }
- PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
- }
- return EFI_SUCCESS;
-}
-
-EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
-{
- PCIE_EP_PORT_LOGIC22_U logic22;
- PCIE_EEP_PCI_CFG_HDR15_U hdr15;
- UINT32 Value = 0;
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
- Value &= ~(0x3f<<16);
-
- if(Width == PCIE_WITDH_X1)
- {
- Value |= (0x1 << 16);
- }
- else if(Width == PCIE_WITDH_X2)
- {
- Value |= (0x3 << 16);
- }
- else if(Width == PCIE_WITDH_X4)
- {
- Value |= (0x7 << 16);
- }
- else if(Width == PCIE_WITDH_X8)
- {
- Value |= (0xf << 16);
- }
- else
- {
- DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
- }
-
- PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
-
- logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
- logic22.UInt32 &= ~(0x1f<<8);
-
- if(Width == PCIE_WITDH_X1)
- {
- logic22.Bits.pre_determ_num_of_lane = 1;
- }
- else if(Width == PCIE_WITDH_X2)
- {
- logic22.Bits.pre_determ_num_of_lane = 2;
- }
- else if(Width == PCIE_WITDH_X4)
- {
- logic22.Bits.pre_determ_num_of_lane = 4;
- }
- else if(Width == PCIE_WITDH_X8)
- {
- logic22.Bits.pre_determ_num_of_lane = 8;
- }
- else
- {
- DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
- }
-
- PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
-
- /* setup RC BARs */
- PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
- PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
-
- /* setup interrupt pins */
- hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
- hdr15.UInt32 &= 0xffff00ff;
- hdr15.UInt32 |= 0x00000100;
- PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
-
- /* setup bus numbers */
- Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
- Value &= 0xff000000;
- Value |= 0x00010100;
- PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
-
- /* setup command register */
- Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
- Value &= 0xffff0000;
- Value |= 0x1|0x2|0x4|0x100;
- PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
-
- return EFI_SUCCESS;
-}
-
-
-EFI_STATUS PcieModeSet(UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
-{
- PCIE_CTRL_0_U str_pcie_ctrl_0;
-
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- if(mPcieIntCfg.PortIsInitilized[Port])
- {
- return PCIE_ERR_ALREADY_INIT;
- }
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
-
- str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
- if(PcieType == PCIE_END_POINT)
- {
- str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
- }
- else
- {
- str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
- }
- PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
-
- return EFI_SUCCESS;
-}
-
-VOID PciePcsInit(UINT32 HostBridgeNum, UINT32 Port)
-{
-
- if(Port<=2)
- {
- RegWrite(pcie_serders_base[HostBridgeNum][Port] + 0xc088, 0x212);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
-
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
- }
- else
-
- {
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
-
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
-
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
- }
-
-}
-
-VOID PcieEqualization(UINT32 Port)
-{
- UINT32 Value;
-
- PcieRegWrite(Port, 0x890, 0x1400);
- PcieRegWrite(Port, 0x894, 0xfd7);
-
- PcieRegWrite(Port, 0x89c, 0x0);
- PcieRegWrite(Port, 0x898, 0xfc00);
- PcieRegWrite(Port, 0x89c, 0x1);
- PcieRegWrite(Port, 0x898, 0xbd00);
- PcieRegWrite(Port, 0x89c, 0x2);
- PcieRegWrite(Port, 0x898, 0xccc0);
- PcieRegWrite(Port, 0x89c, 0x3);
- PcieRegWrite(Port, 0x898, 0x8dc0);
- PcieRegWrite(Port, 0x89c, 0x4);
- PcieRegWrite(Port, 0x898, 0xfc0);
- PcieRegWrite(Port, 0x89c, 0x5);
- PcieRegWrite(Port, 0x898, 0xe46);
- PcieRegWrite(Port, 0x89c, 0x6);
- PcieRegWrite(Port, 0x898, 0xdc8);
- PcieRegWrite(Port, 0x89c, 0x7);
- PcieRegWrite(Port, 0x898, 0xcb46);
- PcieRegWrite(Port, 0x89c, 0x8);
- PcieRegWrite(Port, 0x898, 0x8c07);
- PcieRegWrite(Port, 0x89c, 0x9);
- PcieRegWrite(Port, 0x898, 0xd0b);
- PcieRegWrite(Port, 0x8a8, 0x103ff21);
-
- Value = PcieRegRead(Port, 0x80);
- Value |= 0x80;
- PcieRegWrite(Port, 0x80, Value);
-
- PcieRegWrite(Port, 0x184, 0x44444444);
- PcieRegWrite(Port, 0x188, 0x44444444);
- PcieRegWrite(Port, 0x18c, 0x44444444);
- PcieRegWrite(Port, 0x190, 0x44444444);
-
-}
-
-
-EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port)
-{
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
- {
- (VOID)PcieDisableItssm(HostBridgeNum, Port);
- }
-
- mPcieIntCfg.PortIsInitilized[Port] = FALSE;
- mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
- mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
- mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
- ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
-
- if(Port <= 2)
- {
- RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
- MicroSecondDelay(0x1000);
-
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
- MicroSecondDelay(0x1000);
- }
- else
- {
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
- MicroSecondDelay(0x1000);
-
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
- MicroSecondDelay(0x1000);
- }
- return EFI_SUCCESS;
-}
-
-EFI_STATUS AssertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
-{
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
- {
- (VOID)PcieDisableItssm(HostBridgeNum, Port);
- }
-
- mPcieIntCfg.PortIsInitilized[Port] = FALSE;
- mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
- mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
- mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
- ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
-
- if(Port <= 2)
- {
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
- MicroSecondDelay(0x1000);
- }
- else
- {
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
- MicroSecondDelay(0x1000);
- }
- return EFI_SUCCESS;
-}
-
-EFI_STATUS DeassertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
-{
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
- {
- (VOID)PcieDisableItssm(HostBridgeNum, Port);
- }
-
- mPcieIntCfg.PortIsInitilized[Port] = FALSE;
- mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
- mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
- mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
- ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
-
- if(Port <= 2)
- {
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
- MicroSecondDelay(0x1000);
- }
- else
- {
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
- MicroSecondDelay(0x1000);
- }
- return EFI_SUCCESS;
-}
-
-EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port)
-{
- u_sc_pcie_hilink_pcs_reset_req reset_req;
- UINT32 pcs_local_reset_status;
- UINT32 pcs_local_status_checked;
- UINT32 hilink_reset_status;
- UINT32 hilink_status_checked;
- UINT32 count = 0;
-
- reset_req.UInt32 = 0;
- reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
-
- reset_req.UInt32 = 0;
- reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
- MicroSecondDelay(0x1000);
-
- /* read reset status, make sure pcs is reset */
- do {
- MicroSecondDelay(1000);
- count ++;
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_reset_status);
- pcs_local_status_checked =
- ((pcs_local_reset_status & (1 << Port)) !=
- (1 << Port));
-
- } while ((pcs_local_status_checked) && (count < 1000));
-
- if (pcs_local_status_checked)
- DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n"));
-
- count = 0;
- do {
- MicroSecondDelay(1000);
- count ++;
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
- hilink_status_checked =
- ((hilink_reset_status & (0xff << (Port << 3))) !=
- (0xff << (Port << 3)));
- } while ((hilink_status_checked) && (count < 1000));
-
- if (hilink_status_checked)
- DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n"));
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port)
-{
- u_sc_pcie_hilink_pcs_reset_req reset_req;
- UINT32 pcs_local_status;
- UINT32 pcs_local_status_checked;
- UINT32 hilink_reset_status;
- UINT32 hilink_status_checked;
- UINT32 count = 0;
-
-
- reset_req.UInt32 = 0;
- reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
-
- reset_req.UInt32 = 0;
- reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
- RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
-
- /* read reset status, make sure pcs is deassert */
- do {
- MicroSecondDelay(1000);
- count ++;
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_status);
- pcs_local_status_checked = (pcs_local_status & (1 << Port));
- } while ((pcs_local_status_checked) && (count < 1000));
-
- /* get a timeout error */
- if (pcs_local_status_checked)
- DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
-
- count = 0;
- do {
- MicroSecondDelay(1000);
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
- hilink_status_checked = (hilink_reset_status &
- (0xff << (Port << 3)));
- } while ((hilink_status_checked) && (count < 1000));
-
- if (hilink_status_checked)
- DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
-
- return EFI_SUCCESS;
-}
-
-VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port)
-{
- UINT32 val;
- UINT32 current_speed;
- UINT32 ltssm_state;
- UINT32 timeout = 0;
- UINT32 eq = 0;
- UINT32 loop = 100000;
- U_SC_PCIE0_SYS_STATE4 PcieStat;
-
- while (loop)
- {
- MicroSecondDelay(10);
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
- val = PcieStat.UInt32;
- current_speed = (val >> 6) & 0x3;
- if (current_speed == PCIE_GEN3)
- break;
- loop--;
- }
- if (!loop) {
- DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
- return;
- }
-
- ltssm_state = val & PCIE_LTSSM_STATE_MASK;
- while ((current_speed == PCIE_GEN3) &&
- (ltssm_state != PCIE_LTSSM_LINKUP_STATE) && (timeout < 200)) {
- if ((ltssm_state & 0x30) == 0x20)
- eq = 1;
-
- if ((ltssm_state == 0xd) && (eq == 1))
- {
- MicroSecondDelay(5000);
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
- val = PcieStat.UInt32;
- ltssm_state = val & PCIE_LTSSM_STATE_MASK;
- current_speed = (val >> 6) & 0x3;
- if (ltssm_state == 0xd)
- {
- DEBUG((EFI_D_ERROR, "Do symbol align reset rate %d ltssm 0x%x\n",current_speed, ltssm_state));
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x8000000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x8000000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x8000000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x8000000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x8000000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x8000000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x8000000);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x8000000);
-
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0);
- RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0);
- }
- break;
- }
-
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
- val = PcieStat.UInt32;
- ltssm_state = val & PCIE_LTSSM_STATE_MASK;
- current_speed = (val >> 6) & 0x3;
-
- MicroSecondDelay(1000);
- timeout++;
- }
-
- if (timeout >= 200) {
- DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
- return;
- }
- DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
-}
-
-VOID Gen3DfeEnable(UINT32 HostBridgeNum, UINT32 Port)
-{
- UINT32 val;
- UINT32 lane;
- UINT32 current_speed;
- U_SC_PCIE0_SYS_STATE4 PcieStat;
-
- if (Port == 3)
- return;
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
- val = PcieStat.UInt32;
- current_speed = (val >> 6) & 0x3;
- if (current_speed != PCIE_GEN3)
- return;
- for (lane = 0; lane < 8; lane++)
- RegWrite(pcie_serders_base[HostBridgeNum][Port] + (UINT32)DS_API(lane) + 4, 0x3851);
-
- DEBUG((EFI_D_ERROR, "enable DFE success\n"));
-}
-
-EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
-{
- UINT32 reg_clock_disable;
- UINT32 reg_clock_enable;
- UINT32 reg_clock_status;
- UINT32 clock_status;
- UINT32 clock_status_checked;
- UINT32 clock_ctrl;
- UINT32 count = 0;
-
- if (Port == 3) {
- reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
- reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
- reg_clock_status = PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG;
- } else {
- reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port);
- reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port);
- reg_clock_status = PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(Port);
- }
-
- if (0x1610 == soctype)
- {
- clock_ctrl = 0x7;
- }
- else
- {
- clock_ctrl = 0x3;
- if (Clock)
- RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, clock_ctrl);
- else
- RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, clock_ctrl);
- }
-
- do {
- count ++;
- MicroSecondDelay(1000);
- RegRead(pcie_subctrl_base[HostBridgeNum] + reg_clock_status, clock_status);
- if (Clock)
- clock_status_checked =
- ((clock_status & clock_ctrl) != clock_ctrl);
- else
- clock_status_checked =
- ((clock_status & clock_ctrl) != 0);
- } while ((clock_status_checked) && (count < 1000)); //1S
-
- /* get a timeout error */
- if (clock_status_checked)
- DEBUG((EFI_D_ERROR, "clock operation failed!\n"));
-
- return EFI_SUCCESS;
-}
-
-VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
-{
- UINT32 Value = 0;
-
- if (0x1610 == soctype)
- {
- }
- else
- {
- RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
- Value &= ~(0xf);
- Value |= Spd;
- RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
- return;
- }
- return;
-}
-
-VOID PcieSpdControl(UINT32 HostBridgeNum, UINT32 Port)
-{
- UINT32 Value = 0;;
-
- /* set link width speed control register */
- RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
- /*
- * set the Directed Speed Change field of the Link Width and Speed
- * Change Control register
- */
- Value |= (1 << 17);
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
-}
-
-VOID PcieSetDb2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 enable)
-{
- UINT32 dbi_ctrl;
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
-
- RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
- if (enable)
- dbi_ctrl |= BIT0;
- else
- dbi_ctrl &= ~BIT0;
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
-}
-
-VOID PcieDisabledBar0(UINT32 HostBridgeNum, UINT32 Port)
-{
- PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_ENABLE);
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x10,0);
- PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_DISABLE);
-}
-
-/* Configure vmid/asid table in PCIe host */
-VOID PcieConfigContextP660(UINT32 HostBridgeNum, UINT32 Port)
-{
- UINT32 i = 0;
- UINTN val = 0;;
-
- /*
- * enable to clean vmid and asid tables though apb bus
- * */
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
- RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
- /* enable ar channel */
- val |= PCIE_RD_TAB_SEL | PCIE_RD_TAB_EN;
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
- for (i = 0; i < 0x800; i++)
- PcieRegWrite(Port, i * 4, 0);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
- /* enable aw channel */
- val &= (~PCIE_RD_TAB_SEL);
- val |= PCIE_RD_TAB_EN;
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
-
- /*
- * init vmid and asid tables for all PCIe devices as 0
- * vmid table: 0 ~ 0x3ff, asid table: 0x400 ~ 0x7ff
- */
- for (i = 0; i < 0x800; i++)
- PcieRegWrite(Port, i * 4, 0);
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
-
- RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
- /* disable ar channel */
- val |= PCIE_RD_TAB_SEL;
- val &= (~PCIE_RD_TAB_EN);
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
- /* disable aw channel */
- val &= ((~PCIE_RD_TAB_SEL) & (~PCIE_RD_TAB_EN));
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
-
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL24_REG, 0xb7010040 & 0xffffffff);
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL28_REG, 0);
-
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL16_REG, (1<<12)|(1<<16));
- RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL29_REG, (1<<12));
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);;
-}
-
-EFI_STATUS PcieMaskLinkUpInit(UINT32 HostBridgeNum, UINT32 Port)
-{
- UINT32 Value = 0;
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
- Value = PcieRegRead(Port, 0x1d0);
- Value |= 1 << 12;
- PcieRegWrite(Port,0x1d0, Value);
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
- return EFI_SUCCESS;
-}
-
-BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port)
-{
- UINT32 Value = 0;
- U_SC_PCIE0_SYS_STATE4 PcieStat;
-
- RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
- Value = PcieStat.UInt32;
- if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
- return TRUE;
-
- return FALSE;
-}
-
-VOID PcieWriteOwnConfig(UINT32 Port, UINT32 Offset)
-{
- UINT32 Value = 0;
- Value = PcieRegRead(Port,Offset & (~0x3));
- Value &= 0x0000ffff;
- Value |= 0x06040000;
- PcieRegWrite(Port, Offset & (~0x3), Value);
- return;
-}
-
-EFI_STATUS
-EFIAPI
-PciePortInit (
- IN UINT32 HostBridgeNum,
- IN PCIE_DRIVER_CFG *PcieCfg
- )
-{
- UINT32 Count = 0;
- UINT32 PortIndex = PcieCfg->PortIndex;
- UINT32 Value = 0;
-
-
- if(PortIndex >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- if(mPcieIntCfg.PortIsInitilized[PortIndex])
- {
- return PCIE_ERR_ALREADY_INIT;
- }
-
- mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
-
- /* assert reset signals */
- (VOID)AssertPcieCoreReset(HostBridgeNum, PortIndex);
- (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 0);
- (VOID)AssertPciePcsReset(HostBridgeNum, PortIndex);
-
- /* de-assert phy reset */
- (VOID)DeassertPciePcsReset(HostBridgeNum, PortIndex);
-
- /* de-assert core reset */
- (VOID)DeassertPcieCoreReset(HostBridgeNum, PortIndex);
- (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 1);
-
- do {
- RegRead(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(PortIndex * 0x10000) + 0x8108, Value);
- if (Count == 10) {
- DEBUG((EFI_D_ERROR, "PCIe Failed! PLL Locked: 0x%x\n\n",Value));
- return EFI_NOT_READY;
- }
- Count++;
- MicroSecondDelay(100000);
- } while ((Value & 0x3) == 0);
- Count = 0;
-
- /* initialize phy */
- (VOID)PciePcsInit(HostBridgeNum, PortIndex);
-
- (VOID)PcieModeSet(HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
- (VOID)PcieSpdSet(0x660, HostBridgeNum, PortIndex, 3);
- (VOID)PcieSpdControl(HostBridgeNum, PortIndex);
- /* setup root complex */
- (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
-
- /* Pcie Equalization*/
- (VOID)PcieEqualization(PortIndex);
-
- /* assert LTSSM enable */
- (VOID)PcieEnableItssm(HostBridgeNum, PortIndex);
-
- /*
- * This is a PCS hardware bug, we fix it by resetting
- * PCS symalign module state machine
- */
- (VOID)PcieGen3Config(HostBridgeNum, PortIndex);
- PcieConfigContextP660(HostBridgeNum, PortIndex);
- (VOID)PcieDisabledBar0(HostBridgeNum, PortIndex);
- (VOID)PcieWriteOwnConfig(PortIndex, 0xa);
- /* check if the link is up or not */
- while (!PcieIsLinkUp(HostBridgeNum, PortIndex)) {
- MicroSecondDelay(1000);
- Count++;
- if (Count >= 1000) {
- DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
- return PCIE_ERR_LINK_OVER_TIME;
- }
- }
- DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
-
- /* dfe enable is just for 660 */
- (VOID)Gen3DfeEnable(HostBridgeNum, PortIndex);
-
-
- PcieRegWrite(PortIndex, 0x80c, 0x208FF);
-
- return EFI_SUCCESS;
-}
-
-
-
-
-EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
-{
- PCIE_SYS_CTRL20_U dbi_ro_enable;
-
- if(Port >= PCIE_MAX_PORT_NUM)
- {
- return EFI_INVALID_PARAMETER;
- }
-
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
- dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
- dbi_ro_enable.Bits.ro_sel = Enable;
- PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
- PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
-
- return EFI_SUCCESS;
-
-}
-
-VOID PcieDelay(UINT32 dCount)
-{
- volatile UINT32 *uwCnt = &dCount;
-
- while(*uwCnt > 0)
- {
- *uwCnt = *uwCnt - 1;
- }
-
-}
-
deleted file mode 100644
@@ -1,114 +0,0 @@
-/** @file
-*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/TimerLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-
-#include <Protocol/PlatformSasProtocol.h>
-
-#define SAS0_BASE 0xc0000000
-#define SAS0_RESET 0xa60
-#define SAS0_DISABLE_CLK 0x33c
-#define SAS0_DERESET 0xa64
-#define SAS0_ENABLE_CLK 0x338
-
-#define SAS1_BASE 0xb0000000
-#define SAS1_RESET 0xa18
-#define SAS1_DISABLE_CLK 0x31c
-#define SAS1_DERESET 0xa1c
-#define SAS1_ENABLE_CLK 0x318
-
-#define SAS_RESET_VALUE 0x7ffff
-
-STATIC
-VOID
-SasInit_0 (
- IN PLATFORM_SAS_PROTOCOL *This
-)
-{
- // Apply reset and disable clock
- MmioWrite32(SAS0_BASE + SAS0_RESET, SAS_RESET_VALUE);
- MmioWrite32(SAS0_BASE + SAS0_DISABLE_CLK, SAS_RESET_VALUE);
- // Wait 1ms for reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
- MicroSecondDelay(1000);
- // De-reset and enable clock
- MmioWrite32(SAS0_BASE + SAS0_DERESET, SAS_RESET_VALUE);
- MmioWrite32(SAS0_BASE + SAS0_ENABLE_CLK, SAS_RESET_VALUE);
- // Wait 1ms for de-reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
- MicroSecondDelay(1000);
-}
-
-PLATFORM_SAS_PROTOCOL Sas0 = {
- 0xc1000000,
- SasInit_0
-};
-
-STATIC
-VOID
-SasInit_1 (
- IN PLATFORM_SAS_PROTOCOL *This
-)
-{
- // Apply reset and disable clock
- MmioWrite32(SAS1_BASE + SAS1_RESET, SAS_RESET_VALUE);
- MmioWrite32(SAS1_BASE + SAS1_DISABLE_CLK, SAS_RESET_VALUE);
- // Wait 1ms for reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
- MicroSecondDelay(1000);
- // De-reset and enable clock
- MmioWrite32(SAS1_BASE + SAS1_DERESET, SAS_RESET_VALUE);
- MmioWrite32(SAS1_BASE + SAS1_ENABLE_CLK, SAS_RESET_VALUE);
- // Wait 1ms for de-reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
- MicroSecondDelay(1000);
-}
-
-PLATFORM_SAS_PROTOCOL Sas1 = {
- 0xb1000000,
- SasInit_1
-};
-
-EFI_STATUS
-EFIAPI
-SasV1InitEntry (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_HANDLE Handle;
- EFI_STATUS Status;
-
- Handle = NULL;
- Status = gBS->InstallMultipleProtocolInterfaces(
- &Handle,
- &gPlatformSasProtocolGuid, &Sas0,
- NULL
- );
- if (EFI_ERROR(Status)) {
- return Status;
- }
-
- Handle = NULL;
- Status = gBS->InstallMultipleProtocolInterfaces(
- &Handle,
- &gPlatformSasProtocolGuid, &Sas1,
- NULL
- );
- return Status;
-}
deleted file mode 100644
@@ -1,119 +0,0 @@
-/** @file
-*
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-
-#include <Uefi.h>
-#include <Pi/PiDxeCis.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/PrintLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Protocol/AcpiSystemDescriptionTable.h>
-#include <Protocol/AcpiTable.h>
-#include <IndustryStandard/Acpi.h>
-#include <Uefi/UefiSpec.h>
-#include <Guid/Acpi.h>
-#include "UnInstallAcpiTable.h"
-
-#define EFI_ACPI_MAX_NUM_TABLES 20
-EFI_GUID gSataControlGuid = EFI_SATA_CONTROL_GUID;
-
-EFI_STATUS
-UnInstallSsdtTable (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable)
-{
- EFI_STATUS Status;
- EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol;
- EFI_ACPI_SDT_HEADER *Table;
- EFI_ACPI_TABLE_VERSION TableVersion;
- UINTN TableKey;
- UINTN i;
- EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
- UINT8 DataPtr1 = 2;
- UINTN DataPtr1Size;
- UINT32 SsdtName;
-
- DataPtr1Size = sizeof(DataPtr1);
-
- Status = gRT->GetVariable (
- SATA_ENABLE_FLAG,
- &gSataControlGuid,
- NULL,
- &DataPtr1Size,
- &DataPtr1
- );
- if (!EFI_ERROR (Status)) {
- DEBUG((EFI_D_ERROR,"Get Variable ok\n"));
-
- }
-
- if (SATAENABLE == DataPtr1) {
- Status = gBS->InstallProtocolInterface (
- &ImageHandle,
- &gSataEnableFlagProtocolGuid,
- EFI_NATIVE_INTERFACE,
- NULL
- );
- if (!EFI_ERROR (Status)) {
- DEBUG((EFI_D_ERROR,"Install SataEnableFlag Protocol ok, %r\n",Status));
-
- }
- DEBUG((EFI_D_ERROR, "Current SataEnable Flag is Sata, try to uninstall Sas SSDT table\n"));
- SsdtName = EFI_SAS_SIGNATURE;
- }
- else {
- DEBUG((EFI_D_ERROR, "Current SataEnable Flag is Sas, try to uninstall Sata SSDT table\n"));
- SsdtName = EFI_SATA_SIGNATURE;
- }
-
- //Locate AcpiTableProtocol
- Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
- if (EFI_ERROR (Status)) {
- DEBUG((EFI_D_ERROR,"Unable to locate ACPI table protocol\n"));
- return EFI_ABORTED;
- }
- //
- // Find the Acpi Sdt protocol
- Status = gBS->LocateProtocol(&gEfiAcpiSdtProtocolGuid, NULL, (VOID**) &AcpiTableProtocol);
- if (EFI_ERROR(Status)) {
- DEBUG((EFI_D_ERROR,"Unable to locate ACPI Sdt protocol\n"));
- return EFI_ABORTED;
- }
-
- //
- // Search for SSDT Table and delete the matched SSDT table
- for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) {
- Status = AcpiTableProtocol->GetAcpiTable(i, &Table, &TableVersion, &TableKey);
- if (EFI_ERROR(Status))
- break;
- if (Table->Signature == EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
-
- if(*(UINT64*)Table->OemTableId == SsdtName) {
- Status = AcpiTable->UninstallAcpiTable (AcpiTable, TableKey);
- if (!EFI_ERROR (Status)) {
- DEBUG((EFI_D_ERROR,"Successfully remove the SSDT table\n"));
- return EFI_SUCCESS;
- }
- }
- }
-
- }
- return EFI_SUCCESS;
-
-}
-
-
deleted file mode 100644
@@ -1,94 +0,0 @@
-/** @file
-* Debug Port Table 2 (DBG2)
-*
-* Copyright (c) 2012 - 2014, Linaro Limited. All rights reserved.
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-#include "Pv660Platform.h"
-
-#include <Library/AcpiLib.h>
-#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/DebugPort2Table.h>
-
-#define NUMBER_DEBUG_DEVICE_INFO 1
-#define NUMBER_OF_GENERIC_ADDRESS 1
-#define NAMESPACE_STRING_SIZE 8
-
-#pragma pack(1)
-
-typedef struct {
- EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
- UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
- CHAR8 NamespaceString[NAMESPACE_STRING_SIZE];
-} EFI_ACPI_DBG2_DDI_STRUCT;
-
-typedef struct {
- EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
- EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
-} EFI_ACPI_DEBUG_PORT_2_TABLE;
-
-#pragma pack()
-
-EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
- {
- ARM_ACPI_HEADER(
- EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE,
- EFI_ACPI_DEBUG_PORT_2_TABLE,
- EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
- ),
- OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
- NUMBER_DEBUG_DEVICE_INFO
- },
- {
- {
- {
- EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
- sizeof(EFI_ACPI_DBG2_DDI_STRUCT),
- NUMBER_OF_GENERIC_ADDRESS,
- NAMESPACE_STRING_SIZE,
- OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
- 0, //OemDataLength
- 0, //OemDataOffset
- EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
- EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550,
- {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
- OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),
- OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
- },
- {
- {
- EFI_ACPI_6_1_SYSTEM_MEMORY,
- 32,
- 0,
- EFI_ACPI_6_1_BYTE,
- FixedPcdGet64(PcdSerialRegisterBase)
- }
- },
- {
- 0x1000
- },
- "COM0"
- }
- }
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Dbg2;
deleted file mode 100644
@@ -1,88 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-
-**/
-
-Scope(_SB)
-{
- //
- // A57x16 Processor declaration
- //
- Device(CPU0) {
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- }
- Device(CPU1) {
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- }
- Device(CPU2) {
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- }
- Device(CPU3) {
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- }
- Device(CPU4) {
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- }
- Device(CPU5) {
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- }
- Device(CPU6) {
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- }
- Device(CPU7) {
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- }
- Device(CPU8) {
- Name(_HID, "ACPI0007")
- Name(_UID, 8)
- }
- Device(CPU9) {
- Name(_HID, "ACPI0007")
- Name(_UID, 9)
- }
- Device(CP10) {
- Name(_HID, "ACPI0007")
- Name(_UID, 10)
- }
- Device(CP11) {
- Name(_HID, "ACPI0007")
- Name(_UID, 11)
- }
- Device(CP12) {
- Name(_HID, "ACPI0007")
- Name(_UID, 12)
- }
- Device(CP13) {
- Name(_HID, "ACPI0007")
- Name(_UID, 13)
- }
- Device(CP14) {
- Name(_HID, "ACPI0007")
- Name(_UID, 14)
- }
- Device(CP15) {
- Name(_HID, "ACPI0007")
- Name(_UID, 15)
- }
-}
deleted file mode 100644
@@ -1,38 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-
-**/
-
-Scope(_SB)
-{
- Device(COM0) {
- Name(_HID, "HISI0031") //it is not 16550 compatible
- Name(_CID, "8250dw")
- Name(_UID, Zero)
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0x80300000, 0x1000)
- Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 }
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"clock-frequency", 200000000},
- Package () {"reg-io-width", 4},
- Package () {"reg-shift", 2},
- }
- })
- }
-}
deleted file mode 100644
@@ -1,38 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-Scope(_SB)
-{
- // sysctl dsa
- Device(CTL0) {
- Name(_HID, "HISI0061")
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xC0000000, 0x10000)
- })
- }
- // sysctl pcie
- Device(CTL1) {
- Name(_HID, "HISI0061")
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xB0000000, 0x10000)
- })
- }
- // sysctl peri_c
- Device(CTL2) {
- Name(_HID, "HISI0061")
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0x80000000, 0x10000)
- })
- }
-}
deleted file mode 100644
@@ -1,29 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-
-**/
-
-#include "Pv660Platform.h"
-
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP05 ", EFI_ACPI_ARM_OEM_REVISION) {
- include ("Mbig.asl")
- include ("CPU.asl")
- include ("Com.asl")
- include ("Usb.asl")
- include ("Ctl.asl")
- include ("Hns.asl")
- include ("Pci.asl")
-}
deleted file mode 100644
@@ -1,956 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-Scope(_SB)
-{
- Device (MDIO)
- {
- OperationRegion(CLKR, SystemMemory, 0x80000338, 8)
- Field(CLKR, DWordAcc, NoLock, Preserve) {
- CLKE, 1, // clock enable
- , 31,
- CLKD, 1, // clode disable
- , 31,
- }
- OperationRegion(RSTR, SystemMemory, 0x80000A38, 8)
- Field(RSTR, DWordAcc, NoLock, Preserve) {
- RSTE, 1, // reset
- , 31,
- RSTD, 1, // de-reset
- , 31,
- }
-
- Name(_HID, "HISI0141")
- Name (_CRS, ResourceTemplate (){
- Memory32Fixed (ReadWrite, 0x803c0000 , 0x10000)
- })
-
- Method(_RST, 0, Serialized) {
- Store (0x1, RSTE)
- Sleep (10)
- Store (0x1, CLKD)
- Sleep (10)
- Store (0x1, RSTD)
- Sleep (10)
- Store (0x1, CLKE)
- Sleep (10)
- }
- }
-
- Device (DSF0)
- {
- OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
- H3ST, 1,
- , 31, //RESERVED
- }
- OperationRegion(H4SR, SystemMemory, 0xC0000190, 4)
- Field(H4SR, DWordAcc, NoLock, Preserve) {
- H4ST, 1,
- , 31, //RESERVED
- }
- // DSAF RESET
- OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
- Field(DRER, DWordAcc, NoLock, Preserve) {
- DRTE, 1,
- , 31, //RESERVED
- DRTD, 1,
- , 31, //RESERVED
- }
- // NT RESET
- OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
- Field(NRER, DWordAcc, NoLock, Preserve) {
- NRTE, 1,
- , 31, //RESERVED
- NRTD, 1,
- , 31, //RESERVED
- }
- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
- XRTE, 31,
- , 1, //RESERVED
- XRTD, 31,
- , 1, //RESERVED
- }
-
- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
- GR0E, 30,
- , 2, //RESERVED
- GR0D, 30,
- , 2, //RESERVED
- GR1E, 18,
- , 14, //RESERVED
- GR1D, 18,
- , 14, //RESERVED
- }
- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
- PRTE, 10,
- , 22, //RESERVED
- PRTD, 10,
- , 22, //RESERVED
- }
-
- // RCB PPE COM RESET
- OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
- Field(RRTR, DWordAcc, NoLock, Preserve) {
- RRTE, 1,
- , 31, //RESERVED
- RRTD, 1,
- , 31, //RESERVED
- }
-
- // ROCE
-
- // CPLD LED
-
- // Serdes
- OperationRegion(H4LR, SystemMemory, 0xC2288100, 0x1000)
- Field(H4LR, DWordAcc, NoLock, Preserve) {
- H4L0, 16, // port0
- H4R0, 16, //RESERVED
- Offset (0x400),
- H4L1, 16, // port1
- H4R1, 16, //RESERVED
- Offset (0x800),
- H4L2, 16, // port2
- H4R2, 16, //RESERVED
- Offset (0xc00),
- H4L3, 16, // port3
- H4R3, 16, //RESERVED
- }
- OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
- H3L2, 16, // port4
- , 16, //RESERVED
- Offset (0x400),
- H3L3, 16, // port5
- , 16, //RESERVED
- }
- Name (_HID, "HISI00B1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate (){
- Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
- Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
- {
- 149,150,151,152,153,154,26,27,155,156,157,158,159,160, //[14] ge fifo err 8 / xge 6
- 6,7,8,9,16,17,18,19,22,23,24,25, //[12] rcb com 4*3
- 0,1,2,3,4,5,12,13, //[8] ppe tnl 0-7
- 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, //[21] dsaf event int 3+18
- 161,162,163,164,
- }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
- {
- 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, //[256] sevice rcb 2*128
- 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415,
- 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431,
- 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447,
- 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463,
- 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479,
- 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495,
- 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511,
- 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527,
- 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543,
- 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559,
- 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575,
- }
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"mode", "6port-16rss"},
- Package () {"buf-size", 4096},
- Package () {"desc-num", 1024},
- Package () {"interrupt-parent", Package() {\_SB.MBI1}},
- }
- })
-
- //reset XGE port
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XRST, 2, Serialized) {
- ShiftLeft (0x2082082, Arg0, Local0)
- Or (Local0, 0x1, Local0)
-
- If (LEqual (Arg1, 0)) {
- Store(Local0, XRTE)
- } Else {
- Store(Local0, XRTD)
- }
- }
-
- //reset XGE core
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XCRT, 2, Serialized) {
- ShiftLeft (0x2080, Arg0, Local0)
-
- If (LEqual (Arg1, 0)) {
- Store(Local0, XRTE)
- } Else {
- Store(Local0, XRTD)
- }
- }
-
- //reset GE port
- //Arg0 : GE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(GRST, 2, Serialized) {
- If (LLessEqual (Arg0, 5)) {
- //Service port
- ShiftLeft (0x1041041, Arg0, Local0)
- ShiftLeft (0x1, Arg0, Local1)
-
- If (LEqual (Arg1, 0)) {
- Store(Local1, GR1E)
- Store(Local0, GR0E)
- } Else {
- Store(Local0, GR0D)
- Store(Local1, GR1D)
- }
- }
- }
-
- //reset PPE port
- //Arg0 : PPE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(PRST, 2, Serialized) {
- ShiftLeft (0x1, Arg0, Local0)
- If (LEqual (Arg1, 0)) {
- Store(Local0, PRTE)
- } Else {
- Store(Local0, PRTD)
- }
- }
-
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 2, Serialized) {
- ShiftLeft (Arg1, 10, Local0)
- Switch (ToInteger(Arg0))
- {
- case (0x0){
- Store (H4L0, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local0, H4L0)
- }
- case (0x1){
- Store (H4L1, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local0, H4L1)
- }
- case (0x2){
- Store (H4L2, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local0, H4L2)
- }
- case (0x3){
- Store (H4L3, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local0, H4L3)
- }
- case (0x4){
- Store (H3L2, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local0, H3L2)
- }
- case (0x5){
- Store (H3L3, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local0, H3L3)
- }
- }
- }
-
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
- //Arg1 : port
- //Arg2 : 0 disable, 1 enable
- Method(DRST, 3, Serialized)
- {
- Switch (ToInteger(Arg0))
- {
- //DSAF reset
- case (0x1)
- {
- Store (Arg2, Local0)
- If (LEqual (Local0, 0))
- {
- Store (0x1, DRTE)
- Store (0x1, NRTE)
- Sleep (10)
- Store (0x1, RRTE)
- }
- Else
- {
- Store (0x1, DRTD)
- Store (0x1, NRTD)
- Sleep (10)
- Store (0x1, RRTD)
- }
- }
- //Reset PPE port
- case (0x2)
- {
- Store (Arg1, Local0)
- Store (Arg2, Local1)
- PRST (Local0, Local1)
- }
-
- //Reset XGE core
- case (0x3)
- {
- Store (Arg1, Local0)
- Store (Arg2, Local1)
- XCRT (Local0, Local1)
- }
- //Reset XGE port
- case (0x4)
- {
- Store (Arg1, Local0)
- Store (Arg2, Local1)
- XRST (Local0, Local1)
- }
-
- //Reset GE port
- case (0x5)
- {
- Store (Arg1, Local0)
- Store (Arg2, Local1)
- GRST (Local0, Local1)
- }
- }
- }
-
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
- // Arg3[1] : port index in dsaf
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : port
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : port
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : port index in dsaf
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : port index in dsaf
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
- If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
- {
- If (LEqual (Arg1, 0x00))
- {
- Switch (ToInteger(Arg2))
- {
- case (0x0)
- {
- Return (Buffer () {0x3F})
- }
-
- //Reset Sequence
- case (0x1)
- {
- Store (DeRefOf (Index (Arg3, 0)), Local0)
- Store (DeRefOf (Index (Arg3, 1)), Local1)
- Store (DeRefOf (Index (Arg3, 2)), Local2)
- DRST (Local0, Local1, Local2)
- }
-
- //Set Serdes Loopback
- case (0x2)
- {
- Store (DeRefOf (Index (Arg3, 0)), Local0)
- Store (DeRefOf (Index (Arg3, 1)), Local1)
- SRLP (Local0, Local1)
- }
-
- //LED op set
- case (0x3)
- {
-
- }
-
- // Get port type (GE or XGE)
- case (0x4)
- {
- Store (0, Local1)
- Store (DeRefOf (Index (Arg3, 0)), Local0)
- If (LLessEqual (Local0, 3))
- {
- Store (H4ST, Local1)
- }
- ElseIf (LLessEqual (Local0, 5))
- {
- Store (H3ST, Local1)
- }
-
- Return (Local1)
- }
-
- //Get sfp status
- case (0x5)
- {
-
- }
- }
- }
- }
- Return (Buffer() {0x00})
- }
- Device (PRT0)
- {
- Name (_ADR, 0x0)
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"reg", 0},
- Package () {"media-type", "fiber"},
- }
- })
- }
- Device (PRT1)
- {
- Name (_ADR, 0x1)
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"reg", 1},
- Package () {"media-type", "fiber"},
- }
- })
- }
- Device (PRT4)
- {
- Name (_ADR, 0x4)
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"reg", 4},
- Package () {"phy-mode", "sgmii"},
- Package () {"phy-addr", 0},
- Package () {"mdio-node", Package (){\_SB.MDIO}},
- Package () {"media-type", "copper"},
- }
- })
- }
- Device (PRT5)
- {
- Name (_ADR, 0x5)
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"reg", 5},
- Package () {"phy-mode", "sgmii"},
- Package () {"phy-addr", 1},
- Package () {"mdio-node", Package (){\_SB.MDIO}},
- Package () {"media-type", "copper"},
- }
- })
- }
- }
-/*
- Device (DSF1)
- {
- OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
- H3ST, 1,
- , 31, //RESERVED
- }
-
- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
- XRTE, 31,
- , 1, //RESERVED
- XRTD, 31,
- , 1, //RESERVED
- }
-
- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
- GR0E, 30,
- , 2, //RESERVED
- GR0D, 30,
- , 2, //RESERVED
- GR1E, 18,
- , 14, //RESERVED
- GR1D, 18,
- , 14, //RESERVED
- }
-
- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
- PRTE, 10,
- , 22, //RESERVED
- PRTD, 10,
- , 22, //RESERVED
- }
-
- // ROCE
-
- // CPLD LED
-
- // Serdes
- OperationRegion(H3LR, SystemMemory, 0xC2208100, 0x4)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
- H3L0, 16, // debug port0
- , 16, //RESERVED
- }
- Name(_HID, "HISI00B1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate (){
- Memory32Fixed (ReadWrite, 0xc2000000 , 0x890000)
-
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
- {
- 14, 15,
- }
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"mode", "single-port"},
- Package () {"buf-size", 4096},
- Package () {"desc-num", 1024},
- Package () {"interrupt-parent", Package() {\_SB.MBI1}},
- }
- })
-
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 1, Serialized) {
- ShiftLeft (Arg0, 10, Local0)
- Store (H3L0, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local1, H3L0)
- }
-
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
- //Arg1 : 0 disable, 1 enable
- Method(DRST, 2, Serialized)
- {
- Switch (ToInteger(Arg0))
- {
- //DSAF reset
- case (0x1)
- {
- If (LEqual (Arg1, 0)) {
- Store (0x100, PRTE)
- } Else {
- Store (0x100, PRTD)
- }
- }
- //Reset PPE port
- case (0x2)
- {
- If (LEqual (Arg1, 0)) {
- Store(0x40, PRTE)
- } Else {
- Store(0x40, PRTD)
- }
- }
-
- //Reset GE port
- case (0x5)
- {
- If (LEqual (Arg1, 0)) {
- Store(0x15540, GR1E)
- Store(0x100, PRTE)
- } Else {
- Store(0x15540, GR1D)
- Store(0x100, PRTD)
- }
- }
- }
- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
- // Arg3[1] : reserved
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : reserved
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : reserved
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : reserved
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : reserved
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
- If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
- {
- If (LEqual (Arg1, 0x00))
- {
- Switch (ToInteger(Arg2))
- {
- case (0x0)
- {
- Return (Buffer () {0x3F})
- }
-
- //Reset Sequence
- case (0x1)
- {
- Store (DeRefOf (Index (Arg3, 0)), Local0)
- Store (DeRefOf (Index (Arg3, 2)), Local2)
- DRST (Local0, Local2)
- }
-
- //Set Serdes Loopback
- case (0x2)
- {
- Store (DeRefOf (Index (Arg3, 2)), Local0)
- SRLP (Local0)
- }
-
- //LED op set
- case (0x3)
- {
-
- }
-
- // Get port type (GE or XGE)
- case (0x4)
- {
- Store (H3ST, Local0)
- Return (Local0)
- }
-
- //Get sfp status
- case (0x5)
- {
-
- }
- }
- }
- }
- Return (Buffer() {0x00})
- }
-
- Device (PRT0)
- {
- Name (_ADR, 0x0)
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"reg", 0},
- Package () {"phy-mode", "sgmii"},
- Package () {"phy-addr", 0},
- Package () {"mdio-node", Package (){\_SB.MDIO}},
- }
- })
- }
- }
- Device (DSF2)
- {
- OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
- H3ST, 1,
- , 31, //RESERVED
- }
-
- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
- XRTE, 31,
- , 1, //RESERVED
- XRTD, 31,
- , 1, //RESERVED
- }
-
- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
- GR0E, 30,
- , 2, //RESERVED
- GR0D, 30,
- , 2, //RESERVED
- GR1E, 18,
- , 14, //RESERVED
- GR1D, 18,
- , 14, //RESERVED
- }
-
- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
- PRTE, 10,
- , 22, //RESERVED
- PRTD, 10,
- , 22, //RESERVED
- }
-
- // ROCE
-
- // CPLD LED
-
- // Serdes
- OperationRegion(H3LR, SystemMemory, 0xC2208500, 0x4)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
- H3L1, 16, // debug port1
- , 16, //RESERVED
- }
- Name(_HID, "HISI00B1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate (){
- Memory32Fixed (ReadWrite, 0xc2100000 , 0x890000)
-
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
- {
- 20, 21,
- }
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"mode", "single-port"},
- Package () {"buf-size", 4096},
- Package () {"desc-num", 1024},
- Package () {"interrupt-parent", Package() {\_SB.MBI1}},
- }
- })
-
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 1, Serialized) {
- ShiftLeft (Arg0, 10, Local0)
- Store (H3L1, Local1)
- And (Local1, 0xfffffbff, Local1)
- Or (Local0, Local1, Local0)
- Store (Local1, H3L1)
- }
-
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
- //Arg1 : 0 disable, 1 enable
- Method(DRST, 2, Serialized)
- {
- Switch (ToInteger(Arg0))
- {
- //DSAF reset
- case (0x1)
- {
- If (LEqual (Arg1, 0)) {
- Store (0x200, PRTE)
- } Else {
- Store (0x2200, PRTD)
- }
- }
-
- //Reset PPE port
- case (0x2)
- {
- If (LEqual (Arg1, 0)) {
- Store(0x80, PRTE)
- } Else {
- Store(0x80, PRTD)
- }
- }
-
- //Reset GE port
- case (0x5)
- {
- If (LEqual (Arg1, 0)) {
- Store(0x2aa80, GR1E)
- Store(0x200, PRTE)
- } Else {
- Store(0x2aa80, GR1D)
- Store(0x200, PRTD)
- }
- }
- }
- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
- // Arg3[1] : reserved
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : reserved
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : reserved
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : reserved
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : reserved
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
- If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
- {
- If (LEqual (Arg1, 0x00))
- {
- Switch (ToInteger(Arg2))
- {
- case (0x0)
- {
- Return (Buffer () {0x3F})
- }
-
- //Reset Sequence
- case (0x1)
- {
- Store (DeRefOf (Index (Arg3, 0)), Local0)
- Store (DeRefOf (Index (Arg3, 2)), Local2)
- DRST (Local0, Local2)
- }
-
- //Set Serdes Loopback
- case (0x2)
- {
- Store (DeRefOf (Index (Arg3, 2)), Local0)
- SRLP (Local0)
- }
-
- //LED op set
- case (0x3)
- {
-
- }
-
- // Get port type (GE or XGE)
- case (0x4)
- {
- Store (H3ST, Local0)
- Return (Local0)
- }
-
- //Get sfp status
- case (0x5)
- {
-
- }
- }
- }
- }
- Return (Buffer() {0x00})
- }
-
- Device (PRT0)
- {
- Name (_ADR, 0x0)
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"reg", 0},
- Package () {"phy-mode", "sgmii"},
- Package () {"phy-addr", 1},
- Package () {"mdio-node", Package (){\_SB.MDIO}},
- }
- })
- }
- }
-*/
- Device (ETH5) {
- Name(_HID, "HISI00C1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
- Package () {"ae-handle", Package (){\_SB.DSF0}},
- Package () {"port-idx-in-ae", 5},
- }
- })
- }
- Device (ETH4) {
- Name(_HID, "HISI00C1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
- Package () {"ae-handle", Package (){\_SB.DSF0}},
- Package () {"port-idx-in-ae", 4},
- }
- })
- }
- Device (ETH0) {
- Name(_HID, "HISI00C1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
- Package () {"ae-handle", Package (){\_SB.DSF0}},
- Package () {"port-idx-in-ae", 0},
- }
- })
- }
- Device (ETH1) {
- Name(_HID, "HISI00C1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
- Package () {"ae-handle", Package (){\_SB.DSF0}},
- Package () {"port-idx-in-ae", 1},
- }
- })
- }
-
-}
deleted file mode 100644
@@ -1,86 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-Scope(_SB)
-{
- // Mbi-gen totem
- Device(MBI0) {
- Name(_HID, "HISI0151")
- Name(_CID, "MBIGen")
- Name(_UID, 0)
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0x8c030000, 0x10000)
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package ()
- {
- Package () {"num-pins", 256}
- }
- })
- }
-
- // mbi-gen dsa
- Device(MBI1) {
- Name(_HID, "HISI0151")
- Name(_CID, "MBIGen")
- Name(_UID, 1)
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xc6030000, 0x10000)
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package ()
- {
- Package () {"num-pins", 640}
- }
- })
- }
-
- // mbi-gen m3
- Device(MBI2) {
- Name(_HID, "HISI0151")
- Name(_CID, "MBIGen")
- Name(_UID, 2)
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xa3030000, 0x10000)
- })
-
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package ()
- {
- Package () {"num-pins", 256}
- }
- })
- }
-
- // mbi-gen pcie
- Device(MBI3) {
- Name(_HID, "HISI0151")
- Name(_CID, "MBIGen")
- Name(_UID, 3)
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xb7030000, 0x10000)
- })
-
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package ()
- {
- Package () {"num-pins", 640}
- }
- })
- }
-}
deleted file mode 100644
@@ -1,181 +0,0 @@
-/** @file
-*
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-Scope(_SB)
-{
- // PCIe Root bus
- Device (PCI1)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 1) // Segment of this Root complex
- Name(_BBN, 64) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
- Name (RBUF, ResourceTemplate () {
- WordBusNumber ( // Bus numbers assigned to this root
- ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0, // AddressGranularity
- 64, // AddressMinimum - Minimum Bus Number
- 127, // AddressMaximum - Maximum Bus Number
- 0, // AddressTranslation - Set to 0
- 64 // RangeLength - Number of Busses
- )
- QWordMemory ( // 64-bit BAR Windows
- ResourceProducer,
- PosDecode,
- MinFixed,
- MaxFixed,
- Cacheable,
- ReadWrite,
- 0x0000000000000000, // Granularity
- 0x00000000b0000000, // Min Base Address pci address
- 0x00000000b7feffff, // Max Base Address
- 0x0000021f58000000, // Translate
- 0x0000000007ff0000 // Length
- )
- QWordIO (
- ResourceProducer,
- MinFixed,
- MaxFixed,
- PosDecode,
- EntireRange,
- 0x0000000000000000, // Granularity
- 0x0000000000000000, // Min Base Address
- 0x000000000000ffff, // Max Base Address
- 0x000002200fff0000, // Translate
- 0x0000000000010000 // Length
- )
- }) // Name(RBUF)
- Return (RBUF)
- } // Method(_CRS)
-
- Device (RES1)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CRS, ResourceTemplate (){
- Memory32Fixed (ReadWrite, 0xb0080000 , 0x10000)
- })
- }
-
- OperationRegion(SCTR, SystemMemory, 0xb0006918, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
- LSTA, 32,
- }
- Method(_DSM, 0x4, Serialized) {
- If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
-
- switch(ToInteger(Arg2))
- {
- // Function 0: Return LinkStatus
- case(0) {
- Store (0, Local0)
- Store (LSTA, Local0)
- Return (Local0)
- }
- default {
- }
- }
- }
- // If not one of the function identifiers we recognize, then return a buffer
- // with bit 0 set to 0 indicating no functions supported.
- return(Buffer(){0})
- }
- } // Device(PCI1)
-
- // PCIe Root bus
- Device (PCI2)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 2) // Segment of this Root complex
- Name(_BBN, 128) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
- Name (RBUF, ResourceTemplate () {
- WordBusNumber ( // Bus numbers assigned to this root
- ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0, // AddressGranularity
- 128, // AddressMinimum - Minimum Bus Number
- 191, // AddressMaximum - Maximum Bus Number
- 0, // AddressTranslation - Set to 0
- 64 // RangeLength - Number of Busses
- )
- QWordMemory ( // 64-bit BAR Windows
- ResourceProducer,
- PosDecode,
- MinFixed,
- MaxFixed,
- Cacheable,
- ReadWrite,
- 0x0000000000000000, // Granularity
- 0x00000000c0000000, // Min Base Address
- 0x00000000c3feffff, // Max Base Address
- 0x0000023f4c000000, // Translate
- 0x0000000003ff0000 // Length
- )
- QWordIO (
- ResourceProducer,
- MinFixed,
- MaxFixed,
- PosDecode,
- EntireRange,
- 0x0000000000000000, // Granularity
- 0x0000000000000000, // Min Base Address
- 0x000000000000ffff, // Max Base Address
- 0x000002400fff0000, // Translate
- 0x0000000000010000 // Length
- )
- }) // Name(RBUF)
- Return (RBUF)
- } // Method(_CRS)
-
- Device (RES2)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CRS, ResourceTemplate (){
- Memory32Fixed (ReadWrite, 0xb0090000 , 0x10000)
- })
- }
-
- OperationRegion(SCTR, SystemMemory, 0xb0006a18, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
- LSTA, 32,
- }
- Method(_DSM, 0x4, Serialized) {
- If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949")))
- {
- switch(ToInteger(Arg2))
- {
- // Function 0: Return LinkStatus
- case(0) {
- Store (0, Local0)
- Store (LSTA, Local0)
- Return (Local0)
- }
- default {
- }
- }
- }
- // If not one of the function identifiers we recognize, then return a buffer
- // with bit 0 set to 0 indicating no functions supported.
- return(Buffer(){0})
- }
- } // Device(PCI2)
-}
-
deleted file mode 100644
@@ -1,136 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-
-**/
-
-//#include "ArmPlatform.h"
-Scope(_SB)
-{
- Device (USB0)
- {
- Name (_HID, "PNP0D20") // _HID: Hardware ID
- Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID
- Name (_CCA, One) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
- {
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite,
- 0xA1000000, // Address Base
- 0x00010000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 0x00000014,
- }
- })
- Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
- }
-
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package ()
- {
- Package () {"interrupt-parent",Package() {\_SB.MBI2}}
- }
- })
-
- Device (RHUB)
- {
- Name (_ADR, Zero) // _ADR: Address
- Device (PRT1)
- {
- Name (_ADR, One) // _ADR: Address
- Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
- {
- 0xFF,
- Zero,
- Zero,
- Zero
- })
- Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
- {
- ToPLD (
- PLD_Revision = 0x1,
- PLD_IgnoreColor = 0x1,
- PLD_Red = 0x0,
- PLD_Green = 0x0,
- PLD_Blue = 0x0,
- PLD_Width = 0x0,
- PLD_Height = 0x0,
- PLD_UserVisible = 0x1,
- PLD_Dock = 0x0,
- PLD_Lid = 0x0,
- PLD_Panel = "UNKNOWN",
- PLD_VerticalPosition = "UPPER",
- PLD_HorizontalPosition = "LEFT",
- PLD_Shape = "UNKNOWN",
- PLD_GroupOrientation = 0x0,
- PLD_GroupToken = 0x0,
- PLD_GroupPosition = 0x0,
- PLD_Bay = 0x0,
- PLD_Ejectable = 0x0,
- PLD_EjectRequired = 0x0,
- PLD_CabinetNumber = 0x0,
- PLD_CardCageNumber = 0x0,
- PLD_Reference = 0x0,
- PLD_Rotation = 0x0,
- PLD_Order = 0x0,
- PLD_VerticalOffset = 0x0,
- PLD_HorizontalOffset = 0x0)
-
- })
- }
-
- Device (PRT2)
- {
- Name (_ADR, 0x02) // _ADR: Address
- Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
- {
- Zero,
- 0xFF,
- Zero,
- Zero
- })
- }
-
- Device (PRT3)
- {
- Name (_ADR, 0x03) // _ADR: Address
- Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
- {
- Zero,
- 0xFF,
- Zero,
- Zero
- })
- }
-
- Device (PRT4)
- {
- Name (_ADR, 0x04) // _ADR: Address
- Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
- {
- Zero,
- 0xFF,
- Zero,
- Zero
- })
- }
- }
- }
-}
-
deleted file mode 100644
@@ -1,67 +0,0 @@
-/** @file
-* Firmware ACPI Control Structure (FACS)
-*
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-#include <IndustryStandard/Acpi.h>
-
-EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
- EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
- sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
- 0xA152, // UINT32 HardwareSignature
- 0, // UINT32 FirmwareWakingVector
- 0, // UINT32 GlobalLock
- 0, // UINT32 Flags
- 0, // UINT64 XFirmwareWakingVector
- EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]
- EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
- 0, // UINT32 OspmFlags "Platform firmware must
- // initialize this field to zero."
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]
- EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Facs;
-
deleted file mode 100644
@@ -1,93 +0,0 @@
-/** @file
-* Fixed ACPI Description Table (FADT)
-*
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-//#include "ArmPlatform.h"
-#include "Pv660Platform.h"
-
-#include <Library/AcpiLib.h>
-#include <IndustryStandard/Acpi.h>
-
-EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
- ARM_ACPI_HEADER (
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
- ),
- 0, // UINT32 FirmwareCtrl
- 0, // UINT32 Dsdt
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
- EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
- 0, // UINT16 SciInt
- 0, // UINT32 SmiCmd
- 0, // UINT8 AcpiEnable
- 0, // UINT8 AcpiDisable
- 0, // UINT8 S4BiosReq
- 0, // UINT8 PstateCnt
- 0, // UINT32 Pm1aEvtBlk
- 0, // UINT32 Pm1bEvtBlk
- 0, // UINT32 Pm1aCntBlk
- 0, // UINT32 Pm1bCntBlk
- 0, // UINT32 Pm2CntBlk
- 0, // UINT32 PmTmrBlk
- 0, // UINT32 Gpe0Blk
- 0, // UINT32 Gpe1Blk
- 0, // UINT8 Pm1EvtLen
- 0, // UINT8 Pm1CntLen
- 0, // UINT8 Pm2CntLen
- 0, // UINT8 PmTmrLen
- 0, // UINT8 Gpe0BlkLen
- 0, // UINT8 Gpe1BlkLen
- 0, // UINT8 Gpe1Base
- 0, // UINT8 CstCnt
- 0, // UINT16 PLvl2Lat
- 0, // UINT16 PLvl3Lat
- 0, // UINT16 FlushSize
- 0, // UINT16 FlushStride
- 0, // UINT8 DutyOffset
- 0, // UINT8 DutyWidth
- 0, // UINT8 DayAlrm
- 0, // UINT8 MonAlrm
- 0, // UINT8 Century
- 0, // UINT16 IaPcBootArch
- 0, // UINT8 Reserved1
- EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg
- 0, // UINT8 ResetValue
- EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
- 0, // UINT64 XFirmwareCtrl
- 0, // UINT64 XDsdt
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
- 0, // UINT64 Hypervisor Vendor Identify
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Fadt;
deleted file mode 100644
@@ -1,96 +0,0 @@
-/** @file
-* Generic Timer Description Table (GTDT)
-*
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-#include "Pv660Platform.h"
-
-#include <Library/AcpiLib.h>
-#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
-
-#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
-#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
-#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
-#define GTDT_GLOBAL_FLAGS_LEVEL 0
-
-// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
-#ifdef SYSTEM_TIMER_BASE_ADDRESS
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
-#else
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
- #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
-#endif
-
-#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
-#define GTDT_TIMER_LEVEL_TRIGGERED 0
-#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
-#define GTDT_TIMER_ACTIVE_HIGH 0
-
-#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
-
-#pragma pack (1)
-
-typedef struct {
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[PV660_WATCHDOG_COUNT];
-} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;
-
-#pragma pack ()
-
-EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
- {
- ARM_ACPI_HEADER(
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES,
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
- ),
- SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
- 0, // UINT32 Reserved
- FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
- FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
- 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
-#ifdef notyet
- PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
- sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
- },
- {
- EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
- //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
- 0, 0, 0, 0),
- EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
- //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
- 0, 0, 0, 0)
- }
-#else /* !notyet */
- 0, 0
- }
-#endif
- };
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Gtdt;
-
deleted file mode 100644
@@ -1,274 +0,0 @@
-/*
- * Intel ACPI Component Architecture
- * iASL Compiler/Disassembler version 20151124-64
- * Copyright (c) 2000 - 2015 Intel Corporation
- *
- * Template for [IORT] ACPI Table (static data table)
- * Format: [ByteLength] FieldName : HexFieldValue
- */
-[0004] Signature : "IORT" [IO Remapping Table]
-[0004] Table Length : 0000010C
-[0001] Revision : 00
-[0001] Checksum : BC
-[0006] Oem ID : "HISI "
-[0008] Oem Table ID : "HIP05 "
-[0004] Oem Revision : 00000000
-[0004] Asl Compiler ID : "INTL"
-[0004] Asl Compiler Revision : 20151124
-
-[0004] Node Count : 0000000A
-[0004] Node Offset : 00000034
-[0004] Reserved : 00000000
-[0004] Optional Padding : 00 00 00 00
-
-/* ITS 0, for totem */
-[0001] Type : 00
-[0002] Length : 0018
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000000
-[0004] Mapping Offset : 00000000
-
-[0004] ItsCount : 00000001
-[0004] Identifiers : 00000000
-
-/* ITS 1, for dsa */
-[0001] Type : 00
-[0002] Length : 0018
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000000
-[0004] Mapping Offset : 00000000
-
-[0004] ItsCount : 00000001
-[0004] Identifiers : 00000001
-
-/* ITS 2, m3 */
-[0001] Type : 00
-[0002] Length : 0018
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000000
-[0004] Mapping Offset : 00000000
-
-[0004] ItsCount : 00000001
-[0004] Identifiers : 00000002
-
-/* ITS 3, pcie */
-[0001] Type : 00
-[0002] Length : 0018
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000000
-[0004] Mapping Offset : 00000000
-
-[0004] ItsCount : 00000001
-[0004] Identifiers : 00000003
-
-/* mbi-gen pc, named component */
-[0001] Type : 01
-[0002] Length : 003B
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000027
-
-[0004] Node Flags : 00000000
-[0008] Memory Properties : [IORT Memory Access Properties]
-[0004] Cache Coherency : 00000000
-[0001] Hints (decoded below) : 00
- Transient : 0
- Write Allocate : 0
- Read Allocate : 0
- Override : 0
-[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 00
- Coherency : 0
- Device Attribute : 0
-[0001] Memory Size Limit : 00
-[0012] Device Name : "\_SB_.MBI0"
-[0004] Padding : 00 00 00 00
-
-[0004] Input base : 00000000
-[0004] ID Count : 00000001
-[0004] Output Base : 0000FFCC
-[0004] Output Reference : 00000034 // point to its totem
-[0004] Flags (decoded below) : 00000000
- Single Mapping : 1
-
-/* mbi-gen dsa, named component */
-[0001] Type : 01
-[0002] Length : 003B
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000027
-
-[0004] Node Flags : 00000000
-[0008] Memory Properties : [IORT Memory Access Properties]
-[0004] Cache Coherency : 00000000
-[0001] Hints (decoded below) : 00
- Transient : 0
- Write Allocate : 0
- Read Allocate : 0
- Override : 0
-[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 00
- Coherency : 0
- Device Attribute : 0
-[0001] Memory Size Limit : 00
-[0011] Device Name : "\_SB_.MBI1"
-[0004] Padding : 00 00 00 00
-
-[0004] Input base : 00000000
-[0004] ID Count : 00000001
-[0004] Output Base : 0000FFCC
-[0004] Output Reference : 0000004C
-[0004] Flags (decoded below) : 00000000
- Single Mapping : 1
-
-/* mbi-gen m3, named component */
-[0001] Type : 01
-[0002] Length : 003B
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000027
-
-[0004] Node Flags : 00000000
-[0008] Memory Properties : [IORT Memory Access Properties]
-[0004] Cache Coherency : 00000000
-[0001] Hints (decoded below) : 00
- Transient : 0
- Write Allocate : 0
- Read Allocate : 0
- Override : 0
-[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 00
- Coherency : 0
- Device Attribute : 0
-[0001] Memory Size Limit : 00
-[0011] Device Name : "\_SB_.MBI2"
-[0004] Padding : 00 00 00 00
-
-[0004] Input base : 00000000
-[0004] ID Count : 00000001
-[0004] Output Base : 0000FFCC
-[0004] Output Reference : 00000064
-[0004] Flags (decoded below) : 00000000
- Single Mapping : 1
-
-/* mbi-gen pcie, named component */
-[0001] Type : 01
-[0002] Length : 003B
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000027
-
-[0004] Node Flags : 00000000
-[0008] Memory Properties : [IORT Memory Access Properties]
-[0004] Cache Coherency : 00000000
-[0001] Hints (decoded below) : 00
- Transient : 0
- Write Allocate : 0
- Read Allocate : 0
- Override : 0
-[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 00
- Coherency : 0
- Device Attribute : 0
-[0001] Memory Size Limit : 00
-[0011] Device Name : "\_SB_.MBI3"
-[0004] Padding : 00 00 00 00
-
-[0004] Input base : 00000000
-[0004] ID Count : 00000001
-[0004] Output Base : 0000FFCC
-[0004] Output Reference : 0000007C
-[0004] Flags (decoded below) : 00000000
- Single Mapping : 1
-
- /* RC 0 */
-[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
-
-[0008] Memory Properties : [IORT Memory Access Properties]
-[0004] Cache Coherency : 00000001
-[0001] Hints (decoded below) : 00
- Transient : 0
- Write Allocate : 0
- Read Allocate : 0
- Override : 0
-[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 01
- Coherency : 1
- Device Attribute : 0
-[0004] ATS Attribute : 00000000
-[0004] PCI Segment Number : 00000001
-
-[0004] Input base : 00004000
-[0004] ID Count : 00004000
-[0004] Output Base : 00004000
-[0004] Output Reference : 0000007C
-[0004] Flags (decoded below) : 00000000
- Single Mapping : 0
-
-/* RC 1 */
-[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
-
-[0008] Memory Properties : [IORT Memory Access Properties]
-[0004] Cache Coherency : 00000001
-[0001] Hints (decoded below) : 00
- Transient : 0
- Write Allocate : 0
- Read Allocate : 0
- Override : 0
-[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 01
- Coherency : 1
- Device Attribute : 0
-[0004] ATS Attribute : 00000000
-[0004] PCI Segment Number : 00000002
-
-[0004] Input base : 00008000
-[0004] ID Count : 00004000
-[0004] Output Base : 00008000
-[0004] Output Reference : 0000007C
-[0004] Flags (decoded below) : 00000000
- Single Mapping : 0
-
-/*
-[0001] Type : 03
-[0002] Length : 005C
-[0001] Revision : 00
-[0004] Reserved : 00000000
-[0004] Mapping Count : 00000000
-[0004] Mapping Offset : 0000005C
-
-[0008] Base Address : 0000000000000000
-[0008] Span : 0000000000000000
-[0004] Model : 00000000
-[0004] Flags (decoded below) : 00000000
- DVM Supported : 0
- Coherent Walk : 0
-[0004] Global Interrupt Offset : 0000003C
-[0004] Context Interrupt Count : 00000001
-[0004] Context Interrupt Offset : 0000004C
-[0004] PMU Interrupt Count : 00000001
-[0004] PMU Interrupt Offset : 00000054
-
-[0008] SMMU_NSgIrpt Interrupt : 0000000000000000
-[0008] SMMU_NSgCfgIrpt Interrupt : 0000000000000000
-[0008] Context Interrupt : 0000000000000000
-[0008] PMU Interrupt : 0000000000000000
-*/
deleted file mode 100644
@@ -1,130 +0,0 @@
-/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
-* Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-#include "Pv660Platform.h"
-
-#include <Library/AcpiLib.h>
-#include <Library/ArmLib.h>
-#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
-#include <Library/AcpiNextLib.h>
-
-// Differs from Juno, we have another affinity level beyond cluster and core
-// 0x20000 is only for socket 0
-#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x20000 | ((ClusterId) << 8) | (CoreId))
-
-
-//
-// Multiple APIC Description Table
-//
-#pragma pack (1)
-
-typedef struct {
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16];
- EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[4];
-} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
-
-#pragma pack ()
-
-EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
- {
- ARM_ACPI_HEADER (
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
- ),
- //
- // MADT specific fields
- //
- 0, // LocalApicAddress
- 0, // Flags
- },
- {
- // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
- // GsivId, GicRBase, Mpidr)
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
- // ACPI v5.1).
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
- 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0),
- },
-
- EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4),
- {
- EFI_ACPI_6_1_GIC_ITS_INIT(0,0x8C000000), // pc
- EFI_ACPI_6_1_GIC_ITS_INIT(1,0xC6000000), // dsa
- EFI_ACPI_6_1_GIC_ITS_INIT(2,0xA3000000), // m3
- EFI_ACPI_6_1_GIC_ITS_INIT(3,0xB7000000) // pcie
- }
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Madt;
deleted file mode 100644
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2013 Linaro Limited
- *
- * All rights reserved. This program and the accompanying materials
- * are made available under the terms of the BSD License which accompanies
- * this distribution, and is available at
- * http://opensource.org/licenses/bsd-license.php
- *
- * Contributors:
- * Yi Li - yi.li@linaro.org
-*/
-
-#include <IndustryStandard/Acpi.h>
-#include "Pv660Platform.h"
-
-#define ACPI_6_1_MCFG_VERSION 0x1
-
-#pragma pack(1)
-typedef struct
-{
- UINT64 ullBaseAddress;
- UINT16 usSegGroupNum;
- UINT8 ucStartBusNum;
- UINT8 ucEndBusNum;
- UINT32 Reserved2;
-}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE;
-
-typedef struct
-{
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 Reserved1;
-}EFI_ACPI_6_1_MCFG_TABLE_CONFIG;
-
-typedef struct
-{
- EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
- EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[2];
-}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
-#pragma pack()
-
-EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
-{
- {
- {
- EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
- ACPI_6_1_MCFG_VERSION,
- 0x00, // Checksum will be updated at runtime
- {EFI_ACPI_ARM_OEM_ID},
- EFI_ACPI_ARM_OEM_TABLE_ID,
- EFI_ACPI_ARM_OEM_REVISION,
- EFI_ACPI_ARM_CREATOR_ID,
- EFI_ACPI_ARM_CREATOR_REVISION
- },
- 0x0000000000000000, //Reserved
- },
- {
-
- {
- 0x0000022000000000, //Base Address
- 0x0001, //Segment Group Number
- 0x40, //Start Bus Number
- 0x7f, //End Bus Number
- 0x00000000, //Reserved
- },
- {
- 0x0000024000000000, //Base Address
- 0x0002, //Segment Group Number
- 0x80, //Start Bus Number
- 0xbf, //End Bus Number
- 0x00000000, //Reserved
- },
- }
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Mcfg;
deleted file mode 100644
@@ -1,169 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-
-**/
-#include "Pv660Platform.h"
-DefinitionBlock (
- "SASSSDT.aml", // Output Filename
- "SSDT", // Signature
- 0x01, // SSDT Compliance Revision
- "HISI ", // OEM ID
- "SAS0", // Table ID
- EFI_ACPI_ARM_OEM_REVISION // OEM Revision
- )
-{
- External(\_SB.MBI1)
- External(\_SB.MBI3)
- Scope(_SB) {
- Device(SAS0) {
- Name(_HID, "HISI0161")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xc1000000, 0x10000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- //phy irq(0~79)
- 259,263,264,
- 269,273,274,
- 279,283,284,
- 289,293,294,
- 299,303,304,
- 309,313,314,
- 319,323,324,
- 329,333,334,
- }
-
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- //cq irq (80~111)
- 336,337,338,339,340,341,342,343,
- 344,345,346,347,348,349,350,351,
- 352,353,354,355,356,357,358,359,
- 360,361,362,363,364,365,366,367,
- }
-
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 376, //chip fatal error irq(120)
- 381, //chip fatal error irq(125)
- }
- })
-
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"interrupt-parent",Package() {\_SB.MBI1}},
- Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x0a}},
- Package () {"queue-count", 32},
- Package () {"phy-count", 8},
- }
- })
-
- OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
- Offset (0x338),
- CLK, 32,
- CLKD, 32,
- Offset (0xa60),
- RST, 32,
- DRST, 32,
- Offset (0x5a30),
- STS, 32,
- }
-
- Method (_RST, 0x0, Serialized)
- {
- Store(0x7ffff, RST)
- Store(0x7ffff, CLKD)
- Sleep(1)
- Store(0x7ffff, DRST)
- Store(0x7ffff, CLK)
- Sleep(1)
- }
- }
-
- Device(SAS1) {
- Name(_HID, "HISI0161")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xb1000000, 0x10000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- //phy irq(0~79)
- 259,263,264,
- 269,273,274,
- 279,283,284,
- 289,293,294,
- 299,303,304,
- 309,313,314,
- 319,323,324,
- 329,333,334,
- }
-
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
- {
- //cq irq (80~111)
- 336,337,338,339,340,341,342,343,
- 344,345,346,347,348,349,350,351,
- 352,353,354,355,356,357,358,359,
- 360,361,362,363,364,365,366,367,
- }
-
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
- {
- 376, //chip fatal error irq(120)
- 381, //chip fatal error irq(125)
- }
- })
-
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"interrupt-parent",Package() {\_SB.MBI3}},
- Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
- Package () {"queue-count", 32},
- Package () {"phy-count", 8},
- }
- })
-
- OperationRegion (CTL, SystemMemory, 0xB0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
- Offset (0x318),
- CLK, 32,
- CLKD, 32,
- Offset (0xa18),
- RST, 32,
- DRST, 32,
- Offset (0x5a0c),
- STS, 32,
- }
-
- Method (_RST, 0x0, Serialized)
- {
- Store(0x7ffff, RST)
- Store(0x7ffff, CLKD)
- Sleep(1)
- Store(0x7ffff, DRST)
- Store(0x7ffff, CLK)
- Sleep(1)
- }
- }
-
- }
-
-}
deleted file mode 100644
@@ -1,51 +0,0 @@
-/** @file
- Differentiated System Description Table Fields (DSDT)
-
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-
-**/
-#include "Pv660Platform.h"
-
-DefinitionBlock (
- "SATASSDT.aml", // Output Filename
- "SSDT", // Signature
- 0x01, // DSDT Compliance Revision
- "HISI ", // OEM ID
- "SATA", // Table ID
- EFI_ACPI_ARM_OEM_REVISION // OEM Revision
- )
-{
-External(\_SB.MBI3)
-Scope(_SB) {
- Device (AHCI)
- {
- Name(_HID, "HISI0001") // HiSi AHCI
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xb1002800, 0x00000B00)
- Memory32Fixed (ReadWrite, 0xb1000000, 0x00002800)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 382 }
- })
-
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"interrupt-parent",Package() {\_SB.MBI3}}
- }
- })
- }
-
-}
-
-}
deleted file mode 100644
@@ -1,64 +0,0 @@
-/** @file
-* Serial Port Console Redirection Table (SPCR)
-*
-* Copyright (c) 2012 - 2015, Linaro Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-#include <Library/AcpiLib.h>
-#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
-#include "Pv660Platform.h"
-
-EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
- //Header;
- ARM_ACPI_HEADER(
- EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
- ),
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //InterfaceType;
- {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, //Reserved1[3];
- //BaseAddress;
- {
- EFI_ACPI_6_1_SYSTEM_MEMORY,
- 32,
- 0,
- EFI_ACPI_6_1_BYTE,
- FixedPcdGet64(PcdSerialRegisterBase)
- },
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //InterruptType;
- 0, //Irq;
- 349, //GlobalSystemInterrupt;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, //BaudRate;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //Parity;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //StopBits;
- 0, //FlowControl;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //TerminalType;
- EFI_ACPI_RESERVED_BYTE, //Language;
- 0xFFFF, //PciDeviceId;
- 0xFFFF, //PciVendorId;
- 0, //PciBusNumber;
- 0, //PciDeviceNumber;
- 0, //PciFunctionNumber;
- 0, //PciFlags;
- 0, //PciSegment;
- EFI_ACPI_RESERVED_DWORD //Reserved2;
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Spcr;
Drop Pv660 source code and remove the Pv660 name as D02 is now dropped. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <ming.huang@linaro.org> --- Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 2 +- Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf | 2 +- Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf | 58 -- Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf | 56 -- Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf | 48 - Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf | 57 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf | 60 -- Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h | 36 - Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h | 93 -- Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h | 239 ----- Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h | 346 ------- Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h | 30 - Silicon/Hisilicon/Pv660/Include/Library/SerdesLib.h | 120 --- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h | 48 - Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c | 94 -- Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c | 442 --------- Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c | 103 -- Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c | 1048 -------------------- Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.c | 114 --- Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c | 119 --- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 94 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl | 88 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 38 - Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl | 38 - Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 29 - Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 956 ------------------ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl | 86 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl | 181 ---- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl | 136 --- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 67 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 93 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 96 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 274 ----- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 130 --- Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 80 -- Silicon/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 169 ---- Silicon/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 51 - Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 64 -- 38 files changed, 2 insertions(+), 5783 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel